(19) Japan Patent Office (JP)
`
`(12) Japanese Unexamined Patent
`Application Publication (A)
`
`(11) Japanese UnexaminedPatent
`Application Publication Number
`2000-305532
`(P2000-305532A)
`
`(54) Int. Cl.’
`GO09G3/36
`GO2F 1/133
`G09G3/20
`
`Identification codes
`
`575
`622
`623
`641
`
`FI
`G09G 3/36
`GO02F 1/133
`G09G 3/20
`
`(43) Publication date: November 2, 2000 (11.2.2000)
`
`Themecodes (reference)
`20093
`5C006
` 5C080
`
`575
`622
`623
`641
`
`L
`x
`H
`
`Request for examination: Not yet requested Number of claims: 3 OL (Total of 9 pages) Continued on the last page
`
`(21) Application number
`
`(22) Date of application
`
`Japanese Patent
`Application Hi t-
`116722
`
`April 23, 1999
`(4.23.1999)
`
`
`
`(71) Applicant
`
`(72) Inventor
`
`(72) Inventor
`
`(74) Agent
`
`000005 108
`Hitachi Ltd.
`4-6 Kandasurugadai, Chiyoda-ku, Tokyo
`
`Tatsuo NAGATA
`Hitachi Video & Information System, Inc.
`292 Yoshida-cho, Totsuka-ku, Yokohama-shi,
`Kanagawa
`Takaaki MATONO
`Hitachi Video & Information System, Inc.
`292 Yoshida-cho, Totsuka-ku, Yokohama-shi,
`100078134
`Patent Attorney Kenjiro TAKE
`
`Continued on the last page
`
`(54) (TITLE OF THE INVENTION) IMAGE PROCESSING DEVICE
`
`[FIG. 1]
`
`A2ehRA
`
`
`
`(57) (ABSTRACT)
`(PROBLEM) To provide an image processing device which
`uses a liquid crystal panel as an optical shutter and 1s
`capable of image display having uniform lightness without
`brightness irregularities or color irregularities.
`(MEANS FOR SOLVING) Selectors 21
`and 22 select a
`horizontal offset value H; supplied from a horizontal offset
`value input terminal Ty¢ and a vertical offset value V;
`supplied froma vertical offset value input terminal Tyo by
`high-order three-bit signals of a horizontal discrete value
`HC and a vertical discrete value VC_respectively
`introduced from a horizontal discrete value input terminal
`T,, and a vertical discrete value input terminal T,,, and
`both offset values are added by an adder 23. The added
`value is outputted by an offset generating circuit 2 as an
`offset signal OF to an adder 8, where it 1s addedto a dither
`pattern signal DP outputted from a dither pattern generating
`circuit used for multi-gradation display and outputted to an
`adder 9. It is then added to an image signal IM supplied to
`an image signal input terminal T;,, and outputted from a
`display image signal output terminal T,, as a display image
`signal ID.
`
`BREi
`
`STa
`
`SCRE
`3 He
`
`
`
`
`
`
`AnFC
`
`

`

`Japanese Unexamined Patent Application Publication 2000-305532
`
`(SCOPE OF THE PATENT CLAIMS)
`(CLam 1) An image display device which performs image
`processing on a sampled and quantized digital image signal
`and outputs it as a display image signal of a liquid crystal
`display device;
`wherem a display screen 1s divided into a plurality of
`regions in the vertical direction, and an offset value
`predetermined for each region 1s added to formsaid display
`image signal.
`(CLAM2) An image processing device according to claim
`1, wherein additional data adding processing is performed
`to add additional data of a dither pattem, which is
`determined by respectively assigning irregular additional
`data to each pixel of unit pixel groups formed byarbitrarily
`combining a plurality of pixels, to the image signal of each
`pixel for each of said unit pixel groups.
`(CLam3) An image processing device according to claim
`1, wherein said offset values are determined by adding
`horizontal offset values and vertical offset values selected
`from a plurality of predetermined horizontal offset values
`in the horizontal direction of the display screen and a
`plurality of vertical offset values in the vertical direction of
`the displayscreen.
`(DETAILED DESCRIPTION OF THE INVENTION)
`(0001)
`(TECHNICAL FIELD OF THE INVENTION) The present invention
`relates to an image processing device used when producmg
`images or the like for a personal computer (abbreviated as
`"PC" hereafter) or for television on a liquid crystal display
`device such as a liquid crystal image projection device or a
`liquid crystal rear image projection TV.
`(0002)
`(Prror ART) In an image display device such as a liquid
`crystal
`image projection device or a liquid crystal rear
`image projection TV,the following two types of techniques
`are typically used when performing multi-gradation display
`of an image on the screen. Spectfically, one technique 1s the
`frame
`rate
`control method
`(abbreviated as
`"FRC"
`hereafter), and the other is the dither method. FRC is a
`technique for implementing two-level grayscale display by
`
`for each
`switching the display gradation of each pixel
`frame. The dither method is a technique for increasing the
`number of gradations when displaying an image as a one-
`unit Image by assembling a plurality of pixel groups and
`quantizing them by overlaying pseudo-random numbers
`over the display gradations of each pixel. Technologyfor
`temporally and spatially implementing gradation control by
`combining the FRC and dither methods has been disclosed,
`for example,
`in "Digital Signal Processing for Images"
`(Takahiko Fukinuki, The Nikkan Kogyo Shimbun, Ltd., p.
`236, 237, May 1981) or Japanese Unexamined Patent
`Application Publication H5-108033.
`(0003) FIG. 9 is a circuit diagram showing a grayscale
`image processing circuit of a conventional example. An
`image signal
`IM inputted from an image signal
`input
`terminal T;,, is added to a dither pattern signal DP created
`bya dither pattern generating circuit 1 by an adder 9 so that
`the display gradation is increased, and it is outputted to a
`display image signal output terminal Tj, as a display mage
`signal.
`(0004) In the dither pattern generating circuit 1, in order to
`perform image processing on the image signal IM using
`FRC and the dither method, the least significant bit of a
`horizontal discrete value HC synchronized which is
`inputted from a horizontal discrete value input terminal T),,
`and is synchronized with the video signal IM, the least
`significant bit value of a vertical discrete value VC imputted
`from a vertical discrete value input terminal T,,, and the
`second least significant bit value of a frame discrete value
`FC inputted from a frame discrete value input terminal Ty
`are subjected to logical operations by XOR gates 11, 12,
`and 13 so that a dither pattern signal DP having a pattern
`that is inverted with the frame period 1s created.
`(0005) The dither pattern signal DP created by the dither
`pattern generating circuit
`| changes as follows as one-
`image unit data in accordance with the respective timing of
`the horizontal direction,
`the vertical direction, and the
`frame period with respect to the image signal IM inputted
`from the image signal input terminal Tj.
`
`Whenthe second least significantbit value of the frame discrete value 1s 0
`0, 3 (first line)
`2, 1 (second Ime)
`When the secondleast significant bit value of the frame discrete value 1s 0
`3, 0(first line}
`1, 2 (secondline)
`dither pattern signals DP are repeatedly inverted due to
`changes in the period of the frame discrete value FC is also
`showntogether with the input video signals IM (blackened
`chestnut shape) and the dither pattern signals DP CA, #).
`(0007) In this way, by inverting the dither pattem signals
`DP with the frame period and focusing attention on the
`same pixels, the human faculty of sight can be made to
`sense the dither pattern signal DP of (0, 3) or (2, 1) as a
`brightness level of 1.5 corresponding to the grayscale
`brightness on average. That
`is, gradations under
`the
`minimum value levels with output gradation of (0.5,
`(140.5), (2+0.5), and (3+0.5) can be displayed. As a result,
`it is possible to output an inputted image signal IM after
`converting it to a display image signal ID which enables a
`substantially greater degree of gradation display than the
`gradation that can be expressed at the time of input.
`
`The idea of inverting the dither pattern signal DP each time
`the secondleast significant bit of the frame discrete value
`FC changes periods to (0, 1) is knowledge for extending the
`usage life of the liquid crystal panel, andit typically cycles
`with a four-frame period.
`(0006) FIG. 10 is a characteristic diagram showing the
`image data conversion characteristics of multi-gradation
`display using the dither method. In the figure, (a) shows the
`output gradation obtained by adding dither pattern signals
`DP of even numbered lines to the input image signals IM of
`1-16 gradations, and (b)
`shows
`the output gradation
`obtained by dither pattern signals DP of odd numbered
`lmes. The output signals shown in FIG. 10 show examples
`of cases in which the level of gradation is 2 bits less than
`the numberofgradations ofthe input video signals, and the
`mean gradation (©) of the output signals when the added
`
`

`

`Japanese Unexamined Patent Application Publication 2000-305532
`
`(0008)
`(PROBLEM TO BE SOLVED BY THE INVENTION) The image
`display device of the conventional example described
`above is used as a necessary device of a liquid crystal
`image projection device which displays an image display
`signal ID by having a liquid crystal panel fulfill the role of
`a shutter for transmitting or blocking light. Incidentally,
`there are characteristics m which the amount of light and
`the wavelength of light change depending on the angle at
`which light are incident on the liquid crystal panel when
`light from a light source is reflected by a reflecting mirror.
`Therefore, there 1s the problem that, even for signals of the
`same amplitude at the point when image display signals ID
`are outputted from the image signal processing circuit
`system, a difference in brightness or unevenness
`in
`lightness
`in the display image may arise due to the
`respective display position on the right side, center,
`left
`side, upper side, or bottom side of the display screen. This
`is a phenomenon which 1s generally called brightness
`irregularity or color irregularity, and it has become an issue
`which absolutely must be addressed in the product
`development of a liquid crystal image projection device or
`a liquid crystal rear image projection TV.
`(0009) The present
`invention was conceived in order to
`solve the problem ofthe prior art, and its purpose is to
`provide an image processing device which uses a liquid
`crystal panel as an optical shutter and is capable of image
`display having uniform lightness without bnghtness
`irregularities or color irregularities.
`(0010)
`(MEANS FOR SOLVING THE PROBLEM) In order to solve the
`problem described above, a display screen is divided into a
`plurality of regions i the vertical direction, and an offset
`value predetermined for each region is added to form the
`display image signal, and preferably, additional data adding
`processing is performed to add additional data of a dither
`pattern, which is determined by respectively assigning
`irregular additional data to each pixel of unit pixel groups
`formed by arbitrarily combining a plurality of pixels, to the
`image signal of each pixel for each of the unit prxel groups.
`(0011)
`(EMBODIMENTS OF THE INVENTION) Embodiments showing
`concrete realizations of the present
`invention will be
`described in detail heremafter with reference to the
`drawings.
`1 is an image processing circuit diagram ofa
`(0012) FIG.
`first embodiment ofthe present invention. In the drawing, 2
`is an offset generating circuit which generates an offset
`signal OF of a predetermined offset value added to an
`image signal IM for each unit region resultmg from the
`division of a display screen into a plurality of regions, 21
`and 22 are selectors for respectively selecting one value
`from among a plurality of horizontal offset values Hi and
`vertical offset values Vj, 23 is an adder which adds the
`horizontal offset values Hi and the vertical offset values Vj
`outputted fromthe selectors 21 and 21, and Tyop and Tyopare
`respectively horizontal offset value imput
`terminals and
`vertical offset value input terminals into which a plurality
`of horizontal offset values Hi and vertical offset values Vj
`are inputted. Parts which are the same as or can be
`considered the same as those of the conventional example
`
`are labeled with the same symbols, and their redundant
`explanations will be omitted here.
`(0013) Next,
`the operation of this embodiment will be
`described. A dither pattern signal DP is generated as the
`least significant bit and the second least significant bit
`values of the respective discrete values of the horizontal
`direction,
`the vertical direction, and the frame period
`synchronized with an image signal IM, which are inputted
`from a horzontal discrete value input
`terminal T,,, a
`vertical discrete value input
`terminal T,,, and a frame
`discrete value input terminal T,, are inputted into the dither
`pattern generating circuit 1. The dither pattern signal DP
`generating operation of the dither pattern generating circutt
`1 does not differ from that of the conventional example, so
`its redundant explanation will be omitted here.
`(0014) The offset generating circuit 2 generates an offset
`signal OF of a predetermined offset value to be added to
`the
`input
`image
`signal
`IM of
`each unit
`region
`corresponding to the display position m the display screen
`where the display image signal
`ID is displayed. The
`respective input signals HO, H1, H2, ..., and H7, which are
`outputted from a microcomputer or the like for image
`quality adjustment not shown in the figure and provide
`prescribed offset values corresponding to display positions
`in the horizontal direction, are inputted into the eight
`horizontal offset value input terminals T,,; of the selector
`21. Sumilarly, the respective input signals V0, V1, V2,
`...,
`and V7, which are outputted from a microcomputer or the
`like and provide prescribed offset values corresponding to
`display positions in the vertical direction, are inputted into
`the eight vertical offset value input terminals T,o¢ of the
`selector 22. High-order three-bit data of the horizontal
`discrete values HC and the vertical discrete values VC
`inputted into the respective horizontal discrete value input
`terminal T;,, and vertical discrete value input terminal T,,
`are inputted into the selectors 21 and 22 as control signals.
`(0015) The selector 21 is controlled by the high-order
`three-bit data of the horizontal discrete values HC supplied
`to the horizontal discrete value input terminal T),. so that it
`selects one of the eight horizontal offset values Hi G=0,...,
`7) inputted into the horizontal offset value mput terminals
`Thor In this embodiment, the high-order three bits of the
`horizontal discrete value HC are supplied to the control
`terminal of the selector 21, so the offset value outputted
`from the selector 21 successively switches to HO, H1!, H2,
`..., and H7) as the high-order three bits of this horizontal
`discrete value HC change from the minimum value to the
`maximum value. As a result of the switching operation of
`this selector 21, the respectively selected offset values HO,
`H1, H2,..., and H7 are supplied to the adder 23 for each of
`the regions resultmg fromthe division of the display image
`into eight equal intervals in the horizontal direction.
`(0016) The operation of the selector 22 is the same as that
`of the selector 21. As a result of the switching operation of
`the selector 22 in which the high-order three bits of the
`vertical discrete value VC are supplied as a control signal,
`the respectively selected vertical offset values Vj (j=0,...,
`7) are supplied to the adder 23 for each of the regions
`resulting from the division ofthe display image into eight
`equal intervals in the vertical direction.
`(0017) The adder 23 adds the horizontal offset values Hi
`
`

`

`Japanese Unexamined Patent Application Publication 2000-305532
`
`outputted by the selector 21 and the vertical offset values
`Vj outputted bythe selector 22? and outputs the results to an
`adder 8 as an offset signal OF. The adder 8 adds the dither
`pattern signal DP generated bythe dither pattern generating
`circuit | and the offset signal OF outputted bythe adder 23
`and outputs the result to an adder 9. The adder 9 adds the
`image signal
`IM supplied from an image signal
`input
`terminal Tj, and the dither pattern signal DP + the offset
`signal OF outputted from the adder 8 and outputs the result
`to a display image signal output terminal Tig as a display
`image signal ID.
`(0018) FIG. 2 is an explanatory diagram showing concrete
`examples of the horizontal offset values Hi and vertical
`offset values V} outputted by the selectors 21 and 22 and
`the values of the offset signal OF generated by the offset
`generating circuit 2 for each region of the display screen,
`wherein (a) shows the horizontal offset values Hi outputted
`from the selector 21 at each ofthe display positions of the
`regions Al, A2, A3, ..., and AS resulting fromthe division
`of the display screen into eight regions im the horizontal
`direction, (b) showsthe vertical offset values Vj outputted
`from the selector 22 at each of the display positions of the
`regions Bi, B2, B3,
`..., B8 resulting from the division of
`the display screen imto eight
`regions m the vertical
`direction, and (c) showsthe offset values (Hi+V}) resulting
`from the addition of the horizontal offset values Hi and the
`vertical offset values Vj outputted from the adder 23 at
`each of the display positions of the regions Ay,, Ay, Aja,
`.., Ags resulting from dividing the display screen into
`(8x8)=64 regions. The specific numerical values of the
`horizontal offset values Hi and the vertical offset values Vj
`merely showa single example, and the numerical values do
`not have anyspecial meaning.
`(0019) FIG. 3 is an explanatory diagram showing the
`values of the dither pattern signal DP generated by the
`dither patter generating circuit | in association with each
`pixel of the display screen, and FIG. 4 is an explanatory
`diagram showingthe values of[the dither pattern signal DP
`+ the offset signal OF] outputted from the adder 8 in
`association with each pixel of the display screen. In FIG. 4,
`(a) partially shows the values of[the dither pattem signal
`DP + the offset signal OF] of each of the pixels in region
`Ay, (b) partially shows the values of [the dither pattern
`signal DP + the offset signal OF] of each of the pixels in
`region Ay,, and (c) partially shows the values of[the dither
`pattern signal DP + the offset signal OF] of each of the
`prxels m region Aj.
`(0020) The dither pattern signals DP shown in FIG. 3 are
`an example of the dither pattern described above for the
`case in which (2 horizontal dots x 2 vertical lines) were
`designated as one block. As described above, the values of
`the offset signals OF added to the dither pattern signals DP
`shown in FIGS. 4 (a), (b), and (c) are the values ofthe
`offset signals OF of regions Ay;, Ayg, and Ay; shown in
`FIG. 2 (c), so these values are respectively OF=40, 20, and
`10. As is clear from FIG. 2, in this embodiment, the degree
`ofgradation is adjusted so that the image signals IM ofthe
`pixels of the regions Ajg, Aoz, Azg,
`.., and Ag; on the
`diagonal
`line connecting the upper right corner and the
`lowerleft corner of the display screen are not adjusted, the
`degree of gradation 1s
`increased for pixels in regions
`positioned farther from the diagonal line toward the upper
`
`the degree of gradation is
`left corner, and, conversely,
`reduced for pixels of regions at positions farther from the
`diagonal line toward the lower night corner.
`(0021) In this way,
`in the present invention, the signals
`undergomg gradation adjustment corresponding to the
`display position of the display screen are added to the
`image signals IM simultaneously with the multi-gradation
`resulting from dither processing used conventionally, so tt
`is possible to achieve uniform image display with corrected
`brightness irregularities and color irregularities in a liquid
`crystal display device even if, for example, the light source
`is disposed at a position close to the lower right comer.
`(0022) Moreover, in this embodiment, an example of a case
`im whichdither pattern signals DP are generated using pixel
`data (3, 2, 1, 0) for (2 horizontal dots = 2 vertical lines) as
`one group was described, but the present invention is not
`limited to this example, and the size of one group can be set
`to any combination of numerical values. Further, the dither
`pattern signals DP were created using combinations of
`XORgates, but any generationcircuits may be used.
`(0023) In addition, it 1s not absolutely necessary to divide
`the positions of the display screen for performing display
`gradation adjustment
`into equal
`intervals, and it may
`actually be preferable to divide the positions into uneven
`intervals in order to appropriately handle the light reflection
`and the light transmittance characteristics of the reflecting
`mirror or
`the liquid crystal panel.
`In such cases,
`the
`horizontal discrete values HC and the vertical discrete
`values VC respectively mputted into the horizontal discrete
`value input terminal T,, and the vertical discrete value
`input
`terminal T,, should be decoded and the control
`signals inputted into the selectors 21 and 22 should beset
`to values which enable the division of the screen into
`regions at desired positions. Further, it is not necessary to
`limit the horizontal offset values Hi and the vertical offset
`values Vj respectively inputted into the honzontal offset
`value input terminals Tj,.¢ and the vertical offset value input
`terminals Tyo- of the selectors 21 and 22 to eight inputs, and
`values of [0 to the number of horizontal pixels of the
`display panel] (for example, 1280 and 1024 in the case of
`an SXGA panel or 1024 and 768 in the case of an XGA
`panel) may be used.
`(0024) FIG. 5 is an image processing circuit diagram of a
`second embodiment of the present
`invention.
`In the
`drawing, 3
`is a horizontal offset generating circuit which
`selects and outputs respective horizontal offset values Hi
`for each of the regions Ai resulting from the division of a
`display screen into eight regions in the horizontal direction
`in accordance with the horizontal discrete values HC
`supplied to the horizontal discrete value input terminal T,,,
`4 is a vertical offset generating circuit which selects and
`outputs respective vertical offset values VC for each of the
`regions Bi resulting from the division of a display screen
`into eight regions in the vertical direction in accordance
`with the horizontal discrete values VC inputted into the
`vertical discrete value input terminal T,,, and 7 is an adder
`which adds the horizontal offset values Hi supplied from
`the horizontal offset generating circuit 3 and the vertical
`offset values Vj supplied fromthe vertical offset generating
`circuit 4.
`(0025) In addition, 311, 312, ..., 318, 411, 412, .., 418 are
`decoding circuits which output high-level signals when the
`
`

`

`Japanese Unexamined Patent Application Publication 2000-305532
`
`results of combining the horizontal discrete values HC and
`the vertical discrete values VC are respectively "O", "1", ..,
`and "7", Symbols 321, 322, ..., 328, 421, 422, .., and 428
`are AND gates which assume the logical product of the
`respective decoding circuits 311, 312, ..., 318, 411, 412, ...,
`and 418 and the horizontal offset values Hi and the vertical
`offset values Vj, and 33 and 43 are OR gates which assume
`the logical sums of the AND gates 321, 322,
`..., and 328
`and the AND gates 421, 422,
`.., and 428, respectively.
`Parts which are the same as or can be considered the same
`as those of the first embodiment are labeled with the same
`symbols, and their redundant explanations will be omitted
`here. This will also hold true m the explanations of the
`embodiments below.
`(0026) Next,
`the operation of this embodiment will be
`described with regard to only the points which differ from
`the first embodiment. The decader circuits 311, 312..., 318,
`Ali, 412,
`..., and 418 respectively decode the horizontal
`discrete values HC and the vertical discrete values VC and
`output low-level signals to the AND gates 321, 322, ...,
`328, 421, 422,
`..., and 428 if the results of decoding are
`respectively "0", "1", ..., and "7".
`(0027) The AND gates 321, 322, ..., 328, 421, 422, ..., and
`428 output the horizontal offset values Hi and the vertical
`offset values Vj supplied by a microcomputer or the like
`from the horizontal offset value input terminals T,,., and the
`vertical offset value input terminals T,,; as they are when
`the outputs of the respective decoding circuits 311, 312, ...,
`318, 411, 412,
`.... and 418 are at a high level and output a
`horizontal offset value (vertical offset) value of 0 when the
`outputs are at a low level. The OR gates 33 and 43
`respectively assume and output the logical sums of AND
`gates 321, 322, .... and 328 and the AND gates 421, 422,...,
`and 428. The adder 7 adds the horizontal offset values Hi
`outputted by the horizontal offset generating circuit 3 and
`the vertical offset values Vj outputted by the vertical offset
`generating circuit 4 and supplies the results to the adder 8
`as offset signals OF.
`the intervals of the eight
`(0028)
`In this embodiment,
`divisions with varying offset values in the horizontal and
`vertical directions of the display screen correspond to the
`results of decoding by the decoding circuits 311, 312, ...,
`318, 411, 412, .., and 418, so the intervals of division ofthe
`display screen are not necessarily limited to equal intervals
`and may be set arbitrarily. The fact that the number of
`divisions of the display screen can be set arbitrarily is the
`sameas in the case of the first embodiment.
`(0029) FIG. 6 is an image processing circuit diagram ofa
`third embodiment of the present invention. In the drawing,
`5 is an offset generating circuit which generates an offset
`signal OF providing an offset value corresponding to the
`display position in the horizontal and vertical directions of
`the display screen, 51, 52,
`..., and 58 are selectors which
`select and output the offset values in two-dimensionally
`divided regions in the horizontal and vertical directions of
`the display screen in accordance with their horizontal
`positions, 59 is a selector which selects and outputs the
`offset values respectively selected by the selectors 51, 52,
`.., 58 m accordance with their vertical positions, and Tyg
`represents offset value input terminals mto whichthe offset
`values G, J) G=0,
`..., 7) and G=0,
`..., 7) when the display
`
`screen is respectively divided mto eight regions in the
`horizontal
`and vertical directions
`(=64 divisions) are
`inputted.
`.... and 58 select and output
`(0030) The selectors 51, 52,
`one of the respective eight offset values g, 0), (k, 1), 1, 2),
`.., and (q, 7) which are set corresponding to the two-
`dimensionally (88) divided regions of the display screen
`and are supplied to the offset value input terminals Tyg in
`accordance with the values of the high-order three bits of
`the horizontal discrete values HC supplied from the
`horizontal discrete value input terminal T,,. The selector 59
`selects and outputs one of the offset values G, 0), (k, 1), C1,
`2), .... and (q, 7) which are respectively outputted fromthe
`selectors 51, 52, ..., and 58 in accordance with the values of
`the high-orderthree bits of the vertical discrete values VC
`supplied from the vertical discrete value input termimal T,,..
`(0031) In this embodiment, as described above, the offset
`values (i, j), Which are supplied to the offset value input
`terminals T,, and are set corresponding to the two-
`dimensionally (8x8) divided regions Aj, can be set
`arbitrarily in accordance with differences in brightness or
`unevenness in lightness arising due to the display position
`onthe liquid crystal screen, for example, soit 1s possible to
`implement
`more
`precise
`lightness
`adjustments
`corresponding to the display positions on the liquid crystal
`screen. FIG. 7 is an explanatory diagram showing a
`concrete example ofthe offset values (1, 1) of each of the
`divided regions Aj im the case in which the display screen
`1s divided into 88 regions. In the concrete example shown
`in the drawing, the offset values (1, }) of each ofthe divided
`regions Aj are coincidentally the same as the offset values
`(Hi+-Vj) outputted from the
`adder 23
`in the
`first
`embodiment, but
`these numerical values can be set
`arbitrarily, as described above. The numberofdivisions of
`the display screen and the intervals of the divisions may
`also be determined arbitrarily.
`(0032) FIG. 8 is a signal processing circuit diagram of a
`fourth embodimentof the present invention. In the drawing,
`6 is
`a ROM which stores offset values
`(4,
`J)
`set
`corresponding to the two-dimensionally (8x8) divided
`regions A; of a display screen, and T,, 1s a page switching
`input termmal for inputting page switching signals which
`switch the pages of the offset values stored in the ROM6.
`The page switching signals inputted into the page switching
`input terminal T,; are supplied from a microcomputer or the
`like. Offset values corresponding to two-dimensional
`coordinate positions
`in
`the horizontal
`and
`vertical
`directions of the display screen are stored in the ROM6 in
`advance. Groups of 64 of these offset values of a plurality
`ofpatterns are stored for each page.
`(0033) By respectively leading the high-order three bits of
`a vertical discrete value VC inputted into the vertical
`discrete value input terminal T,, to the high-order address
`terminal of the ROM 6 and the high-order three bits of a
`horizontal discrete value HC inputted mto the horizontal
`discrete value mput terminal T;, to the low-order address
`terminal and using them as readout signals, it is possible to
`make
`the
`adder
`8
`and
`output offset
`signals OF
`corresponding to the two-dimensional coordinates at the
`divided regions A,
`resulting from the division of the
`display image ito 8x8 regions mthe horizontal and vertical
`
`

`

`directions. When performing lightness adjustments with
`different patterns in the display screen, by switching and
`inputting the page switching signals inputted into the page
`switching input terminal T,,,
`it
`is possible to read out
`groupsofoffset values of different patterns from the ROM
`6 and output themas offset signals OF.
`(0034) In this embodiment, the ROM 6 1s configured so
`that it stores offset values for 8x8 wards, but the present
`invention is not necessarily limited to this example.
`Theoretically, it is possible to employ a configuration m
`which rt stores (0 to the number of horizontal display
`pixels) x (0 to the numberofvertical display pixels) offset
`values, and a large-capacity device may also be used to
`store 12801024 words m the case of an SKGA panel or
`1024768 words in the case of an XGA panel, for example.
`Moreover, a configuration respectively using the high-order
`three-bit data of the horizontal discrete values HC and the
`vertical discrete values VC to control the ROM addresses is
`employed, but this is merely one example, andit is possible
`to employ any division method for dividing the display
`screen in the horizontal and vertical directions. Further, if
`the number ofbits of an image signal IM is n, for example,
`the ROM6 can store a maximum of 2n pages worth of
`offset values.
`aforementioned
`in the
`(0035) As described above,
`embodiments, offset values OF corresponding to the
`coordinate positions of the display screen can be added to
`the image signals IM and outputted concurrently with the
`multi-gradation performed based on dither processing used
`for the grayscale image processing of image signals IM, so
`it is possible to display an image having uniform lightness
`by correcting the brightness
`irregularities and color
`irregularities of the liquid crystal display device.
`(0036)
`(EFFECT OF THE INVENTION) As described above, according
`to the invention of claim 1, a display screen 1s divided into
`a plurality of regions inthe vertical direction, and an offset
`value predetermined for each region is added to form the
`display image signal, so rt 1s possible to display an image
`having a unttorm concentration with no brightness
`irregularities or color irregularities with respect to an image
`of the same gradation of the liquid crystal display device,
`evenif the amount of light or the wavelength of light varies
`depending on differences in the angle of incidence of
`irradiated light at the respective display positions.
`(0037) According to the invention of claim 2, additional
`data adding processing is performed to add additional data
`of a dither pattern, which is determined by respectively
`assigning irregular additional data to each pixel of unit
`pixel groups formed byarbitrarily combining a plurality of
`pixels, to the image signal of each pixel for each ofthe unit
`pixel groups, so it 1s possible to display an image with a
`uniform concentration with respect to an image ofthe same
`gradation
`concurrently with multi-gradation
`display
`required for the liquid crystal display device.
`
`Japanese Unexamined Patent Application Publication 2000-305532
`
`the offset
`(0038) According to the mvention of claim 3,
`values are determined by adding horizontal offset values
`and vertical offset values sel