Trials@uspto.gov
`571-272-7822
`
`Paper: 7
`Entered: October 20, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`NVIDIA CORPORATION,
`Petitioner,
`
`Vv.
`
`SAMSUNG ELECTRONICS CO., LTD,
`Patent Owner.
`
`Case IPR2015-01068
`Patent 7,804,734 B2
`
`Before KEVIN F. TURNER, BEVERLY M. BUNTING,and
`JON B. TORNQUIST,Administrative Patent Judges.
`
`TORNQUIST,Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 CFR. § 42.108
`
`
`571-272-7822
`
`Paper: 7
`Entered: October 20, 2015
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`NVIDIA CORPORATION,
`Petitioner,
`
`Vv.
`
`SAMSUNG ELECTRONICS CO., LTD,
`Patent Owner.
`
`Case IPR2015-01068
`Patent 7,804,734 B2
`
`Before KEVIN F. TURNER, BEVERLY M. BUNTING,and
`JON B. TORNQUIST,Administrative Patent Judges.
`
`TORNQUIST,Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 CFR. § 42.108
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`I. INTRODUCTION
`
`A. Background
`
`NVIDIA Corporation (“Petitioner’’) filed a Petition (Paper 2, “Pet.”)
`
`requesting inter partes review of claims 1, 3, 7-9, 12-15, 17, and 19 of U.S.
`Patent No. 7,804,734 B2 (Ex. 1001, “the °734 patent’). Samsung
`
`Electronics Co., Ltd. (“Patent Owner”) filed a Preliminary Response (Paper
`6, “Prelim. Resp.”) to the Petition.
`Wehavejurisdiction under 35 U.S.C. § 314(a), which provides that an
`
`inter partes review maynotbeinstituted “unless .
`
`.
`
`. there is a reasonable
`
`likelihood that the petitioner would prevail with respect to at least 1 of the
`claims challenged in the petition.” For the reasons given below, we
`
`determine that Petitioner has demonstrated a reasonable likelihood of
`
`prevailing with respect to claims 1, 3, 7-9, 12-15, 17, and 19 of the ’734
`
`patent. Accordingly, we authorize an inter partes review to be instituted as
`
`to these claims on the groundsset forth below.
`
`B. Related Proceedings
`
`The parties inform us that the ’734 patent is the subject of a Petition
`
`for inter partes review in IPR2015-01135 and an investigation before the
`
`International Trade Commission: Certain Graphics Processing Chips,
`Systems ona Chip, and Products Containing the Same, 337-TA-941
`(USITC). Pet. 2; Paper 5, 2. Petitioner also identifies petitions for inter
`partes review in IPR2015-01062 andIPR2015-01065 as related to the
`current proceeding. Pet. 2.
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`C. The ’734 Patent
`
`The ’734 patent discloses a data strobe buffer, and a memory system
`
`containing the same, that can be interfaced to different types of
`
`semiconductor memory devices. Ex. 1001, 1:15-19.
`
`In one embodimentof the ’734 patent, the data strobe buffer may
`
`operate in different modes based on the type of memory device to which the
`
`data strobe buffer is interfaced. Jd. at 4:28-29. In this embodiment, during
`
`a read operation in a first mode, the data strobe buffer receives a data strobe
`
`signal, comparesthis signal with a reference voltage Vref, and outputs a new
`
`data strobe signal based on the results of the comparison. Id. at 4:32-37.
`
`Conversely, during a read operation in a second mode,the data strobe buffer
`
`receives a data strobe signal and passesthis signal without comparing it with
`
`the reference voltage Vref. Jd. at 4:44-48. According to the’734 patent, the
`
`first mode maybe an operating mode ofthe data strobe buffer when the data
`strobe buffer interfaces with Double-Data-Rate (DDR) Synchronous
`Dynamic Random Access Memory (SDRAM)andthe second mode may be
`
`an operating mode ofthe data strobe buffer when the data strobe buffer
`
`interfaces with Mobile Double-Data-Rate (MDDR) SDRAM./d. at 1:21-
`
`28, 4:37-39, 4:48-51, 5:13-16, 5:25-30, Figs. 3A, 3B.
`
`D. Illustrative Claims
`
`Ofthe challenged claims, claims 1 and 17 are independent. Claims 1
`
`and 3 areillustrative of the challenged claims and are reproducedbelow:
`
`1. A data strobe buffer comprising:
`
`a first input/output node;
`a first driver coupled to the first input/output node, the first
`driver configured to output a first data strobe signal to the
`first input/output node during a write operation; and
`
`3
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`a first receiver coupled to receive a second data strobe signal
`from the first
`input/output node and output a third data
`strobe signal during a read operation when the data strobe
`' buffer is
`in a first or second mode,
`the first
`receiver
`configured to compare the second data strobe signal with a
`first reference voltage and output a result of the comparison
`as the third data strobe signal when the data strobe buffer is
`in the first mode,
`the receiver further configured to not
`compare the second data strobe signal with the first
`reference voltage when the data strobe buffer is in the
`second mode.
`
`Ex. 1001, 8:27-42.
`3. The data strobe buffer of claim 1, wherein the first driver
`includes:
`
`a pull-up transistor, a first side of the pull-up transistor coupled
`to a power supply voltage, a second side of the pull-up
`transistor coupled to the first input/output node, the pull-up
`‘transistor configured to couple the power supply voltage to
`the first input/output node in response to a pull-up control
`signal received on a gate ofthe pull-up transistor; and
`a pull-downtransistor, a first side of the pull-down transistor
`coupled to a ground voltage, a second side of the pull-down
`transistor'coupled to the first input/output node, the pull-down —
`transistor configured to couple the ground voltage to the first
`input/output node in response to a pull-down control signal
`received on a gate of the pull-downtransistor.
`
`Id. at 8:47-62.
`
`E. The Asserted Grounds of Unpatentability
`
`Petitioner asserts the following grounds of unpatentability (Pet. 3):
`
`1. Whether claims 1, 3, 7-9, 12, 13, 17, and 19 are unpatentable
`under 35 U.S.C. § 102(e) as anticipated by Lai.’
`
`' U.S. Patent No. 7,032,092 B2, issued Apr. 18, 2006 (Ex. 1003).
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`2. Whetherclaims 3, 14, and 15 are unpatentable under
`35 U.S.C. § 103 as having been obvious over Lai and Kong.”
`
`II. ANALYSIS
`
`A. Claim Construction
`
`In an inter partes review, “[a] claim in an unexpired patent shall be
`
`given its broadest reasonable construction in light of the specification of the
`
`patent in whichit appears.” 37 C.F.R. § 42.100(b); In re Cuozzo Speed
`
`Tech., LLC, 793 F.3d 1268, 1275 (Fed. Cir. 2015). In determining the
`
`broadest reasonable construction, we presumethat claim termscarry their
`
`ordinary and customary meaning. See Jn re Translogic Tech., Inc., 504 F.3d
`1249, 1257 (Fed. Cir. 2007). This presumption may be rebutted when a
`
`patentee, acting as a lexicographer, sets forth an alternate definition of a
`term in the specification with reasonable clarity, deliberateness, and |
`precision. Jn re Paulsen, 30 F.3d 1475, 1480 (Fed. Cir. 1994).
`
`Petitioner proffers claim constructions for four terms: “coupled,”
`
`“data strobe signal,”“data strobe bar signal,” and “input/output node.” Pet.
`
`7-8. Patent Owner proposesconstructions for the terms “mode” and
`
`“input/output node.” Prelim. Resp. 8-14.
`
`Uponreview ofthe record, we determine that no claim terms need be
`
`. construed for purposesofthis decision. See Vivid Techs., Inc. v. Am. Sci. &
`
`Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“only those terms need be
`
`construed that are in controversy and only to the extent necessary to resolve
`
`the controversy.”’).
`
`2 U.S. Patent No. 7,173,871 B2, issued Feb. 6, 2007 (Ex. 1004).
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`B. Anticipation Based on Lai
`
`Petitioner contendsthat claims 1, 3, 7-9, 12, 13, 17, and 19 of the
`
`°734 patent are unpatentable under 35 U.S.C. § 102(e) as anticipated by Lai.
`
`Pet. 2449. In support ofits contention, Petitioner relies on the declaration
`testimony of Dr. Bruce Jacob (Ex. 1007). For the reasons that follow, we
`
`determine that Petitioner demonstrates a reasonable likelihood of prevailing.
`
`as to claims 1, 7-9, 12, 13, 17, and 19 of the ’734 patent. Weare not
`
`persuaded, however,that claim 3 is anticipated by Lai.
`
`1. Lai
`
`Lai is directed to a controller for supporting a plurality of memory
`types or modes.? Ex. 1003, 1:20-21, 1:54—55, 1:65-66, Abstract. Figure 9
`
`of Lai is reproduced below (annotations by Petitioner):
`
`> Lai discloses that memories having different data rates or data types
`generally require a different and separate memory controller for each data
`type. Ex. 1003, 1:48-50. According to Lai, because more memory
`controllers complicate the system and are space consuming,there is a need
`for a single memory controller that can control different memory types or
`modespresentin a single application, such as various memory types on a
`single motherboard. Jd. at 1:50-55, 8:62—9:6.
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`Centratier
`
`Writing
`
`Process
`
`Figure 9 is a preferred embodimentof the memory controller of Lai
`
`As depicted in Figure 9, memory controller 20 includes determining
`
`device 22, memory writing device 24, and memory reading device 26. Jd. at
`
`6:27-29. Clock signal generator 220 interfaces with memory controller 20
`
`and may generate a plurality of clock signals. Jd. at 6:7—11, 6:29-37,
`
`Table I.
`
`During a write operation, data selection (DQS) generator 206 selects a
`
`suitable memory clock signal for transmission to input/output node DQS.
`
`Id. at 6:54—58; Ex. 1007 4 122. During a read operation, DQSreceiver 214
`
`receives a data selection signal (DQS) from the semiconductor memory
`
`device and a memory selection signal (MSEL) from determining device 22.
`
`Depending on the contents of memory selection signal (MSEL),e.g.,
`
`whether the memory type or modeis identified as DDR SDRAM mode,
`Quad Data Rate (QDR) mode, or Quad Band Memory (QBM) mode, DQS
`receiver 214 comparesthe data selection signal (DQS) with either reference
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`voltage (VREF)or data mask signal (DQM). Jd. at 1:42-44, 6:38-48, 8:11-
`
`16; Ex. 1007 4] 126-127.
`Figure 11 of Lai is reproduced below and depicts one embodiment of
`
`.
`
`DQSreceiver 214:
`
`1004
`
`—— 1002
`
`MSEL
`FIG. 11
`
`Figure 11 is a block diagram of a second embodiment of the DQS Receiver
`Lai discloses that, if the memory type is identified by memory selection
`
`signal (MSEL) as DDR SDRAM or QBMstructure, multiplexer 1002 passes
`
`reference voltage VREFto buffer 1004 for generation ofdifferential output
`
`signal DQS I. On the other hand, if the memory typeis identified as QDR
`
`structure, multiplexer 1002 passes data mask signal (DQM)to buffer 1004
`
`for generation of differential output signal DQS I. Ex. 1003, 8:18—24; Ex.
`
`1007jf 76-78.
`
`2. Claim 1
`
`Petitioner contends that Lai discloses each limitation of claim 1. Pet.
`
`24-31. With reference to Figure 9 of Lai (as annotated by Petitioner),
`
`Petitioner identifies DQS(highlighted in blue) as the claimed “input/output
`
`node”; DQS Generator 206 and associated buffer (highlighted in green) as
`the claimed “driver”; and DQS Receiver 214 (highlighted in orange) as the
`claimed “receiver.” Jd. at 11 (citing Ex. 1007 § 74), 24-29. With reference
`
`8
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`to Figure 11 of Lai, Petitioner identifies VREF as the claimed “reference
`
`voltage” and DQS|]as the claimed “third data strobe signal.” /d. at 12
`
`(citing Ex. 1003, 8:11-18; Ex. 1007
`
`76), 29-30.
`
`Petitioner contends that the data strobe buffer of Lai is designed to
`
`compare a seconddata strobe signal with a reference voltage (VREF) when
`
`in a first mode and is designed to compare a seconddata strobe signal with
`
`data mask signal (DQM)when in a second mode. /d.'at 12, 30-31.
`
`Petitioner concludes, therefore, that the receiver of Lai is “configured to
`compare the second data strobe signal with a first reference voltage and
`
`output a result of the comparisonasthe third data strobe signal when the
`
`data strobe bufferis in the first mode”andis “further configured to not
`
`compare the seconddata strobe signal with thefirst reference voltage when
`
`the data strobe buffer is in the second mode,”as recited in claim 1.
`31,
`|
`
`/d. at 29,
`
`Patent Ownercontendsthat Lai does not anticipate claim 1 because,in
`
`contrast to the memory controller of the ’734 patent, Lai’s data strobe buffer
`
`“cannot be ‘configured’ or ‘further configured’ to operate in any other mode
`
`after it is connected to a memory device.” Prelim. Resp. 17. Patent Owner
`
`reasons that Lai’s data strobe buffer is controlled by the memory selection
`
`signal (MSEL)and,“[b]ecause the output of MSELis dictated by the type of
`
`memory connected to the receiver,” Lai’s receiver is configured to operate in
`
`only a single modefor any particular memory type, such as “DDR, QDR,
`
`and QBM memory types.” /d. at 16.
`
`Patent Owner contendsthat Lai’s single mode of operationis in
`
`contrast to the receiver of the ’734 patent, which Patent Owner contends can
`
`process“the same data strobe signal” from the same memory device in two
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`different ways. Jd. at 18-19. In support of this argument, Patent Owner
`
`refers to Figures 3A and 3B of the ’734 patent, reproduced below
`
`(highlighting by Patent Owner):
`
`110
`;
`
`FIG. 3A
`
`
`
`$< 1st MODE >
`
`< 2nd MODE >
`
`The ’734 patent describes Figure 3A as a circuit diagram depicting the
`operation ofthe data strobe buffer in a first mode. Jd. at 2:16-18. In this
`first mode, the data strobe buffer compares data strobe signal DQS_2 to
`reference voltage Vref and outputs third data strobe signal DOS3. Id. at
`4:32-37. Figure 3B is described as a circuit diagram depicting the operation
`
`of the data strobe buffer in a second mode. Ex. 1001, 2:20—22. In this
`
`second mode, data strobe signal DQS_2 is not compared to Vref. Jd. at
`
`4:44-48,.
`
`Patent Ownercontendsthat the data strobe buffer of Figures 3A and
`
`3B receives the same data strobe signal DQS_2 from the same memory,but
`
`is configured to processthis signal in two different ways based on whether
`
`the data strobe buffer is in a first or second mode. Prelim. Resp. 18-19. In
`
`describing the functionality depicted in Figures 3A and 3B, however,the
`
`’734 patent discloses that the first mode (Fig. 3A) “may be an operating
`
`10
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`modeof the datastrobe buffer 190 whenthe data strobe buffer 190
`
`interfaces with DDR SDRAM”andthe second mode (Fig. 3B) “may be an
`
`operating mode of the data strobe buffer 190 whenthe data strobe buffer 190
`
`interfaces with an MDDR SDRAM.” Ex. 1001, 4:37-39, 4:48-51. Patent
`
`Ownerdoes not persuasively explain why the disclosure of using a first
`
`modeofprocessing for DDR SDRAM and a second modeof processing for
`MDDRSDRAM disclosesor suggests applying two modesofprocessing for
`
`a data strobe signal from the same memory device.
`
`Patent Owneralso arguesthat use of the permissive language “may”
`
`to describe the memory types usedin the Figures 3A and 3B implicitly
`
`supports its argumentthat data strobe signal DQS_2 may be from the same
`memory device. Prelim. Resp. 20-21. Patent Owner does not explain
`
`persuasively, however, why the use of the term “may”in this context would
`
`suggest to one of ordinary skill in the art that data strobe signal DQS_2 may
`
`be from the same memory device, as opposed to suggesting that the first
`
`mode may be used in memory types that require the single-ended signaling
`
`scheme of Figure 3A and the second mode may be used in memory types
`
`that require the signaling schemeof Figure 3B. /d.; Ex. 1001, 1:33-39
`
`(noting that DDR SDRAM usesa single-ended type data strobe buffer).
`
`With respect to Patent Owner’s argumentthat the data strobe buffer of
`
`Lai differs from that of the ’734 patent because its mode of operation is
`
`controlled by a memory selection signal (MSEL), we note that in describing
`
`the operation of the data strobe buffer of Figures 3A and 3B, the ’734 patent
`
`discloses that reference voltage Vref may be selected “in response to a mode
`signal (not shown) indicating that the memory device 200 is DDR
`SDRAM.” Jd. at 5:13—-16. Patent Ownerdoes not explain persuasively why
`
`11
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`this method ofselecting reference voltage Vref based on a “mode signal”
`
`differs in any relevant respect from Lai’s method ofselecting reference
`
`voltage VREF based on memory selection signal (MSEL). Ex. 1003, 8:13-
`
`16 (“Based on the control of memory selection signal (MSEL), multiplexer
`
`[] selects either reference voltage VREFor data mask signal (DQM)for
`comparison with data selection signal (DQS).”).
`Based on the foregoing, and onthis record, we are not persuaded by
`
`Patent Owner’s argumentthat the ’734 patent discloses a data strobe buffer
`that will process a data strobe signal from the same memory device in two
`
`~
`
`modes. This informs our understanding of the claim terms “configured” and
`
`“further configured,” as recited in claim 1 of the ’734 patent. Thus, on this
`
`record, we find persuasive Petitioner’s argument that Lai’s data strobe
`
`buffer, which can process an incomingdata strobe signal in a first or second
`
`mode depending on a memory selectionsignal, is “configured” and “further
`
`configured,” as recited in claim 1.
`
`Based on the foregoing, we are persuadedthat Petitioner has
`
`presented sufficient evidence and argument to demonstrate a reasonable
`
`likelihood of prevailing on its assertion that claim 1 of the ’734 patentis
`
`anticipated by Lai.
`
`3. Claims 3, 7-9, 12, 13, 17, and 19 ofthe ’734 patent
`
`Petitioner, supported by the testimony of Dr. Jacob, provides detailed
`
`analysis showing where Petitioner contends each limitation of claims 7-9,
`
`12, 13, 17, and 19 of the ’734 patent is disclosed in Lai. Pet. 31-49; Ex.
`
`1007 {f 131-159. Patent Owner does not provide contentions regarding the
`
`additional limitations recited in challenged claims 7-9, 12, 13, 17, and 19.
`
`12
`
`
`
`IPR2015-01068
`Patent 7,804,734 B2
`
`Upon review of Petitioner’s arguments, evidence, and the supporting
`
`testimony of Dr. Jacob, we are persuaded that Petitioner has set forth
`
`sufficient argument and evidenceto establish a reasonable likelihood of
`
`prevailing with respect to anticipation of claims 7-9, 12, 13,17, and 19 of
`
`.
`
`the ’734 patent by Lai. Petitioner presents no analysis or evidence, however,
`
`to support its assertion that Lai anticipates claim 3 of the ’734 patent.
`
`Indeed,as discussed below, Petitioner concedes that Lai does not disclose
`every limitation of claim 3. Pet. 49-54. Accordingly, on this record, we are
`
`not persuaded by Petitioner’s contention that Lai anticipates claim 3 of the
`
`°734 patent.
`
`C. Obviousness of Claims 3, 14, and 15 — Lai and Kong
`
`Petitioner contends claims 3, 14, and 15 of the ’734 patent are
`
`unpatentable under 35 U.S.C. § 103 in view of Lai and Kong. Pet. 49-55.
`
`For the reasonsthat follow, we determine Petitioner has demonstrated a
`
`reasonable likelihood of prevailing as to these challenged claims.
`
`1. Kong
`
`Kong discloses a semiconductor memory device containing at least
`| two circuits for inputting and outputting data in association with a data
`strobe signal. Pet. 15 (citing Ex. 1004, 1:14-18). Figure 3 of Kongis
`
`reproduced below:
`
`
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`IPR2015-01068
`Patent 7,804,734 B2
`
`
`
`Figure 3 illustrates the circuit diagrams of Kong’s data strobe
`signal input and output buffer and control circuit
`Dr. Jacobtestifies that control circuit 20-1 of Kong controlsa tri-state buffer
`
`(element 34), which drives an outgoing data strobe signal to the input/output
`
`. node. Ex. 1007 Jf 85, 86. Dr. Jacob furthertestifies that element 34 of
`
`Kongcontains a “simple pull-up transistor P2 connected between powerand
`
`the output DQS; and a.simple pull downtransistor N2 connected between
`
`ground and the output DQS.” Jd. J 87 (citing Ex. 1003, 4:57-64,Fig. 3).
`
`2. Claim 3, 14, and 15
`
`Claims 3, 14, and 15 depend,directly or indirectly, from independent
`
`claim 1, and require, inter alia,a first driver with “a pull-up transistor” and
`
`“a pull-downtransistor.” Ex. 1001, 8:47-62, 9:50-67, 10:1-18. Petitioner
`
`contends Kongdiscloses the claimedfirst driver, including the recited “pull-
`
`up” and “pull-down”transistors, and a person ofordinary skill in theart
`
`would have found it obvious to implement Kong’s driver in Lai “because the
`
`two references both address exactly the same technical topic—developing
`
`input/output buffers for bi-directional data-strobes” and “Kong simply
`
`14
`
`
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`IPR2015-01068
`Patent 7,804,734 B2
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`provides a more detailed disclosure of elements already disclosed in Lai.”
`
`Pet. 22 (citing Ex. 1007 J 93, 99, 100), 49-54.
`
`Patent Ownerdoesnotraise arguments specifically against the
`
`combination of Lai and Kong,but asserts that Kong cannot remedy the
`deficiencies of Lai with respect to claim 1. Prelim. Resp. 23-24. As noted
`
`above, however, on this record weare not persuaded that Lai fails to disclose
`
`any limitation of claim 1.
`
`Uponreview ofPetitioner’s arguments, evidence, and the supporting
`testimony of Dr. Jacob, we concludethat Petitioner hasset forth sufficient
`
`articulated reasoning with rational underpinnings to support the combination
`
`of Lai and Kong. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007).
`
`Weare persuaded,therefore, that Petitioner has established a reasonable
`
`likelihood of prevailing on its assertion that claims 3, 14, and 15 would have
`
`been obvious under 35 U.S.C. § 103 in view of Lai and Kong.
`
`I. ORDER
`
`For the foregoing reasons,itis:
`
`ORDEREDthat pursuant to 35 U.S.C. § 314 an inter partes review of
`
`the ’734 patent is hereby instituted on the following grounds:
`
`Whetherclaims 1, 7-9, 12, 13, 17, and 19 of the ’734 patent are
`anticipated under 35 U.S.C. § 102 by Lai; and
`|
`Whetherclaims 3, 14, and 15 of the ’734 patent are unpatentable
`
`under 35 U.S.C. § 103 over Lai and Kong;
`
`FURTHER ORDEREDthatthetrial is limited to the grounds
`
`identified above and no other groundsare authorized; and
`
`FURTHER ORDEREDthat pursuantto 35 U.S.C. § 314(a), inter
`
`partes review ofthe ’734 patent is hereby instituted commencing on the
`
`15
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`IPR2015-01068
`Patent 7,804,734 B2
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`entry date of this Order, and pursuant to 35 U.S.C. § 314(c) and
`
`37 C.F.R. § 42.4, notice is hereby given ofthe institution oftrial.
`
`16
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`IPR2015-01068
`Patent 7,804,734 B2
`
`PETITIONER:
`
`Bob Steinberg
`Julie Holloway
`LATHAM & WATKINS LLP
`bob.steinberg@lw.com
`Julie.Holloway@lw.com
`
`PATENT OWNER:
`
`Robert Appleby
`Gregory Arovas
`KIRKLAND & ELLIS LLP
`robert.appleby@kirkland.com
`greg.arovas@kirkland.com
`
`17
`
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