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METHOD AND SYSTEM FOR REDUCING INTER-LAYER CAPACITANCE IN INTEGRATED CIRCUITS

12/156,281 | U.S. Patent Application

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Location ELECTRONIC
Filed May 30, 2008
Examiner THUAN DO, V
Class 716
Art Group 2825
Patent No. 8,015,540
Case Type Utility - 716/010000
Status Patented Case
Parent 10/991,107 Patented
Last Updated: 4 years, 5 months ago
Date # Transaction