`
`In re patent of:
`
`Burns et 0:].
`
`Confirmation No.: 7760
`
`Art Unit: 2816
`
`Patent. No.: 7,190,219 B2
`
`Examiner: Tra, Anh Quan
`
`Issued: March 13, 2007
`
`Atty. Docket: 1875.109000A
`
`For: Extended Range Variable-Gain
`Amplifier
`
`Request for Certificate of Correction
`Under 37 C.F.R. § 1.322 and 1.323
`
`Attn: Certificate of Correction Branch
`
`Commissioner for Patents
`
`PO Box 1450
`
`Alexandria, VA 223 1 3— 145 0
`
`Sir:
`
`It is hereby requested that a Certificate of Correction under 37 CPR. §§ 1.322
`
`and 1.323 be issued for the above-captioned United States Patent. This Certificate of
`
`Correction is being requested due to mistakes which appear in the printed patent. These
`
`mistakes were made by both the US. Patent and Trademark Office and by Applicants.
`
`The mistakes made by Applicants are of a clerical or typographical nature, or of a
`
`minor character. Patentees submit that correction of these errors does not introduce new
`
`matter.
`
`Specifically,
`
`the printed patent contains the following errors for which a
`
`Certificate of Correction is respectfully requested:
`
`On the cover page, in section (63) of Related US. Application Data, “Jul 30,
`
`2001” should be replaced with --Jul. 3, 2001——. The correct filing date of priority app].
`
`No. 09/897,601 is July 3, 2001, as noted in the Application Data Sheet, filed January 20,
`
`2004.
`
`
`
`- 2 -
`
`Bums ez‘ a].
`
`Patent. No. 7,190,219 B2
`
`In Figure l, the reference number “120” that is tagged to the Up—Stream Channels
`
`should be replaced with --119--. This error is to correct an inadvertent duplication of the
`
`use of reference number 120 in the application. As can be seen in Figure 1, reference
`
`number 120 is already used for the High-Pass Filter (labeled “HPF”), which is just above
`
`and to the right of the Up-Stream Channels. To correct this duplication, the Up-Stream
`
`Channels should be labeled as 119.
`
`Similar to the afore-mentioned Figure correction, at column 2,
`
`line 54, “up-
`
`stream channels 118” should be replaced with ——up—stream channels 119——. In this part of
`
`the specification, the up-stream channels were mislabeled with number 118, which is
`
`already used by the Low—Pass Filter.
`
`At column 3,
`
`lines 48-58 should deleted and replaced with the correct
`
`corresponding paragraph [0024], which is reproduced here for convenience:
`
`—-Looking now to FIG. 3A, automatic gain control logic decoder 204 is illustrated
`
`as comprising automatic gain control amplifiers 350 and a logic circuit array 352.
`
`Automatic gain control amplifiers 350 accept automatic gain control voltage 114 and
`
`output a plurality of comparator outputs 312(n) which are routed to logic circuit array
`
`352. Logic circuit array 352 outputs the plurality of amplifier control signals. As
`
`illustrated in FIG. 3B, automatic gain control amplifiers 350 are preferably comprised of
`
`a resistor ladder 302 and thirty—five high-gain, low frequency amplifiers 306.1 through
`
`306.35, and logic circuit array 352 is preferably comprised of thirty-five logic circuits
`
`308.1 through 308.35. Resistor ladder 302 is comprised of a top resistor 303, thirty—four
`
`resistors designated as resistors 304.1 through 304.34, and a bottom resistor 305. Top
`
`resistor 303 is connected on a first side to a bias potential VDD and on a second side to a
`
`
`
`_ 3 _
`
`Burns et a].
`
`Patent. No. 7,190,219 B2
`
`first side of resistor 304.1. The connection point between top resistor 303 and resistor
`
`304.1 is node 301.1. A second side of resistor 304.1 is connected to a first side of resistor
`
`304.2 at a node 301.2. Thus it can be said that for any sequential pair of resistors 304(i)
`
`and 304(i+1) in resistor ladder 302, a second side of resistor 304(i) is connected to a first
`
`side of resistor 304(i+1) at node 301 (i+1). At the "bottom" of resistor ladder 302, a
`
`second side of resistor 304.34 is preferably connected to a first side of bottom resistor
`
`305 at node 301.35, and a second side of bottom resistor 305 is preferably connected to a
`
`ground 309. Those skilled in the relevant art(s) will understand, based on the teachings
`
`contained herein, that the second side of bottom resistor 305 could be connected to a
`
`potential other than ground without deviating from the spirit and intent of the invention.
`
`Further, the invention also covers the embodiment wherein the first side of resistor 304.1
`
`is connected directly to bias potential VDD 307, and the second side of resistor 304.34 is
`
`connected directly to ground 309.--
`
`On August 9, 2006, Applicants filed an Amendment in which an attempt was
`
`made to correct the mislabeling of up-stream channels 118 (which is noted above).
`
`However, Applicants inadvertently inserted the incorrect replacement paragraph number
`
`into the Amendment. The paragraph that should have been replaced was paragraph
`
`[0020], but Applicants inadvertently listed the paragraph number of [0024]
`
`in the
`
`Amendment. Therefore, the patent issued with incorrect text at column 3, lines 48—5 8.
`
`At column 15, line 41, a period should be inserted after “settings)”. This will
`
`correct a minor grammatical error.
`
`At column 15, line 50, a period should be inserted after “off”. This will correct a
`
`minor grammatical error.
`
`
`
`- 4 -
`
`Burns et al.
`
`Patent. No. 7,190,219 B2
`
`Remarks
`
`The above-noted corrections do not involve such changes in the patent as would
`
`constitute new matter or would require reexamination.
`
`A completed Form PTO/SB/44 accompanies this request, with the above—noted
`
`corrections printed thereon. Accordingly, a Certificate of Correction is believed proper
`
`and issuance thereof is respectfully requested.
`
`This request
`
`is accompanied by payment of the fee set forth in 37 C.F.R.
`
`§ 1.20(a). Fee payment is provided in the attached Credit Card Payment Form (PTO-
`
`2038). The Commissioner is hereby authorized to charge any fee deficiency, or credit
`
`any overpayment, to our Deposit Account No. 19—0036.
`
`Respectfully submitted,
`STERNE, KESSLER, GOLDSTEIN & Fox P.L.L.C.
`
`”M51 [MW
`
`Jeffrey T. Helvey
`Agent for Applicants
`Registration No. 44,757
`
`Date:
`
`’L ) $5 have
`
`1100 New York Avenue, NW.
`
`Washington, DC. 20005-3934
`(202) 371-2600
`
`714169_1.DOC
`
`
`
`PTO/SB/44 (04-05)
`Approved for use through 04/30/2007. OMB 0651-0033
`US. Patent and Trademark Office: US. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number
`Also Form PTO-1050
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`CERTIFICATE OF CORRECTION
`
`Page 1 of g
`
`PATENT NO:
`
`7,190,219 B2
`
`DATED:
`
`March 13, 2007
`
`INVENTORS: Burns et a1.
`
`resistor 304.1 is connected to a first side of resistor 304.2 at a node 301.2. Thus it can be said that for
`
`It is certified that error appears or errors appear in the above-identified patent and that said
`Letters Patent is hereby corrected as shown below.
`
`Cover Page
`At section (63), under Related US. Application Data, “Jul. 30, 2001” should be replaced
`with --Jul. 3, 2001—-.
`
`Drawings
`In Figure 1, please replace the up-stream channels reference number “120” with -—119--.
`
`Column 2
`
`At line 54, please replace “up-stream channels 118” with -—up-stream channels 119--.
`
`Column 3
`
`Please delete lines 48-58 and replace with the following paragraph:
`-—
`Looking now to FIG. 3A, automatic gain control logic decoder 204 is illustrated as
`comprising automatic gain control amplifiers 350 and a logic circuit array 352. Automatic gain
`control amplifiers 350 accept automatic gain control voltage 114 and output a plurality of comparator
`outputs 312(n) which are routed to logic circuit array 352. Logic circuit array 352 outputs the
`plurality of amplifier control signals. As illustrated in FIG. 3B, automatic gain control amplifiers 350
`are preferably comprised of a resistor ladder 302 and thirty-five high-gain, low frequency amplifiers
`306.1 through 306.35, and logic circuit array 352 is preferably comprised of thirty-five logic circuits
`308.1 through 308.35. Resistor ladder 302 is comprised of a top resistor 303, thirty-four resistors
`designated as resistors 304.1 through 304.34, and a bottom resistor 305. Top resistor 303 is
`connected on a first side to a bias potential VDD and on a second side to a first side of resistor 304.1.
`The connection point between top resistor 303 and resistor 304.1 is node 301.1. A second side of
`
`MAILING ADDRESS OF SENDER (Please do not use customer number below):
`1100 New York Avenue, NW
`Washington DC 20005-3934
`Atty. Dkt. No. 1875.109000A
`This collection of information is required by 37 CFR 1.322. 1.323 and 1.324. The information is required to obtain or retain a benefit by the public which is to file (and by the USPTO to
`process) an application. Confidentiality is governed by 35 U.S.C. 122 and 37 CFR 1.14. This collection is estimated to take 1.0 hour to complete, including gathering, preparing, and
`submitting the completed application form to the USPTO. Time will vary depending upon the individual case. Any comments on the amount of time you are required to complete this form
`and/or suggestions for reducing this burden, should be sent to the Chief Information Officer, US. Patent and Trademark Office. US. Department of Commerce, PO. Box 1450,
`Alexandria, VA 22313-1450. DO NOT SEND FEES OR COMPLETED FORMS TO THIS ADDRESS. SEND TO: Attention Certificate of Corrections Branch, Commissioner for
`Patents, P.0. Box 1450, Alexandria, VA 22313-1450.
`if you need assistance in completing the form. call 1-800-PTO-9199 (1300-7868199) and select option 2.
`
`714197_1.DOC
`
`PTO/SB/44 (04-05)
`
`

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