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Inventor

Cathal Phelan

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CYPRESS SEMICONDUCTOR CORPORATION SPANSION LLC

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MORGAN STANLEY SENIOR FUNDING, INC., Assignor MONTEREY RESEARCH, LLC, Assignor

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Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

09/747,790 | U.S. Patent Application

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Location FILE REPOSITORY (FRANCONIA)

Filed Dec. 22, 2000

Examiner HUAN HOANG

Class 365

Art Group 2818

Patent No. 6,363,031

Case Type Utility - 365/233000

Status Patented Case

Parent 09/433,822 Patented

Last Updated: 4 years, 7 months ago

Date	#	Transaction
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Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit

09/747,790 | U.S. Patent Application

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