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Inventor

CATHAL PHELAN

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CYPRESS SEMICONDUCTOR CORPORATION SPANSION LLC

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CYPRESS SEMICONDUCTOR CORPORATION, Assignor MORGAN STANLEY SENIOR FUNDING, INC., Assignor MONTEREY RESEARCH, LLC, Assignor

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CIRCUIT, ARCHITECTURE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYNCHRONOUS INTEGRATED CIRCUIT

09/433,822 | U.S. Patent Application

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Location FILE REPOSITORY (FRANCONIA)

Filed Nov. 3, 1999

Examiner HUAN HOANG

Class 365

Art Group 2818

Patent No. 6,166,991

Case Type Utility - 365/233000

Status Patented Case

Child 09/747,790 Patented

Last Updated: 4 years, 4 months ago

Date	#	Transaction
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CIRCUIT, ARCHITECTURE AND METHOD FOR REDUCING POWER CONSUMPTION IN A SYNCHRONOUS INTEGRATED CIRCUIT

09/433,822 | U.S. Patent Application

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