Trials@uspto.gov
`§71—272-7822
`
`Paper 11
`Entered: February 7, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`APPLEINC.,
`Petitioner,
`
`Vv.
`
`LIMESTONE MEMORYSYSTEMSLLC,
`Patent Owner.
`
`Case IPR2016-01561
`Patent 6,233,181 Bl
`
`Before BART A. GERSTENBLITH, BARBARA A. PARVIS,and
`ROBERTJ. WEINSCHENK,Administrative Patent Judges.
`
`WEINSCHENK,Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 CFR. § 42.108
`
`
`§71—272-7822
`
`Paper 11
`Entered: February 7, 2017
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`APPLEINC.,
`Petitioner,
`
`Vv.
`
`LIMESTONE MEMORYSYSTEMSLLC,
`Patent Owner.
`
`Case IPR2016-01561
`Patent 6,233,181 Bl
`
`Before BART A. GERSTENBLITH, BARBARA A. PARVIS,and
`ROBERTJ. WEINSCHENK,Administrative Patent Judges.
`
`WEINSCHENK,Administrative Patent Judge.
`
`DECISION
`Institution of Inter Partes Review
`37 CFR. § 42.108
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`I.
`
`INTRODUCTION
`
`Apple Inc. (“Petitioner’’) filed a Petition (Paper 1, “Pet.”) requesting
`
`an inter partes review of claims 3 and 5 of U.S. Patent No. 6,233,181 Bl
`
`(Ex. 1003, “the ’181 patent”). Limestone Memory Systems LLC (“Patent
`
`Owner’) filed a Preliminary Response (Paper 10, “Prelim. Resp.”) to the
`
`Petition. An inter partes review maynotbeinstituted “unless .
`
`.
`
`. there is a
`
`reasonablelikelihood that the petitioner would prevail with respect to at least
`
`1 of the claims challenged in the petition.” 35 U.S.C. § 314(a).
`
`For the reasonsset forth below, Petitioner demonstrates a reasonable
`
`likelihood of prevailing in showing the unpatentability of claims 3 and 5 of
`
`the ’?181 patent. Accordingly, we institute an inter partes review as to
`
`claims 3 and 5 of the °181 patent on the groundsspecified below.
`
`A.
`
`Related Proceedings
`
`The parties indicate that the ’181 patent is the subject of several cases
`
`in the United States District Court for the Central District of California.
`
`Pet. 1-2; Paper 4, 4-6. Thepartiesalso indicate that the following petitions
`
`for inter partes review mayberelated to this case:
`
`
`
`
`
`
`
`
`
`IPR2016-00096
`IPR2016-00097
`IPR2016-01567
`
`USS. Patent No. 6,233,181
`U.S. Patent No. 6,697,296
`US. Patent No. 5,894,441
`
`
`
`
`
`
`
`
`
`
`Pet. 2; Paper 4, 2-3.
`
`B.
`
`The ’181 Patent
`
`The ’181 patent relates to repairing defective memory cells ina
`
`semiconductor memory device. Ex. 1003, col. 1, ll. 9-13. The ’181 patent
`
`
`
`IPR2016-01561
`Patent 6,233,181 BI
`
`explains that, when a memory cell becomes defective, it can be replaced
`
`with a spare memorycell. Jd. at col. 1, ll. 15-18. According to the
`
`’181 patent, prior semiconductor memory devices contained an array of
`
`spare memory cells for each memory block in the device, and, as a result, the
`
`spare memory cells were not usedefficiently. Jd. at col. 3, 1. 58-col. 4, |. 8.
`
`To address this problem, the ’?181 patent describes a semiconductor memory
`
`device with an array of spare memory cells that can be shared among a
`
`plurality of memory blocks.
`
`/d. at col. 16, Il. 31-39.
`
`C.—Illustrative Claim
`
`Claim 3 depends from claims 1 and 2. Claims 1, 2, and 3 are
`
`reproduced below.
`
`1. A semiconductor memory device, comprising:
`
`a plurality of first memory blocks each having a plurality
`of first normal memory cells arranged in a matrix of rows and
`columns, each ofsaid plurality of first memory blocks
`including word lines provided corresponding to said rows,
`respectively, and the first memory blocksaligned in the column
`direction; and
`
`a plurality of first spare memory cells arranged in a
`matrix of rows and columnsin a particular one ofsaid plurality
`of first memory blocks, each row ofsaid plurality offirst spare
`memory cells being capable of replacing a defective row
`including a defective first normal memory cell in said plurality
`of first memoryblocks.
`
`2. The semiconductor memory deviceas recited in claim 1,
`further comprising:
`a plurality of second memory blocksarrangedalternatively
`with said plurality of first memory blocks along the column
`direction, the second memory blocks each having a plurality of
`second normal memory cells arranged in a matrix of rows and
`columns; and
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`a plurality of second spare memory cells arranged in a
`matrix of rows and columnsin a particular one ofsaid plurality of
`second memory blocks, each row ofsaid plurality of second spare
`memory cells being capable of replacing a defective row
`including a defective second normal memory cell in said plurality
`of second memory blocks.
`
`3. The semiconductor memory device as recited in claim 2,
`further comprising a plurality of sense amplifier bands provided
`between each ofsaid plurality of first memory blocks and each of
`said second memory blocks, and shared by adjacent memory
`blocks in the column direction for sensing and amplifying data in
`each column ofthe adjacent memory block including a selected
`memory cell when aclivaled.
`
`Ex. 1003, col. 45, 1. 55—col. 46, 1. 31.
`
`D.
`
`Evidence ofRecord
`
`Petitioner relies on the following references and declaration (Pet. 4):
`
`
`
`Reference or Declaration
`Declaration of Dr. Pinaki Mazumder(“Mazumder
`Declaration”
`Sukegawaet al., U.S. Patent No. 5,487,040 (issued Jan. 23,|Ex. 1005
`1996)
`(“Sukegawa”
`Fujishimaet al., U.S. Patent No. 5,267,214 (issued Nov. 30,|Ex. 1006
`1993)
`(“Fujishima”’
`Walck, U.S. Patent No. 4,967,397 (issued Oct. 30, 1990)
`“Walck”
`
`Exhibit No.
`Ex. 1001
`
`Ex. 1007
`
`E.
`
` Asserted Grounds of Unpatentability
`
`Petitioner asserts that the challenged claims are unpatentable on the
`
`following grounds(Pet. 5):
`
`
`[Claim[Basis|References
`
`35 U.S.C. § 103(a)
`Sukegawa and Fujishima
`
`
`35 U.S.C. § 103(a)
`-Sukegawa, Fujishima, and
`5
`
`
`Walck
`
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`Il.
`
`ANALYSIS
`
`A.—Claim Construction
`
`The claims of an unexpired patent are interpreted using the broadest
`
`reasonable interpretation in light of the specification of the patent in which
`
`they appear. 37 C.F.R. § 42.100(b); Cuozzo Speed Techs., LLC v. Lee, 136
`
`S. Ct. 2131, 214446 (2016). The parties agree that no claim construction is
`
`necessary at this stage of the proceeding. Pet. 6; Prelim. Resp. 18-19.
`
`Therefore, on this record and for purposes of this decision, we determine
`
`that no claim terms require express construction. See Vivid Techs., Inc. v.
`
`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999) (“[O]nly those
`
`terms need be construedthat are in controversy, and only to the extent
`
`necessary to resolve the controversy.”).
`
`B.
`
` Asserted Grounds of Unpatentability
`
`1.
`
`Obviousness of Claim 3 over Sukegawa and Fujishima
`
`Petitioner argues that claim 3 would have been obvious over
`
`Sukegawaand Fujishima. Pet. 5. We have reviewed the parties’ assertions
`
`and supporting evidence. For the reasons discussed below,Petitioner
`
`demonstrates a reasonable likelihood of prevailing in showing that claim 3
`
`would have been obvious over Sukegawaand Fujishima.
`
`Claim 3 depends from claims | and 2. Ex. 1003, col. 45, 1. 55—
`
`col. 46, 1. 31. Petitioner identifies evidence indicating that Sukegawa
`
`teaches the limitations in claims 1 and 2. Pet. 39-52. Patent Owner does
`
`not raise any specific disputes with respect to the limitations in claims 1 and
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`2.' Onthis record, Petitioner has shownsufficiently that the combination of .
`Sukegawaand Fujishima teaches the limitations in claims 1 and2.
`
`Claim 3 recites
`
`a plurality of sense amplifier bands provided between each of
`said plurality of first memory blocks and each of said second
`memory blocks, and shared by adjacent memory blocksin the
`column direction for sensing and amplifying data in each
`column of the adjacent memoryblock including a selected
`memorycell when activated.
`Ex. 1003, col. 46, Il. 24-31. Petitioner identifies evidence indicating that
`
`Fujishima teaches a plurality of sense amplifier bands provided between
`
`each ofa plurality of first memory blocks and each of a plurality of second
`
`memory blocks. Pet. 53-55 (citing Ex. 1006, Abstract, col. 1, ll. 11-14,
`
`col. 15, ll. 24-28, col. 24, Il. 26-39, col. 25, ll. 34-47, Fig. 14). Petitioner
`
`also identifies evidence indicating that the sense amplifier bands in
`
`Fujishima are shared by adjacent memory blocksin the column direction for
`
`sensing and amplifying data in each column of the adjacent memory block
`
`including a selected memory cell whenactivated. Jd. at 55-59 (citing
`
`Ex. 1006, col. 2, Il. 11-17, col. 24, Il. 35-58, col. 25, ll. 3-15, Figs. 8, 14).
`
`Patent Ownerrespondsthat neither Sukegawa nor Fujishima teaches a
`
`memory that shares sense amplifier bands and spare memory cells between
`
`different memory blocks. Prelim. Resp. 23-27. Patent Owner’s argumentis
`
`not persuasive becauseit addresses the teachings in Sukegawa and
`
`Fujishima individually, not the combination proposedby Petitioner. See In
`
`'TIn IPR2016-00096, we granted Patent Owner’s request for adverse
`judgment with respect to claims 1, 2, 4, 6, and 7 of the °181 patent. Micron
`Tech., Inc. v. Limestone Memory Sys. LLC, Case IPR2016-00096,slip op. at
`2 (PTAB Aug.3, 2016) (Paper 11).
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`re Keller, 642 F.2d 413, 426 (CCPA 1981) (“[O]ne cannot show non-
`
`obviousness by attacking references individually where,as here, the
`
`rejections are based on combinations of references.”). Specifically,
`
`Petitioner argues that Sukegawateaches replacing defective memorycells in
`
`one memory block with spare memorycells from another memory block
`
`(Pet. 46-47), and Fujishima teaches sharing sense amplifier bands between
`
`adjacent memory blocks (id. at 53-59). Thus, on this record, Petitioner has
`
`shown sufficiently that the combination of Sukegawa and Fujishima teaches
`
`the limitations in claim 3.
`
`Petitioner argues that it would have been obvious to combinethe cited
`
`teachings in Sukegawaand Fujishima. Pet. 59-63. Specifically, Petitioner
`
`argues that Sukegawaand Fujishimarelate to the same field of endeavor,
`
`namely the design and architecture of dynamic random access memory
`
`(“DRAM”). Jd. at 59 (citing Ex. 1005; Ex. 1006). Further, according to
`
`Petitioner, Fujishima teaches that there are several benefits to using shared
`
`sense amplifier bands, such as providing accurate sensing of small memory
`
`cells, reducing parasitic capacitance ofbit lines associated with memory
`
`cells, reducing power consumption, and increasing production yield. Jd. at
`
`61 (citing Ex. 1006, col. 1, ll. 27-42, col. 1, ll. 47-50, col. 2, Il. 4-9, col. 13,
`
`ll. 24-26). Petitioner identifies evidence indicating that a person of ordinary
`
`skill in the art would have recognized that the benefits of the shared sense
`
`amplifier bands in Fujishima would improve the memory in Sukegawa. Id.
`
`(citing Ex. 1001 J] 46, 141). Petitioner also identifies evidence indicating
`
`that “there would have been no undueobstacle” to combining the cited
`
`teachings in Sukegawaand Fujishima. Jd. at 62 (citing Ex. 1001 4 143).
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`Patent Owner respondsthat Petitioner has not shownsufficiently that
`
`it would have been obvious to combine the cited teachings in Sukegawa and
`
`Fujishima. Prelim. Resp. 27-44. First, Patent Owner arguesthat the
`
`additional references mentionedin the Petition teach away from the
`
`proposed combination of Sukegawa and Fujishima. /d. at 28-35. Patent
`
`Ownerspecifically points out that none of the additional references
`
`mentionedin the Petition teach a memorythat shares sense amplifier bands
`
`and spare memory cells between different memory blocks. Jd. We are not
`
`persuaded, though, that a person ofordinary skill in the art would have been
`discouraged from combiningthe cited teachings in Sukegawa and Fujishima
`
`simply becausePetitioner does not identify a single reference that discloses
`
`each ofthe limitations of claim 3.
`
`Patent Owneralso points out that the Horiguchi reference (Ex. 1009)
`mentionedin the Petition states“that inter-subarray replacement(to replace
`
`a defective normalline in a subarray by a spare line in another subarray)
`
`should be avoided in DRAM redundancy, because of the cumbersome
`
`control of memory-array associated circuitry, especially the sense circuit.”
`
`Prelim. Resp. 30 (quoting Ex. 1009, 1-2) (emphasis omitted); id. at 40. In
`
`other words, Horiguchiindicates that replacing a defective memory cell in
`
`one memory block with a spare memory cell from another block can be
`
`cumbersome. Ex. 1009, 1-2. In contrast, though, Sukegawa expressly
`
`encourages using this type of memory cell replacement. Pet. 46; Ex. 1005,
`
`col. 2, ll. 21-59. Thus, on this record, we are not persuaded that Horiguchi
`
`would have discouraged a person ofordinary skill in the art from using the
`
`memory cell replacement in Sukegawa or from combiningit with the shared
`
`sense amplifier bands in Fujishima.
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`Second, Patent Ownerarguesthat“the Petition makes no showing that
`
`Sukegawacould tolerate the complication added by implementing the shared
`
`sense amplifier design from Fujishima.” Prelim. Resp. 36 (citing Ex. 1006,
`
`col. 24, 1. 65-col. 25, 1. 14, Fig. 14); id. at 27-28. In particular, Patent
`
`Ownercontendsthat “the bit line selecting switches BS would haveto be
`
`reconfigured to enable sense amplifiers associated with the spare wordlines,
`
`which might, as disclosed in Sukegawa, reside in separate memory blocks.”
`
`Id. at 36. On this record, Patent Owner’s argumentis not persuasive. As
`
`discussed above,Petitioner identifies evidence indicating that “there would
`
`have been no undueobstacle” to combining the cited teachings in Sukegawa
`
`and Fujishima. Pet. 62 (citing Ex. 1001 4 143). Further, even assuming,as
`
`Patent Ownercontends, that the bit line selecting switches in Sukegawa
`
`would haveto be reconfigured to accommodate the shared sense amplifier
`
`bands in Fujishima, Patent Ownerdoesnot identify specific evidence
`
`indicating that doing so would have been beyondthe level of ordinary skill
`
`in the art. See Prelim. Resp. 36-37.
`
`Third, Patent Ownerarguesthat “[e]ach of the motivations offered by
`
`the Petition is premised on the argumentthat the concepts taught both in
`
`Sukegawa and Fujishima were well-known,” but “[jJust because elements
`
`are well knowndoes not establish that such elements would be obviously
`
`combined by oneof ordinary skill in the art.” Prelim. Resp. 37. On this
`
`record, Patent Owner’s argumentis not persuasive. Petitioner does more
`
`than just argue that the concepts in Sukegawaand Fujishima were well
`
`known. Asdiscussed above,Petitioner identifies evidence indicating that
`
`there are benefits to using the shared sense amplifier bands in Fujishima, and
`
`that a person of ordinary skill in the art would have recognized that the
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`benefits of the shared sense amplifier bands in Fujishima would improvethe
`
`memory in Sukegawa. Pet. 61 (citing Ex. 1001 ff 46, 141; Ex. 1006, col. 1,
`
`I]. 27-42, col. 1, ll. 47-50, col. 2, Il. 4-9, col. 13, Il. 24-26).
`
`Fourth, Patent Owner arguesthat “[t]he Petition cites several general
`
`benefits of the shared sense amplifier design but does not explain how these
`
`general benefits would relate ‘particularly’ to the memory disclosed by
`
`Sukegawa.” Prelim. Resp. 41. On this record, Patent Owner’s argumentis
`
`not persuasive. Petitioner identifies evidence indicating that the specific
`
`benefits provided by the shared sense amplifier bands in Fujishima would
`
`have been “particularly useful” to the memory in Sukegawa. Pet. 61-62
`
`(citing Ex. 1001 4 142; Ex. 1005, col. 3, Il. 4-15, col. 3, ll. 25—32,
`
`col. 3, ll. 51-53).
`
`Lastly, Patent Ownerarguesthat Petitioner does not address the
`
`objective indicia of nonobviousness. Prelim. Resp. 43. Specifically, Patent
`
`Ownerarguesthat the earliest possible filing date of the ?181 patent is six
`
`years after the earliest possible filing date of Sukegawa. Id. Thus,
`
`according to Patent Owner,“there existed a long felt need that had not been
`accommodated bythe ordinary skill in theart.” Id. Onthis record, Patent
`Owner’s argumentis not persuasive. Patent Owner does notidentify
`
`specifically what need had not been accommodated, and Patent Owner does
`
`not identify specific evidence indicating that any such need had been
`
`recognized by those of ordinary skill in the art. See id.
`
`For the reasons discussed above,Petitioner demonstrates a reasonable
`
`likelihood of prevailing in showing that claim 3 would have been obvious
`
`over Sukegawaand Fujishima.
`
`10
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`2.
`
`Obviousness of Claim 5 over Sukegawa, Fujishima, and
`Walck
`
`Petitioner argues that claim 5 would have been obvious over
`
`Sukegawa, Fujishima, and Walck. Pet. 5. We have reviewedthe parties’
`
`- assertions and supporting evidence. For the reasons discussed below,
`
`Petitioner demonstrates a reasonable likelihood ofprevailing in showingthat
`
`claim 5 would have been obvious over Sukegawa, Fujishima, and Walck.
`
`Claim 5 depends from claim 3, and recites “wherein said plurality of
`
`first memory blocks,said plurality of second memory blocks and said
`
`plurality uf sense amplifier bands form a first memory array, and said
`
`semiconductor memory device further comprises: a second memory array
`
`having a same arrangementas the first memory array.” Ex. 1003, col. 46,
`
`ll. 36-43. Petitioner identifies evidence indicating that the combination of
`
`Sukegawaand Fujishima teaches several memory arrays, each of which
`
`includesa plurality of first memory blocks, a plurality of second memory
`
`blocks, and a plurality of sense amplifier bands. Pet. 64-65 (citing
`
`Ex. 1005, col. 1, Il. 39-43, Fig. 1; Ex. 1006, col. 24,ll. 35—36). On this
`
`record, Petitioner has shownsufficiently that the combination of Sukegawa,
`
`Fujishima, and Walck teaches the abovelimitation of claim 5.
`
`Claim 5 further recites wherein said semiconductor memory device
`
`further comprises
`
`control circuitry for driving one memory blockfrom thefirst
`and second memory arraysinto a selected state in a normal
`operation mode, and for simultaneously driving a prescribed
`number of memoryblocks from each of said first and second
`memory arrays into a selected state in a particular operation
`mode.
`
`11
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`Ex. 1003, col. 46, Il. 44-50. Petitioner identifies evidence indicating that
`
`Walck teaches control circuitry that drives a particular memory block during
`
`a normal operating mode, such as a READ/WRITEoperation. Pet. 67-68
`
`(citing Ex. 1007, col. 1, Il. 44-46,col. 1, Il. 57-67, col. 2, Il. 8-10,col. 8,
`
`ll. 18-26). Petitioner also identifies evidence indicating that the control
`
`circuitry in Walck simultaneously drives the memoryblocksin all the
`
`memory arrays during a memory refresh mode. /d. at 69 (citing Ex. 1007,
`
`col. 1, ll. 47-48,col. 1, Il. 57-67, col. 2, Il. 10-13, col. 8, lI. 26-29). On this
`record, Petitioner has shown sufficiently that the combination of Sukegawa,
`Fujishima, and Walck teaches the above limitation of claim 5.
`
`Petitioner argues that it would have been obvious to combinethe cited
`
`teachings in Walck with the cited teachings in Sukegawa and Fujishima. Id.
`
`at 70-71. Specifically, Petitioner argues that, like Sukegawa and Fujishima,
`
`Walck relates to the design and architecture of DRAM.
`
`/d. at 70 (citing
`
`Ex. 1007, col. 1, 1. 11-col. 2, 1. 32). Petitioner identifies evidence indicating
`
`that a person of ordinary skill in the art would have recognized that the
`
`control circuitry in Walck would be useful for a memory that has multiple
`
`banks, such as the memory in Sukegawa. Jd. at 70 (citing Ex. 1001 ¥ 154;
`
`Ex. 1007, col. 7, 1. 45—col. 8, 1. 9). Petitioner also identifies evidence
`
`indicating that “there would have been no undueobstacle” to combining the
`
`control circuitry in Walck with the cited teachings in Sukegawa and
`
`Fujishima. Jd. at 70-71 (citing Ex. 1001 4 154). On this record, Petitioner
`
`has shown sufficiently that it would have been obvious to combinethe cited
`
`teachings in Walck with the cited teachings in Sukegawa and Fujishima.
`
`Patent Ownerrelies on the same arguments discussed above with
`
`respect to claim 3. Prelim. Resp. 44. For the reasons discussed above, on
`
`12
`
`
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`IPR2016-01561
`Patent 6,233,181 Bl
`
`this record, Patent Owner’s arguments are not persuasive. See supra
`
`Section II.B.1. Therefore, Petitioner demonstrates a reasonable likelihood of
`
`prevailing in showing that claim 5 would have been obvious over Sukegawa,
`
`Fujishima, and Walck.
`
`IW.
`
`CONCLUSION
`
`Petitioner demonstrates a reasonable likelihood of prevailing in
`
`showing the unpatentability of claims 3 and 5 of the 7181 patent. Atthis
`
`stage in the proceeding, we have not madea final determination with respect
`
`to the patentahility of any of the challenged claims.
`
`IV. ORDER
`
`In consideration of the foregoing,it is hereby:
`
`ORDEREDthat, pursuant to 35 U.S.C. § 314(a), an inter partes
`
`review is hereby instituted as to claims 3 and 5 of the 7181 patent on the
`
`following grounds:
`
`A.
`
`Claim 3 as obvious over Sukegawa and Fujishima under 35
`
`U.S.C. § 103(a); and
`
`B.
`
`Claim 5 as obvious over Sukegawa, Fujishima, and Walck
`
`under 35 U.S.C. § 103(a);
`
`FURTHER ORDEREDthat, pursuant to 35 U.S.C. § 314(a), an inter
`
`partes review of the ’181 patent is hereby instituted commencing on the
`
`entry date of this Order, and, pursuant to 35 U.S.C. § 314(c) and 37 C.F.R.
`
`§ 42.4, notice is hereby given ofthe institution ofa trial; and
`
`FURTHER ORDEREDthatthetrial is limited to the grounds
`
`identified, and no other groundsare authorized.
`
`13
`
`
`
`IPR2016-01561
`Patent 6,233,181 Bl
`
`PETITIONER:
`
`John R. Hutchins
`Rose Cordero Prey
`Michael N. Zachary
`ANDREWS KURTH KENYON LLP
`jhutchins@kenyon.com
`roseprey@andrewskurthkenyon.com
`michaelzachary@andrewskurthkenyon.com
`
`PATENT OWNER:
`
`Nicholas T. Peters
`Paul B. Henkelmann
`FITCH EVEN TABIN & FLANNERY LLP
`ntpete@fitcheven.com
`phenkelmann@fitcheven.com
`
`14
`
`
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