`
`B 355 - Qos
`
`+4
`
`COMMUNICATION CONTROL SYSTEM
`
`BACKGROUND OF THE INVENTION
`
`1.
`
`Field of the Invention
`
`This invention relates to subsystems communications and more particularly to a
`
`subsystem communication control system.
`
`2.
`
`Discussion of the Prior Art
`
`
`
`
`Many computers and electronic systems handle complex processes by dividing a
`
`given process into subprocesses and using different elements of the system
`(“subsystems”) simultaneously to execute respective subprocesses. To coordinate this |
`
`type of distributed processing, the subsystemsare typically interconnected by a
`
`communications “bus”or busses, and are provided with interface circuits for enabling
`
`communications of commands and data. Thus, in a distributed processing systern, one
`
`subsystem performsits task and communicates the result to another subsystem, and so
`
`on, until the entire process has been completed.
`
`Subsystem interconnections may have any of several configurations
`
`(“topologies”) including one or moreserial and/or parallel busses and multiple bus
`
`|
`subdivisions (“sub-busses”). Address and data bus-lines can be separate (“non-
`multiplexed”) or shared (“multiplexed”). The term “bus” herein refers to a linear bus
`
`20
`
`topology, whichis a parallel, multiplexed or non-multiplexed bus of continuouslines
`which are designated for certain kinds of connections to subsystems. An example of such
`
`a busis the typical personal computer (“PC”) configuration illustrated by Fig. 1. PC bus
`
`
`
`101 interconnects processor 120, memory 130, host video I/O controller 140, host audio
`
`V/O controller 150, user-I/O controller 160 (for connecting user interface control devices.
`
`such as a keyboard and/or mouse) and system expansion interface 170. A secondary bus
`
`102 connects video I/O controller 140 to monitor 145, and another secondary bus 103
`
`connects system expansion interface 170 to other subsystems, not shown.
`
`Overall communication-flow (“bus traffic”) is typically controlled by designated
`
`bus-master subsystems capable ofinitiating communications to each other and to slave
`
`subsystems capable only of responding to communications.
`Conventional master subsystems control communications among subsystems ona
`
`communication-by-communication basis. A bus having only one communications
`
`pathway allows only one communication at a time and therefore, before attempting to-
`
`communicate over a one-path bus, a master must wait until the bus is not being used.
`
`Then, since at any time more than one master might attempt a communication,the
`
`requesting master must acquire exclusive control of the bus. When the bus becomes
`
`available, the master typically begins arbitration by communicating a message over the
`
`bus requesting control of the bus. If no other master is communicating a similar request,
`
`then the requesting master may initiate communication. Conflicting contemporaneous
`
`requests can be resolved using typically a combination of predeterminedprioritization
`and first-come-first-served criteria to allocate the bus to a prevailing master. Thus,
`arbitration times are often unpredictable and, with many contemporaneously requesting
`masters, can be long.
`|
`
`A master, having acquired control of a bus,typically initiates a transfer by issuing
`
`a command which includes the address of a slave that is to send or receive data. If the
`
`
`
`20
`
`
`
`slave is available, then it begins sending or receiving. Otherwise, the master generally
`
`waits for the slave to become available. Alternatively, if another capable slave exists, the
`
`master may attemptto utilize it. Typically, however, the master must yield control of
`
`_
`
`the bus and then request control anew. If meanwhile other masters have begun requesting
`a
`
`control of the bus, then all the masters must conduct an arbitration. Once communication
`
`is initiated with a slave, there are few limitations on the length of time utilized for the
`
`communication, and meanwhile any other subsystems requesting communications must.
`
`wait. Communicationitself is typically conducted by a master by addressing a slave and
`
`transferring data on a word-by-wordbasisin orderto clearly identify the intended data
`
`recipient.
`
`Conventional subsystem-directed communications, as described thus far, are well
`
`matched to the needs of conventional personal computers (“PCs”) and other less complex
`
`systems. The Personal Computer Interface (“PCI’’) bus of a conventional PC, for
`
`example, supports essentially predictable communication. Typically, since each ofthe
`
`three or four subsystems supported performs a unique function in an essentially
`
`repetitious manner, a subsystem sendsdata resulting from a given type of processing to
`
`the same next-subsystem. For example, a PC-based sound-processing subsystem
`repeatedly sends processed sound-data to the same audio-controller for output. Thus,
`
`
`
`subsystem communication control by masters according to predetermined and fixed
`priorities is sufficient. PCs also do not typically require or provide for the highly robust
`
`20
`
`responsesofreal-time systems. Thus, the potentially substantial delays associated with
`
`waiting for an available bus, seeking control ofthe bus,arbitration and waiting for an
`
`
`
`uninterruptable slave have been acceptable, as have delays associated with word-based
`
`transfer controls typically directed by the master.
`
`Unfortunately, delays inherent to master-slave systems may be unacceptable in
`
`systems requiring more robust responses, such as real-time systems. To make matters
`
`worse, communication patterns are far less predictable in more complex systems, and
`
`designation of masters and predetermined priority-criteria becomeless effective in
`
`coordination of subsystems as the number and complexity of the subsystems increase.
`
`As the numberof subsystemsincreases, the possibility that an equal or higher-priority
`
`master might monopolize the bus increases and the possibility of time-consuming
`
`arbitration also increases. Other delays inherent to master-slave systemsarealso likely to
`
`be magnified as system complexity increases. Additionally, master subsystemsare highly
`
`complex and use expensive components.
`
`Thus, there is a need for a dynamic, robust, flexible and well-coordinated means
`
`for directing subsystem communications.
`
`SUMMARY OF THE INVENTION
`
`
`
`
`
`The present invention provides a dynamic, robust, flexible and well-coordinated
`
`meansfor directing subsystem communications. The invention comprises a centralized
`
`subsystem communication controller that allocates communication resources and
`
`20
`
`conducts subsystem communications according to dynamic system needs.
`
`In a preferred embodiment, a system communication controller (“coordinator”) is
`
`coupled via a main control bus and other connections to each subsystem,andis also
`
`connected to a host PC for user control and monitoring. The coordinatorassigns time-
`
`
`
`sharing communications “channels” to selected subsystem pairs and then,utilizing the
`
`main control bus and dedicated control connections, dynamically and interruptably
`
`enables assigned communication channels. In further accordance with the preferred
`embodiment, a dynamic memory access (“DMA”) type communicationis utilized.
`
`Preferably, the coordinator monitors communications and limits message-lengths, thereby
`
`leaving an integral coordinator processor free for other tasks.
`
`Advantageously, the use of a dedicated and centralized subsystem
`
`‘communications controller maximizes responsiveness to system requirements while
`
`minimizing system cost. The centralized coordinatoris better equipped than individual
`
`non-dedicated subsystem masters to dynamically apportion available communication
`
`resources according to ongoing user control, known system parameters and ongoing
`
`communications monitoring.
`
`Further advantage is gained through avoidance of unnecessary delays. The
`
`combined use of a channel assignment, dedicated controllines, independently monitored
`
`DMAtransfers and dynamic decision making by the coordinator provides immediate,
`
`interruptable and switchable accessto the bus.
`
`These and other advantages and benefits of the present invention will become
`
`apparent from the drawings and specification that follow.
`
`
`
`
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`Fig. 1 is block diagram showing the functional elements of a conventionalhost
`
`personal computer;
`
`Fig. 2 is a functional block diagram showing subsystems and interconnectionsof a
`
`video system in accordance with the invention, including its connection to the host
`
`personal computerofFig.1;
`
`Fig. 3 is a flowchart of method steps for providing subsystem addresses in
`
`accordance with the invention;
`
`Fig. 4 is a detailed block diagram showing subsystem communication control
`
`functions and interconnections in accordance with the invention; and
`
`Fig. 6 is a flowchart of method steps for dynamic communication channel
`
`assignment and monitoring of subsystem communication accordingto the invention.
`
`DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
`
`Fig. 2 shows how subsystem communication requirements are met according to
`
`the present invention in an independently operable audio-video processing system
`
`(“video system”) 200 having a peripheral connection 103 to host PC 100.
`Video system 200 isa modular, re-configurable and expandable system of
`elements needed for real-time mixing and/or processing of one or more audio and/or video
`data input streams. Video data streams supplied by external video sourcesare, for
`
`example, input through respective I/O control subsystems (not shown), then pre-
`
`processed (not shown) to provide a consistent internally-utilized format and then
`
`communicated over video bus 209 for individual and/or combined-stream (“mixed”)
`
`
`
`20
`
`
`
`processing. Actual processing varies from addingtitles and splicing video segments to
`
`animation, video effects and virtual-world type enhancement. Video system 200 also
`provides sophisticated audio and time-locked audio-video processing.
`|
`
`Video system 200 comprises subsystems including coordinator 240, video
`
`processing subsystems “video card-1” 250 through “video card-N” 260, switcher 270,
`
`and interconnections including main control bus 201, communications“enable”lines 203
`
`and video bus 209. Video card-1 250 through video card-N 260 manipulate the video
`
`data. Additionally, a peripheral communication link 103 to system expansion interface
`
`170 of PC 100 provides use of PC-based resources for user control, downloading and
`
`audio-video previewing.
`
`Operation of video system 200 is centrally monitored and controlled by
`
`coordinator 240 according to user audio-video manipulation selections and other input
`
`received through connection 103 from host PC 100 system expansion interface 170.
`
`Coordinator 240 provides for subsystem address assignment, busutilization and other
`
`subsystem communications and control functionsthat utilize main control bus 201.
`
`Coordinator 240 also controls operation of switcher 270, which in turn directs audio and
`
`video data flow over video bus 209.
`
`
`
`
`
`aye
`
`Video system 200 real-time performance and overall flexibility at a minimized cost
`are achieved in several ways. Many subsystems, including the video cards (c.g., video
`
`20
`
`card-1 250, video card-N 260), are socketed such that subsystems can easily be added or
`
`replaced. Another example is that many video cards and other subsystems provide
`
`programmable audio-video processing functionality. Thus, maximized functionality is
`
`provided by continuously maximizedutilization of available subsystems. A further
`
`
`
`example is that while the numberof bus-linesis limited to minimize cost, use of available
`
`bus throughput is maximized throughefficient and dynamically assignable bus utilization
`by coordinator 240,
`
`Subsystem addresses allow directing communications to and from specific
`
`subsystems. While video card-1 250 to video card-N 260 each receive all communications
`
`over shared main control bus 201, the video cards decode only communications including
`
`their address.
`
`The Fig. 3 flowchart, with reference to Fig. 2, illustrates how during system reset
`
`
`
`' a unique addressis statically assigned to each subsystem. In step 310, coordinator 240
`
`polls a first card slot for the presence of a subsystem card. If in step 320 a card is found
`
`in the first slot, then in step 330 coordinator 240 transfers a first available address over
`
`bus 201 to the card and, in step 340, the card stores the address in its memory (eg. 257b
`
`or 267b, Fig. 4). If instead, in step 320, a subsystem cardis not foundin thefirst slot,
`
`‘then no address is assigned. Whetheror not there is a subsystem card in the first slot, in
`
`step 350 if video system 200 has moreslots that have not been polled, then in step 360
`
`coordinator 240 polls a nextslot and returns to step 320. If instead, in step 350, no more
`
`slots remain to be polled, then all subsystem cards present have been assigned unique
`
`addresses and address assignment is complete.
`Subsystem addresses are thus assigned in a sequential mannerfor all subsystems _
`found during initialization. Contrary to conventional bus-mastering however, subsystem
`
`20
`
`addresses are not utilized throughout subsystem communication as a meansfor allocating
`
`main control bus 201. Rather, coordinator 240 utilizes subsystem addressesforalerting
`
`
`
`respective subsystems as to an assigned communication channel, thereby rapidly re-
`
`assigning bus channels.
`
`Fig. 4 is a detailed view of Fig. 2 showing components used by video system 200
`
`to coordinate and control communications. Coordinator 240 comprises ongoing
`
`communication control elements including bus master I/O controller 243a and. message
`
`length counter 243b, processing elements including processor 245a and processor-
`memory 245b, and bus allocation elements including enable I/O controller 246a and
`
`allocation queue 246b. Coordinator 240 is connected by connection 201a to main control
`
`bus 201 control lines, connection 201b to main control bus 201 address and data lines, and
`
`connection 203 to subsystem communications enable lines 203a and 203b.
`
`Video card-1 250 comprises communication elements including slave I/O controller
`
`253 and subsystem controller 255, as well as video processing elements including video
`
`processor 257a and memory 257b. Video card-1 250 is connected by connection 201c to
`
`main control bus 201 control lines, connection 201d to main control bus 201 address and
`
`
`
`data lines, and connection 203b to enable lines 203. Similarly, video card-N 260
`
`comprises communication elements including slave I/O controller 264 and subsystem
`
`controller 264, as well as video processing elements including video processor 267a and
`
`memory 267b. Video card-N is also connected by connection 201e to main control bus
`
`20
`
`201 control lines, connection 201f to main control bus 201 address and data lines, and
`connection 203c to enable lines 203.
`Coordinator 240 preferably contains no video processing components.It is
`responsible for all monitoring and control ofsubsystem communications, and is therefore
`
`the only subsystem requiring expensive bus mastering components. Conversely, video
`
`
`
`cards 250 through 260 are dedicated primarily to processing of received video data and
`
`therefore only require less expensive components.
`
`Subsystem communication is coordinated by coordinator 240 based upon user
`
`control information received over connection 103 from PC 200 (Fig. 3), system activity
`
`monitored over main control bus 201 and known system characteristics, records of which
`
`are stored in processor memory 245b. Since coordinator 240 controls all communication
`
`over main control bus 201, coordinator 240 keeps informed of each dataset andits
`
`processing from the time the data is input. Coordinator 240 also controls system 200
`
`configuration and therefore has related information available as well. Processor 245a
`
`evaluates such information to continuously determine the most appropriate
`
`communication and then dynamically initiate and control such communication. All
`
`communications are handled similarly except for a priority given to interactive user
`
`instructions,
`
`Processor 245a generates, as a result of communication-need evaluation, a time-
`
`based transfer-window (“communications channel”) designation. The designation
`
`preferably includes subsystem addresses for a subsystem that will send a dataset and for
`
`a subsystem that will receive the dataset, as well as the numberof a channel according to
`
`which data will be sent. A channel numberis a re-assignable code that coordinator 240
`
`
`
`20
`
`stores in allocation queue 246b and then, along with respective send and receive
`instructions, communicates over main control bus 201 address and data lines to the
`currently assigned subsystems. Coordinator 240 later (during an allocated transfer
`
`period) asserts a “channel on” message and a selected channel number through connection
`
`
`
`201a onto main bus 201 control lines.to instruct sets of assigned subsystems to begin or
`
`continue transferring data.
`
`Since coordinator 240 can change the control code on main control bus 201 control
`
`lines to re-allocate main control bus 201 almost instantly, the use of channel assignments
`
`provides for robust dynamic bus assignments.
`
`Coordinator 240 additionally provides subsystem enabling control for each
`
`subsystem such that channels can be re-assigned without the needto first clear a prior
`assignment. Prior to assigned subsystem communication, processor 245a, using enable
`
`I/O controller 246a to assert selected enable lines 203, preferably enables each of the
`
`assigned subsystemsto drive main control bus 201 independently.
`
`Subsystem controller 255 of video card-1, for example, is connected through
`
`connection 203b to one of enable lines 203 while video card-N is connected through
`
`connection 203c to a different one of enable lines 203. Another advantage of such dual
`
`control is that, by continuously disabling one enable line pair while enabling another, a
`
`single channel can be used to switch among multiple-subsystem pair communications.
`
`Thus a minimum numberof main control bus 201 controllines can be used to greater
`
`
`
`effect.
`
`During subsystem communication, bus master I/O controller 243a and counter
`
`243b offload lower-level monitoring and control from processor 245a to enhance system
`
`20
`
`performance. Processor 245ainitiates communication by setting counter 243b and
`sending to bus master I/O controller 243a a command code to “turn on” an included
`
`channel number. Bus master I/O controller 243a asserts main control bus 201 control
`
`connections 201a to latch the command codes on main control bus 201. Bus master I/O
`
`11
`
`
`
`controller 243a, through main control bus 201 address and data bus connections 201b,
`
`monitors bus activity and decrements counter 243b for each data word received by'a
`
`subsystem. Counter 243b, upon being decremented to zero, asserts an interrupt signal on
`
`connection 244b to processor 245a. The counter 243b starting valve thus defines, unless
`
`5
`
`superseded by processor 245, a data transfer block size limit for each communication
`
`block. While the counter-set value 243b is variable depending upon particular system
`
`performanceconstraints, a counter-set value indicating a block size of sixty four is
`
`preferably used for video system 200.
`
`
`
`
`
`Subsystem communication is otherwise conducted by the communicating
`
`subsystemsutilizing slave I/O controllers 253 and 263 according to a DMAprotocol.
`
`An enabled subsystem, having received on main control bus 201 address and data lines a
`
`control code designating it a sending subsystem on, for example, channel-1, and having
`
`received a channel-1 control code on main control bus 201 control lines, will send a next
`
`data word and then wait for an acknowledge signal. Similarly, an enabled subsystem,
`
`having received a control code on main control bus 201 address and datalines designating
`
`it as a receiving subsystem on a given channel, and having received the given channel
`
`control code on main control bus 201 control lines, will expect a data word.
`
`The specific embodiment of bus master I/O controller 243a and of slave I/O
`
`controllers 253 and 263 may be varied according to cost, response time andother criteria
`
`20
`
`Eachslave I/O controller is, however, preferably configured to receive from coordinator
`
`240 and respond appropriately to commandsincluding subsystem address designations,
`
`channel designations and the presence or absence of appropriate channel-on codes. Two
`
`main control bus 201 control lines are used for indicating one ofup to four channels, and
`
`12
`
`
`
`two more are used for command codes. In addition, slave I/O controllers 253 and 263
`
`preferably acknowledge received data words, in response to which coordinator 240 bus
`
`master I/O controller 243a decrements counter 243b.
`
`The Fig. 5 flowchart illustrates how coordinator 240 (Fig. 2) allocates main control
`
`bus 201 for subsystem communications. This illustration assumesthat no other transfers
`
`are pending and that a sender subsystem is sending a complete dataset. Since processor
`
`245a has determined that a subsystem communication (“transfer”) is required, a transfer
`
`is initiated in steps 515 through step 540, the transfer occurs in steps 545 through 560
`and post-transfer steps occur in steps 565 through 575.
`|
`
`In step 515, processor 245a polls allocation queue 246b to determine the next
`
`available communications channel number. In step 520, coordinator 240 sends the
`
`communications channel designation including the allocated channel number and
`notification that the subsystem will send data, to a first subsystem (“sender”), and then
`
`coordinator 240 enables the sender. In step 525, coordinator 240 sends the
`
`communications channel designation including the allocated channel number and
`
`notification that the second subsystem will receive data, to a second subsystem
`
`
`
`(“receiver”), and then enables the receiver. In step 530 processor 246a sets counter
`
`243b. In step 535, processor 246a sends a “channel-on” message includingthe allocated
`
`channel numberto bus master I/O controller 243a. In step 540, controller 243a latches
`the received channel-on message on main control bus 201 controllines, and in step 545
`
`20
`
`the sender and receiver begin the transfer.
`
`If bus master I/O controller 243a in step 550 detects an acknowledge,then in step
`
`555 it decrements counter 243b by one. If, in step 560, counter 243b has not been
`
`13
`
`
`
`decremented to zero, then there remains data to be transferred and the process repeats
`
`steps 550 through 560. However,if in step 560 counter 243b has been decremented to
`
`zero, then in step 565 counter 243b interrupts processor 245a. Processor 245a in step
`570 changes the control code and in step 565 disables the sender and receiver and clears
`
`the allocated request from allocation queue 246b.
`Since none ofthe conventional master-slave bus acquisition and arbitration delays
`
`are present and coordinator 240 is freed from video processing and lower-level control to
`
`continually analyze system-wide communication needs,initiation of a new transferis
`
`_
`
`robust. Therelative priority of a communication is in most cases continually known by
`
`coordinator 240 and even a new channelassignmentincurs little delay. In addition, once
`
`established, a channel can be re-activated quickly by re-enabling designated subsystems
`
`and/or issuing a channel-on messageindicating that channel.
`
`The use of robust channel assignment, channel pausing, channel switching and
`
`other capabilities of the invention also providesflexibility in typical cases of more than
`
`one concurrent request for subsystem communication. This is particularly the case where
`
`subsystem communications control is dynamically provided by a dedicated centralized
`
`
`
`ran
`
`CaraSama
`aie"a
`
`postGe4b.
`ey
`atah
`
`controller such as coordinator 240.
`
`Communicationon any assigned channelcontinues only while a corresponding
`
`channel-on codeis present onmain control bus 201 address anddata lines and while the
`
`20
`
`communicating subsystemsare enabled. Thus, an ongoing communication can be paused
`while, for example, coordinator 240 transfers configuration data to another subsystem, A
`
`pause might also be appropriate while another channelis utilized for a higherpriority
`
`transfer, a transfer upon which further tasks depend, or simply a short message that in a
`
`14
`
`
`
`conventional master-slave system might wait inordinately long. Pausing a transfer might
`
`also be appropriate where one or more communicating subsystemsfails to operate
`
`properly, so that the channel could be altered for receipt by an alternative subsystem.
`
`Controlled broadcasting is also possible by setting multiple receiving subsystemsto the
`
`same channel. Numerous other examples exist. In addition, pausing and other capabilities
`
`are provided dynamically. Thus, less than complete data sets might be utilized, among
`
`other available dynamic selection and/or manipulation. Centralization further removes
`
`
`
`
`
`complexity attributable to coordination of, for example, multiple masters.
`
`Another example of such flexibility is the use of channel switching for
`
`dynamically interleaving subsystem communications. Since switching from one
`
`communications channel to another is almost instantaneous, repeated switching will result
`
`in communication according to each channel appearing to occur almost continuously.
`
`Dynamic control by processor 245a not only provides for interleaving, but also provides
`
`for interleaving initiation and discontinuance, unequal time (“weighted”) interleaving and
`
`variably weighted interleaving either singly or in a mixed fashion. In addition to an
`
`equivalent need to move larger amounts of data among various subsystems, such
`
`capability might also be utilized for seemingly simultaneousbi-directional (“full duplex”)
`
`communication or other functionality.
`
`While the above description contains many specifics, these should not be
`construed as limitations on the scope of the invention but rather as examples ofpreferred
`
`20
`
`embodiments thereof. Many other possibilities exist within the spirit and scopeofthis
`
`invention. For example, while video system 200 is usefulfor illustrative purposes,
`
`dynamic centralized subsystem communications control accordingto the present
`
`
`
`invention is also applicable to a variety of other systems in whichefficient utilization of
`
`available communication resources is desired.
`
`A second exampleis that the invention is also applicable to systems employing
`
`topologies other than the linear bus modelillustrated, as well as systems in which
`
`multiple topologies are utilized and/or where no specific topology model predominates.
`
`Similarly, the number and types of communications connections may vary substantially
`
`from thoseofthe illustrated video system. This includes, for example, the use of multiple
`
`busses and/or sub-busses for communication as well as varied error reporting and
`
`resolution. Control according to the invention is, for example, especially well suited to
`more complex systems including any numberofsubsystems and/or communications
`
`interconnections.
`
`A third exampleis that a broad range of coordinator 240 configurations, control
`
`messaging and commandsets might be used. Processor 245a need not employ a particular
`
`decision making model andit is likely that some decision making characteristics might be
`shared with another processor, bus master I/O controller 243a or other components,
`
`particularly but not necessarily where control methods are repeated. Such functionality
`
`might be distributed and/or utilize specific processor 245a commands. Various channel.
`
`control structures other than a queue might be utilized. Discrete channel assignment
`
`means, while not preferred, might also be utilized. In addition, numerous control codes or
`
`102!
`
`
`
`20
`
`messages other than channel-on might be utilized.
`
`
`
`WHATIS CLAIMEDIS:
`
`1,
`A system for coordinating and controlling communications overa plurality of
`communication connections betweena plurality of subsystems, comprising:
`
`a communications controller for allocating available communication connections
`
`according to ongoing determinations of system communication needs; and
`
`allocation communication meansforinitiating communications among said
`
`subsystems according to said determinations.
`
`
`
`
`
`
`
`COMMUNICATION CONTROL SYSTEM
`
`ABSTRACT OF THE DISCLOSURE
`
`A communication control system provides dynamic centralized control of
`
`subsystem communications. In a preferred embodiment, a dedicated subsystem
`
`communications coordinator is coupled to a main control bus whichis utilized for
`
`subsystem communication. The coordinatoris further coupled to each subsystem for
`
`enabling subsystem communication. The coordinator preferably assigns each pending
`
`communication a time-based transfer-window channel designation which, while asserted
`
`on the control lines of the main control bus, signals corresponding enabled subsystemsto
`
`transfer data. The coordinator further preferably monitors all subsystem communications
`
`for limiting message length and for continuously determining the most effective main
`
`control busutilization according to current system-wide communications needs.
`
`
`
`18
`
`
`
`Host Computer
`
`145
`
`Monitor
`
`120
`
`130
`
`143
`
`140
`
`150
`
`Host Video
`
`Host Audio
`
`Interface (PCI)
`
`160
`
`User /O
`Controller
`
`Sys. Expansion
`
`,
`
`Fig. 1
`
`Prior A
`
`rior
`
`Art
`
`
`
`
`
`Host Computer
`
`145
`
`120
`
`130
`
`143
`
`140
`
`150
`
`Host Video
`
`Host Audio
`
`100
`
`
`
`
`
`160
`
`User I/O
`Controller
`
`Sys. Expansion
`Interface (PCI)
`
`170
`
`101
`
`
`
`ae
`
`Audio-Video
`Processing System
`
`
`200
`
`
`Video
`Main
`
`
`
`Control
`240 Enabl
`Bus
`
`
`
`nable
`Bus
`
`
`
`Lines Coordinator
`
`
`
`
`
`Video CardSe
`
`
`
`
`
`
`Video Card
`“N’
`
`Fig. 2
`
`
`
`polls first slot
`
`Card
`Present
`
`
` Coordinator
`
`
`address YES
`
`
`
`Coordinator
`assigns subsys.
`an address
`
`Subsys. stores
`
`Coordinator
`polls next slot
`
`Fig. 3
`
`
`
`
`
`Main
`
`200
`
`Video
`Bus
`
`244
`
`Slave I/O
`Controller
`
`Control
`Bus
`201a
`a Bus Master
`pe //O Control
`
`A
`108
`240
`
`
`Enable
`Lines
`
`
`|[ren
`
`tS Allocation
`
`
`203c
`
`“
`
`°
`
`260
`
`201e
`
`Pe| Seve ti
`
`Controller
`
`201f
`
`
`
`590
`
`560
`
`565
`
`570
`
`975
`
`
`
`Proc. determines
`transfer is required
`
`510
`
`
`
`Master
`
`Detects
`Ack
`
`Master decrements
`counter by 1
`
`
`
`
`Proc. checks queue
`and assigns next CH
`
`
`
`Coord. sends sender
`
`Counter
`CH assignment and
`
`
`=0
`enables sender
`
`7ce
`
`
`
`
`
`enables receiver
`
`
`
`
` Proc. sets counter
`
`
`
` Fig. 5
`
`
`Coord. sends receiver
`CH assignment and
`
`YES
`
`CounterInterrupts
`Processor
`
`Processor changes
`control code
`
`
`Processor disables
` Proc. sends "CH on"
`
`subsystems & clears
`and CH# to master
`queue entry
`
`
`Master latches CH on
`control message
`
`
`
`assigned subsystems
`begin dma
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
