Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 1 of 28 PageID# 10541
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 1 of 28 Page|D# 10541
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`EXHIBIT E
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`EXHIBIT E
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 2 of 28 PageID# 10542
`Case 3:14-CV-00757-REP-DJN Document 81ml“ lMMlflm/nflmllllllmlmfllllnmlmmnliiIIFOS42
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`U8008252675B2
`
`(12) United States Patent
`Lee et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,252,675 B2
`Aug. 28, 2012
`
`(54) METHODS OF FORMING CMOS
`lRAhblSIORS WllH HIGH LONDULIIVIIY
`GATE ELECTRODES
`
`233;??? g:
`6:492:217 Bl
`
`1333; £ng entail-
`12.5003 Baits;
`.
`(Contmued)
`
`‘
`
`(75)
`
`Inventors: Jongwon Lee. Hwaseong-si (KR): Bonn
`Yoon. Seoul (KR): Sang Yeob Han.
`Anyang-si (KR); (Thae Lyoung Kim.
`Hwaseong'Si (KR)
`
`.
`(73) Assrgnee: Samsung Electronics (70., Ltd. (KR)
`5:
`N
`S b
`d
`1
`h
`f h]
`u ject to any isc aimer. t e term 0 t
`'s
`patent is extended or adjusted under 35
`U.S.(‘. 154(b) by 0 days.
`
`(
`
`)
`
`otice:
`
`1:
`JP
`KR
`KR
`KR
`
`‘
`‘
`FOREIGN PATENT DOC UMENTS
`$882332:
`1;'%38§
`2000:351580
`125006
`|020020075732 A
`l0:2()02
`1020050073541 A
`7,2005
`1020060129959 A
`12:2006
`a
`OTHER PUBLK ATIONS
`Joseph M..
`"Chemical Mechanical Polish: The
`Steigetwald.
`Enabling Technology,” 2008 IEEE, pp. 37-40.
`
`Primart E\aminer — Femando L Toledo
`4ssistan! Etaminer 7 Valerie N Brown
`(74) Allurne} Agent or Firm 7 Myers Bigel Sibley &
`Sajovec pA
`
`ABSTR‘KIT
`(57)
`Provided is a method for manufacturing a MOS transistor.
`The method comprises providing a substrate having a first
`active region and a second active region: forming a dummy
`gate stack on the first active region and the second active
`region. the dummy gate stack comprising a gate dielectric
`layer and a dummy gate electrode: forming source/drain
`regions in the first active region and the second active region
`disposed at both sides of the dummy gate stack: forming a
`mold insulating layer on the source/drain region: removing
`the dummy gate electrode on the first active region to form a
`first trench on the mold insulating layer; forming a first metal
`pattern to form a second trench at a lower portion of the first
`trench. zuld removing the dummy gate electrode on the second
`active region to from a third trench on the mold insulating
`layer; and fonning a second metal layer in the second trench
`and the third trench to form a first gate electrode on the first
`active region and a second gate electrode on the second active
`region.
`
`15 Claims, 19 Drawing Sheets
`
`(21) Appl.No.: 12/942,763
`
`(22)
`
`Filed:
`
`Nov. 9. 2010
`
`(65)
`
`(30)
`
`Prior Publication Data
`
`Jun. 9. 2011
`US 2011/0136313 A1
`Foreign Application Priority Data
`
`Dec. 8~ 2009
`
`(KR)
`
`10-2009'0121108
`
`(51)
`
`Int. 0-
`(2006-01)
`H0114 21/336
`(2006-01)
`H0114 21/44
`(2006-01)
`H01L 21/83
`(2006-01)
`H01L 21/4763
`(52) US. Cl.
`........ 438/592: 438/299: 438/637: 438/926:
`438/ 183: 257/E2l .177: 257/E2 l .62 l: 257/E2l.626:
`257/E2 1 -64
`(58) Field of Classification Search ................... 438/296
`See application file for complete search history.
`
`(56)
`
`References Cited
`US. PATENT DOCUMENTS
`0130123 A
`6.]66.4l7 A
`
`1032000 Liangetal.
`l2.‘2000 Baietal.
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 3 of 28 PageID# 10543
`Case 3:14-cv-OO757-REP-DJN Document 81-5 Filed 04/10/15 Page 3 of 28 Page|D# 10543
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`US 8,252,675 B2
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`US. PATENT DOCUMENTS
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 4 of 28 PageID# 10544
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 4 of 28 Page|D# 10544
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`US. Patent
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`Aug. 28, 2012
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`Sheet 1 of 19
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`US 8,252,675 B2
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 5 of 28 PageID# 10545
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`U.S. Patent
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`Aug. 28, 2012
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`Sheet 2 of 19
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`US 8,252,675 B2
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 6 of 28 PageID# 10546
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`US. Patent
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 7 of 28 PageID# 10547
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 8 of 28 PageID# 10548
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 8 of 28 Page|D# 10548
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`US. Patent
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 9 of 28 PageID# 10549
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 9 of 28 Page|D# 10549
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 10 of 28 PageID# 10550
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 10 of 28 Page|D# 10550
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`US. Patent
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 11 of 28 PageID# 10551
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 11 of 28 Page|D# 10551
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`US. Patent
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 12 of 28 PageID# 10552
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`US. Patent
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`Aug. 28, 2012
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 13 of 28 PageID# 10553
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 13 of 28 Page|D# 10553
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`US. Patent
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 14 of 28 PageID# 10554
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`US. Patent
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 15 of 28 PageID# 10555
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 16 of 28 PageID# 10556
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 17 of 28 PageID# 10557
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`US. Patent
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 18 of 28 PageID# 10558
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 18 of 28 Page|D# 10558
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 19 of 28 PageID# 10559
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 19 of 28 Page|D# 10559
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`US. Patent
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 20 of 28 PageID# 10560
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 20 of 28 Page|D# 10560
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`US. Patent
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`Aug. 28, 2012
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`Sheet 17 of 19
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`US 8,252,675 B2
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 21 of 28 PageID# 10561
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 21 of 28 Page|D# 10561
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`U.S. Patent
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`Aug. 28, 2012
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`Sheet 18 of 19
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`US 8,252,675 B2
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 22 of 28 PageID# 10562
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 22 of 28 Page|D# 10562
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`US. Patent
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`Aug. 28, 2012
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`Sheet 19 of 19
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`US 8,252,675 B2
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`

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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 23 of 28 PageID# 10563
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 23 of 28 Page|D# 10563
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`US 8,252,675 B2
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`1
`METHODS OF FORMING CMOS
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`TRANSISTORS WITH HIGH CONDUCTIVITY
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`GATE ELECTRODES
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`REFERENCE TO PRIORITY APPLICATION
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`This application claims priority to Korean Patent Applica-
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`tion No. 10-2009-0121108, filed Dec. 8, 2009, the contents of
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`which are hereby incorporated herein by reference.
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`FIELD OF THE INVENTION
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`This invention relates to methods for manufacturing MOS
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`transistors and, more particularly, to methods for manufac-
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`turing MOS transistors having gate electrodes formed of dif-
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`ferent metals.
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`BACKGROUND OF THE INVENTION
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`A MOS transistor is widely used as switching devices. In
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`contrast to conventional MOS transistors containing a gate
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`electrode which is formed of poly silicon, a metal material
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`with superior electric conductivity better than the poly silicon
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`have beenused as the gate electrode of MOS transistors. MOS
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`transistors are classified as n-MOS transistors orp-MOS tran-
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`sistors in accordance with the channel type which is induced
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`beneath the gate electrode. The gate electrodes of the n-MOS
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`transistor and the p-MOS transistor may be formed of differ-
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`ent metals so that the n-MOS transistor and the p-MOS tran-
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`sistor have different threshold voltages.
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`SUMMARY
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`Methods of forming insulated-gate field effect transistors
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`according to embodiments of the invention includes forming
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`a gate insulating layer on a substrate and forming a dummy
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`gate electrode on the gate insulating layer. Electrically insu-
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`lating spacers are formed on sidewalls of the dummy gate
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`electrode. These spacers and the dummy gate electrode are
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`covered with an electrically insulating mold layer. An upper
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`portion of the mold layer is then removed to expose an upper
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`surface of the dummy gate electrode. The dummy gate elec-
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`trode is then removed from between the spacers by selectively
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`etching back the dummy gate electrode using the mold layer
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`and the spacers as an etching mask. A first metal layer is
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`deposited onto an upper surface of the mold layer and onto
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`inner sidewalls of the spacers. A space between the inner
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`sidewalls of the spacers is filled with a dummy filler layer
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`(e. g., polysilicon) that contacts the first metal layer. An upper
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`portion of the first metal layer is removed from between the
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`inner sidewalls of the spacers and the dummy filler layer. The
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`dummy filler layer is then removed from between the inner
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`sidewalls of the spacers to expose the first metal layer. A
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`second metal layer is then deposited onto a portion ofthe first
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`metal layer extending between the inner sidewalls of the
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`spacers, to thereby define a metal gate electrode containing a
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`composite of the first and second metal layers.
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`According to some ofthese embodiments ofthe invention,
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`the step of filling a space between the inner sidewalls of the
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`spacers is followed by a step of planarizing the dummy filler
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`layer to expose a portion of the first metal layer on the upper
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`surface of the mold layer. In addition, the step of forming a
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`dummy gate electrode on the gate insulating layer may be
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`preceded by forming a buffer gate electrode containing tita-
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`nium nitride or tantalum nitride on the gate insulating layer. In
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`addition, the step of removing an upper portion of the first
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`metal layer may include selectively etching the first metal
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`5
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`10
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`2
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`layer using the dummy filler layer and the mold layer as an
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`etching mask. This first metal layer may include titanium
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`nitride.
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`Still further embodiments ofthe invention include methods
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`of forming CMOS transistors by forming first and second
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`gate insulating layers on a substrate and forming first and
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`second dummy gate electrodes on the first and second gate
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`insulating layers, respectively. First and second electrically
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`insulating spacers are formed on sidewalls of the first and
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`second dummy gate electrodes, respectively. These first and
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`second spacers and the first and second dummy gate elec-
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`trodes are covered with an electrically insulating mold layer.
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`An upper portion of the mold layer is removed to expose an
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`upper surface of the first dummy gate electrode and an upper
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`surface ofthe second dummy gate electrode. The first dummy
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`gate electrode is selectively removed from between the first
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`spacers using a mask to prevent removal of the second
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`dummy gate electrode. A first metal layer is deposited onto an
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`upper surface ofthe mold layer and onto inner sidewalls ofthe
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`first spacers. A space between the inner sidewalls of the first
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`spacers is filled with a dummy filler layer that contacts the
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`first metal layer. An upper portion of the first metal layer is
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`removed from between the inner sidewalls of the first spacers
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`and the dummy filler layer. The dummy filler layer is removed
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`from between the inner sidewalls ofthe first spacers to expose
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`the first metal layer. This step is performed concurrently with
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`removing the second dummy gate electrode from between
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`inner sidewalls ofthe second spacers. A second metal layer is
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`then deposited onto a portion ofthe first metal layer extending
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`between the inner sidewalls of the first spacers to thereby
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`define a first metal gate electrode including a composite ofthe
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`first and second metal layers. This step is performed concur-
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`rently with depositing the second metal layer into a space
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`between the inner sidewalls of the second spacers to thereby
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`define a second metal gate electrode.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The accompanying drawings are included to provide a
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`further understanding of the inventive concept, and are incor-
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`porated in and constitute a part of this specification. The
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`drawings illustrate exemplary embodiments of the inventive
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`concept and, together with the description, serve to explain
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`principles of the inventive concept. In the figures:
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`FIGS. 1 through 17 are cross-sectional views illustrating a
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`method for manufacturing a MOS transistor according to a
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`first embodiment of the inventive concept; and
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`FIGS. 18 through 37 are cross-sectional views illustrating
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`a method for manufacturing a MOS transistor according to a
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`second embodiment of the inventive concept.
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`DETAILED DESCRIPTION OF THE
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`EMBODIMENTS
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`Exemplary embodiments of the inventive concept will be
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`described below in more detail with reference to the accom-
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`panying drawings. The embodiments ofthe inventive concept
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`may, however, be embodied in different forms and should not
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`be construed as limited to the embodiments set forth herein.
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`Rather, these embodiments are provided so that this disclo-
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`sure will be thorough and complete, and will fully convey the
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`scope of the inventive concept to those skilled in the art.
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`Hereinafter, exemplary embodiments of the inventive con-
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`cept will be described in detail with reference to the accom-
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`panying drawings.
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`

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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 24 of 28 PageID# 10564
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 24 of 28 Page|D# 10564
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`US 8,252,675 B2
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`4
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`3
`FIGS. 1 through 17 are cross-sectional views illustrating a
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`method for manufacturing a MOS transistor according to a
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`first embodiment of the inventive concept.
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`Referring to FIG. 1, a first well and a second well may be
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`respectively formed in a first active region 14 and a second
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`active region 16 which are defined by a device isolation layer
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`12 on a substrate 10. The first well may be formed in an ion
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`implantation process in which impurities of a first conductiv-
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`ity type are injected in the substrate 10. The impurity of the
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`first conductivity type may comprise a donor ion such as
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`phosphorus or arsenic. For example, the impurities ofthe first
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`conductivity type may be injected at an energy of about 100
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`KeV~300 KeV and a concentration of about
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`ea/cm3~l><1016 ea/cm3. The second well may be formed by
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`an ion implantation process in which impurities of a second
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`conductivity type opposite to the first conductivity type are
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`injected in the substrate 10. The impurity of the second con-
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`ductivity type may comprise an acceptor ion such as boron.
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`For example, the impurities of the second conductivity type
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`may be injected at an energy of about 70 KeV~200 KeV and
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`a concentration of about l><10l3 ea/cm3~l ><1016 ea/cm3. The
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`device isolation layer 12 may be formed after forming the first
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`well and the second well. The device isolation layer 12 may
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`comprise silicon oxide that is formed by a plasma enhanced
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`chemical vapor deposition (PECVD). The silicon oxide is
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`formed in a trench where a predetermined depth of the sub-
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`strate 10 is removed.
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`Referring to FIG. 2, a gate insulating layer 18, a buffer gate
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`electrode 20 and a dummy gate electrode 22 may be stacked
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`on the substrate 10. The gate insulating layer 18 may be
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`formed of a high-k dielectric layer such as a hafnium oxide
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`layer, a tantalum oxide layer and a silicon oxide layer. The
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`gate insulating layer 18 may be formed to have thickness of
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`about 30 A~200 A by a method such as chemical vapor
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`deposition (CVD), atomic layer deposition (ALD) or rapid
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`thermal process (RTP). The buffer gate electrode 20 may
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`comprise a titanium nitride layer or a tantalum nitride layer.
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`The buffer gate electrode 20 may be formed to have thickness
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`of about 20 A~50 A by a method such as CVD or ALD. The
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`dummy gate electrode 22 may comprise poly silicon that is
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`formed by a chemical vapor deposition.
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`Referring to FIG. 3, a dummy gate stack 24 comprising the
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`gate insulating layer 18, the buffer gate electrode 20 and the
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`dummy gate electrode 22 may be formed on the first active
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`region 14 and the second active region 16. The dummy gate
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`stack 24 may be patterned using a photo lithography process
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`and an etching process. The photo lithography and the etching
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`process may be performed as follows. Initially, a first photo
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`resist pattern (not shown) may be formed on the dummy gate
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`electrode 22. The dummy gate electrode 22, the buffer gate
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`electrode 20 and the gate insulating layer 18 may be succes-
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`sively etched using the first photo resist pattern as an etch
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`mask.
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`Referring to FIG. 4, a second photo resist pattern 25 may be
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`formed to cover the second active region 16. A lightly doped
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`drain (LDD) 26 is formed using the second photo resist pat-
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`tern 25 and the dummy gate electrode 22 as an ion implanta-
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`tion mask. The impurities of the second conductivity type
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`may be injected into the first active region 14. The impurities
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`of the second conductivity type may be injected at an energy
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`of about 1 KeV ~20 KeV and a concentration of about 1 ><1013
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`ea/cm3~l><10l 6 ea/cm3 . The second photo resist pattern 25 is
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`removed.
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`Referring to FIG. 5, a third photo resist pattern 27 may be
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`formed to cover the first active region 14. A LDD 26 may be
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`formed in the second active region using the third photo resist
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`pattern 27 and the dummy gate electrode 22 as an ion implan-
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`5
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`15
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`20
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`25
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`30
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`tation mask. Impurities of the first conductivity type may be
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`injected into the second active region 1 6. The impurities ofthe
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`first conductivity type may be injected at an energy of about
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`5 KeV~30 KeV and a concentration of about
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`ea/cm3~l><1016 ea/cm3. The LDDs 26 may be formed ofthe
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`same depth in the first active region 14 and the second active
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`region 16, and diffused to the same distant below the dummy
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`gate stack 24. The photo resist pattern 27 is removed.
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`Referring to FIG. 6, a spacer 28 may be formed on a
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`sidewall of the dummy gate stack 24. The spacer 28 may
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`comprise a silicon nitride layer which is formed by a chemical
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`vapor deposition process. The spacer 28 may be formed by a
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`self alignment method. For example, a silicon nitride layer is
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`formed to cover the dummy gate stack 24, and the silicon
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`nitride layer is then anisotropically etched to remain on the
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`sidewall of the dummy gate stack 24.
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`Referring to FIG. 7, a fourth photo resist pattern 29 may be
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`formed to cover the second active region 16. A source/drain
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`region 30 may be formed in the first active region using the
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`fourth photo resist pattern 29, the dummy gate electrode 22
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`and the spacer 28 as an ion implantation mask. The source/
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`drain region 30 may comprise impurities of the second con-
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`ductivity type. The impurities ofthe second conductivity type
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`may be injected at an energy of about 10 KeV~40 KeV and a
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`concentration of about l><10l6 ea/cm3~l ><10l7 ea/cm3. The
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`fourth photo resist pattern 29 on the second active region 16 is
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`removed.
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`Referring to FIG. 8, a fifth photo resist pattern 31 is formed
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`to cover the first active region 14. A source/drain region 30
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`may be formed in the second active region 16 using the fifth
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`photo resist pattern 31, the dummy gate electrode 22 and the
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`spacer 28 as an ion implantation mask. The source/drain
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`region 30 in the second active region 16 may comprise impu-
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`rities ofthe first conductive type. For example, The impurities
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`of the first conductivity type may be injected in the second
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`active region 16 at an energy of about 10 KeV~50 KeV and a
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`concentration of about l><10l6 ea/cm3~l ><10l7 ea/cm3. The
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`source/drain regions 30 in the first active region 14 and the
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`second active region may be the same depth. The photo resist
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`pattern 31 may be then removed.
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`Although not shown in drawings, the source/drain region
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`30 may be formed by removing portions of the first active
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`region 14 and the second active region 16 and filling an
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`epitaxial silicon germanium with impurities of respective
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`conductivity type in the removed portions of the first active
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`region 14 and the second active region 16.
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`Referring to FIG. 9, a mold insulating layer 32 is formed to
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`cover the source/drain region 30 and the dummy gate stack
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`24. The mold insulating layer 32 may comprise a silicon
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`oxide layer. The mold insulating layer 32 may be formed in a
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`low pressure chemical vapor deposition (LPCVD) process or
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`plasma enhanced chemical vapor deposition (PECVD) pro-
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`cess. The mold insulating layer 32 may be planarized such
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`that the dummy gate electrode 22 may be formed. The pla-
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`narization of the mold insulating layer 32 may be performed
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`by a method such as chemical mechanical polishing (CMP) or
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`etch-back.
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`Referring to FIG. 10, the dummy gate electrode 22 on the
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`first active region 14 may be selectively removed to form a
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`first trench 35. The removing of the dummy gate electrode 22
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`may comprise forming a sixth photo resist pattern 34 to cover
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`the second active region 16 while exposing the dummy gate
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`electrode 22 on the first active region 14, and etching the
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`dummy gate electrode 22 in a dry or wet etching process. The
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`sixth photo resist pattern 34, the mold insulating layer 32 and
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`the spacer 28 on the substrate 10 may be used as an etch mask
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`while the dummy gate electrode 22 is removed. The buffer
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`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 25 of 28 PageID# 10565
`Case 3:14-cv-00757-REP-DJN Document 81-5 Filed 04/10/15 Page 25 of 28 Page|D# 10565
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`US 8,252,675 B2
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`5
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`gate electrode 20 may be used as an etc