Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 1 of 24 PageID# 10517
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 1 of 24 Page|D# 10517
`
`
`
`
`EXHIBIT D
`
`EXHIBIT D
`
`
`
`
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 2 of 24 PageID# 10518
`Case 3: l4-CV-00757-REP-DJ N DOCUment 81'1““ "mm" Mill/m llllnflflmmmflllllIMImMmIIIZLOSl8
`
`U3006819602B2
`
`(12)
`
`United States Patent
`Seo et al.
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 6,819,602 B2
`Nov. 16, 2004
`
`(54)
`
`(75)
`
`(73)
`
`MULTIMODE DATA BUFFER AND METHOD
`FOR CONTROLLING PROPAGATION
`DELAY TIME
`
`Inventors: Seong-young Seo, Suwon (KR);
`Jung-bae Lee, Yongin (KR); Byong-mo
`Moon, Seoul (KR)
`
`Assignee: Samsung Electronics Co, Ltd.,
`Kyungki-Do (KR)
`
`6396.768 B2 *
`6,414,517 Bl
`*
`6.424.590 Bl
`6,452.849 Bl *
`6,512,704 Bl “
`2003/0000204 A1 *
`
`365,233
`
`5.12002 Ooishi
`7.12002 Kim et al.
`3651123008
`7,;‘2002 Taruishi ct al.
`365/201
`9,-‘201'12
`lwamoto
`365,-"189.07
`1,2003 Wu et al.
`5.12003 Chang ......................... 326.193
`
`FOREIGN PATENT DOCUMENTS
`
`PP
`KR
`
`0322915 A3
`2002046826
`
`7,-'l 989
`62002
`
`(‘)
`
`Notice:
`
`Subject to any disclaimer. the term of this
`patent is extended or adjusted under 35
`U.S.C‘. 154(b) by 77 days.
`
`* cited by examiner
`
`Appl. No.: 10/278,071
`
`Filed:
`
`Oct. 23, 2002
`Prior Publication Data
`
`US 200350210575 A1 Nov. 13. 2003
`
`(60)
`
`(51)
`(52)
`
`(58)
`
`(56)
`
`Related U.S. Application Data
`Provisional application No. 60/379,665, filed on May 10,
`2002.
`
`Int. Cl.7 .................................................. GllC 7/00
`U.S. Cl.
`.................. 365/193; 365/18905; 365/191;
`365/194
`
`Field of Search
`
`365118905, 191,
`365/193, 104
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`Primary Examiner—Van Thu Nguyen
`(74) Attorney, Agent, or Firm—Hamess, Dickey & Pierce,
`P.L,C.
`
`(57)
`
`ABSTRACT
`
`A data bulfer, such as a data strobe input buffer or a data
`input butfer, which may operate in multiple modes, such as
`a single mode (SM) and a dual mode (DM) and where the
`mode is selected by providing a signal, such as an external
`signal such as an address signal or an external command
`signal. A data hufi'er which can he used for a SM,='|)M
`dual-use and can improve a data setupthold margin. A
`semiconductor memory device including one or more of the
`data buffers described above. A method for controlling
`propagation delay times which can improve a data setup/
`hold margin in a SM,«’DM dual-use data bufi‘er.
`
`6.279.073 Bl
`
`*
`
`8/2001 McCraeken et al.
`
`711/105
`
`29 Claims, 13 Drawing Sheets
`
`DIFFERENTIAL
`AMPLIFIER
`
`
`
`
`0088 D
`
`VREF.
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 3 of 24 PageID# 10519
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 3 of 24 Page|D# 10519
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 1 0f 13
`
`US 6,819,602 B2
`
`FIG.
`
`1
`
`Prior Art
`
`005
`
`DO
`
`DIN
`
`DOS D
`
`0080 -
`
`VREF D r---------00---“..-‘u-
`
`
`
`
`
`00
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 4 of 24 PageID# 10520
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 4 of 24 Page|D# 10520
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 2 of 13
`
`US 6,819,602 B2
`
`FIG. 3A
`
`0088
`
`CNTB '
`
`VREF
`
`
`
`—"
`
`211
`
`~— CNT
`
`FIG. BB
`
`CNT ~———{>o———— CNTB
`
`FIG. 4
`
`CNT/CNTB
`
`
`
`MODE
`REGISTER SET
`
`COMMAND
`
`ADD
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 5 of 24 PageID# 10521
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 5 of 24 Page|D# 10521
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 3 of 13
`
`US 6,819,602 B2
`
`FW(}.
`
`5A»
`
`25i
`
`712
`
`714
`
`>
`
`CNT
`
`VCCH
`
`710
`
`N6
`
`FIGu EH3
`
`VOLTAGE LEVEL
`
`POWER
`
`e—VCCH
`
`T1
`
`T2
`
`——-—nME
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 6 of 24 PageID# 10522
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 6 of 24 Page|D# 10522
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 4 0f 13
`
`US 6,819,602 B2
`
`FIG. 6
`
`vDD
`
`14100l14200 14400
`l;1><3—'- CNT
`
`14300
`
`FIG.
`
`'7
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 7 of 24 PageID# 10523
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 7 of 24 Page|D# 10523
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 5 0f 13
`
`US 6,819,602 B2
`
`FIG. 8
`
`DS 'CNTB
`
`FIG. 9
`
`DO
`
`DOS
`
`-—~os
`
`DIN
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 8 of 24 PageID# 10524
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 8 of 24 Page|D# 10524
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 6 of 13
`
`US 6,819,602 B2
`
`FIG. 10
`
`
` " DIFFERENTIAL
`
`AMPLIFIER
`
`
`00
`
`FIG. 11
`
`31
`
`CNT/CNTB
`
`DOS I»
`
`1st
`
`AMPLIFIER
`
`
`- DIFFERENTIAL
`
`
`
`
`:52
`
`ems/cm
`
`
`2nd
`
`DIFFERENTIAL
`AMPLIFIER
`
`(
`
`0088 II
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 9 of 24 PageID# 10525
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 9 of 24 Page|D# 10525
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 7 of 13
`
`US 6,819,602 B2
`
`FIG. 12
`
`.130
`
`}
`
`DS
`
`DELAY
`
`251
`
`} 130
`
`DS
`
`Ist
`
`DOS D
`
`VREF o
`
`CNT/CNTB
`31
`
`- DIFFERENTIAL
`
`AMPLIFIER
`
`
`32
`cma/c \IT
`
`
`34
`2nd
`DIFFERENTIAL
`
`DQSB D
`AMPLIFIER
`
`
`FIG. 13
`
`31
`
`CNT/CNTB
`
`33
`
`CNTB/CNT
`
`
`DOS .
`-
`Ist
`DIFFERENTIAL
`
`AMPLIFIER
`
`
`32
`34 2nd
`
`DIFFERENTIAL
`
`AMPLIFIER
`
`I Cdummy
`
`VREF .
`
`0058 D
`
`VSS
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 10 of 24 PageID# 10526
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 10 of 24 Page|D# 10526
`
`US. Patent
`
`Nov. 16,2004
`
`Sheet 8 0f 13
`
`US 6,819,602 B2
`
`FIG. 14
`
`CNTB/CNT
`
`DIFFERENTIAL
`AMPLIFIER
`
`DO
`
`D0
`
`
`
`
`DQB
`
`VREF
`
`CNT/CNTB
`
`
`
`DIFFERENTIAL
`AMPLIFIER
`
`DOB
`
`VREF
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 11 of 24 PageID# 10527
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 11 of 24 Page|D# 10527
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 9 of 13
`
`US 6,819,602 B2
`
`FIG. 16
`
`DO
`
`'I In
`
`I
`I
`l
`I
`
`II
`
`DO
`
`l'
`'
`I
`I
`
`I
`:
`:
`.
`I
`
`I
`
`DIFFERENTIAL
`AMPLIFIER
`
`Cdummy
`
`E VREF
`vss
`
`:
`:
`;
`.
`I
`21 I
`|
`'L ____________________________ j
`
`FIG. 17
`
`CNT/CNTB
`31
`
`
`
`Ist
`00 D
`- DIFFERENTIAL
`
`AMPLIFIER
`
`
`
`2nd
`DIFFERENTIAL
`
`AMPLIFIER
`
`VREF D
`
`008 D
`
`32
`
`CNTB/CNT
`
`
`
`
`'I
`I
`I
`I
`
`I
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 12 of 24 PageID# 10528
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 12 of 24 Page|D# 10528
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 10 0f 13
`
`US 6,819,602 B2
`
`FIG. 18
`
`31
`
`CNT/CNTB
`
`DO -
`
`VREI: .
`
`Ist
`
`- DIFFERENTIAL
`AMPLIFIER
`
`
`
`
`I I0
`
`f
`
`DIN
`
`34
`
`DELAY
`
`231
`
`
`
`
`DQB D—~*
`
`
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`FIG. 19
`
`31
`
`CNT/CNTB
`
`DO I.
`
`VREF I-
`
`Ist
`
`- DIFFERENTIAL
`AMPLIFIER
`
`
`
`
`
`2nd
`DIFFERENTIAL
`
`DOB D
`AMPLIFIER
`
`
`
`110
`
`DIN
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 13 of 24 PageID# 10529
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 13 of 24 Page|D# 10529
`
`US. Patent
`
`Nov. 16,2004
`
`Sheet 11 0f 13
`
`US 6,819,602 B2
`
`FIG. 20
`
`------ 4------
`11
`
` DQ
`DATA
`1NPUT BUFFER
`
`
`
`DINE
`
`
`
`
`DOS D -
`DATA
`
`
`DOSE D
`STROBE SIGNAL
`
`VREF . I INPUT BUFFER
`
`
`
`DI NO
`
`COMMAND
`
`ADD
`
`FIG. 21
`
`COMMAND (E)
`
`®
`
`0°
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 14 of 24 PageID# 10530
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 14 of 24 Page|D# 10530
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 12 0f 13
`
`US 6,819,602 B2
`
`FIG. 22
`
` DS. I ’-
`
`’.
`
`°
`
`DINO
`
`.
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 15 of 24 PageID# 10531
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 15 of 24 Page|D# 10531
`
`US. Patent
`
`Nov. 16, 2004
`
`Sheet 13 0f 13
`
`US 6,819,602 32
`
`f]
`
`’
`
`~DINE
`
`.
`
`DINO
`
`FIG. 23
`
`11
`
`17
`r ------ 1------ 1
`
`'
`
`.
`
`.
`i
`.
`I
`l
`l
`
`I
`.
`.
`
`a
`
`:
`.
`l
`l
`l
`|
`
`i
`.
`
`17b E
`
`
`g
`. -I.
`
`INPUT BUFFER l
`
`
`
`008 n
`
`008 .
`
`VREF D
`
`DATA
`STROBE SIGNAL
`
`COMMAND
`
`ADD
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 16 of 24 PageID# 10532
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 16 of 24 Page|D# 10532
`
`
`
`US 6,819,602 B2
`
`
`
`
`1
`MULTIMODE DATA BUFFER AND METHOD
`
`
`
`
`FOR CONTROLLING PROPAGATION
`
`
`DELAY TIME
`
`
`CROSS REFERENCE TO RELATED
`
`
`
`APPLICATIONS
`
`
`
`
`
`
`
`
`
`
`This US. nonprovisional application claims priority
`
`
`
`
`
`under 35 U.S.C. § 119 to US. Provisional Patent Applica-
`
`
`
`
`
`
`
`
`
`tion No. 60/379,665 filed May 10, 2002, the entire contents
`
`
`
`
`
`
`
`
`
`of which are incorporated by reference.
`
`
`
`
`
`
`BACKGROUND OF THE INVENTION
`
`
`
`1. Field of the Invention
`
`
`
`
`
`The present invention relates to a semiconductor memory
`
`
`
`
`
`
`
`device, and more particularly, to a multimode data buffer and
`
`
`
`
`
`
`
`
`
`a method for controlling propagation time delay.
`
`
`
`
`
`
`
`2. Description of the Related Art
`
`
`
`
`
`
`innovations in the
`To improve system performances,
`
`
`
`
`
`
`
`design of semiconductor memory devices in general, and the
`
`
`
`
`
`
`
`
`
`design of dynamic random access memories (DRAMs) in
`
`
`
`
`
`
`
`
`particular, continue to focus on higher integration and higher
`
`
`
`
`
`
`
`
`
`speed operation. That is, DRAMs capable of processing
`
`
`
`
`
`
`
`
`more data at higher speed are desired. For higher speed
`
`
`
`
`
`
`
`
`
`
`operations, DRAMs synchronized with a system clock have
`
`
`
`
`
`
`
`been developed. This synchronous feature of DRAMs has
`
`
`
`
`
`
`
`
`increased data transmission speeds.
`
`
`
`
`However, since a data input/output operation in a syn-
`
`
`
`
`
`
`
`
`chronous DRAM should be performed in a cycle of a system
`
`
`
`
`
`
`
`
`
`clock, there is a limit to increasing the bandwidth between
`
`
`
`
`
`
`
`
`
`
`the synchronous DRAM and a DRAM controller, that is, the
`
`
`
`
`
`
`
`
`
`amount of data which is input/output from a memory device
`
`
`
`
`
`
`
`
`
`
`in a unit time is limited. In order to increase data transmis-
`
`
`
`
`
`
`
`
`
`
`
`sion speed, dual data rate (DDR) synchronous DRAMs in
`
`
`
`
`
`
`
`
`which data is input/output synchronized both with the rising
`
`
`
`
`
`
`
`
`edge and falling edge of a clock have been developed.
`
`
`
`
`
`
`
`
`
`In general, a DDR synchronous DRAM uses a data strobe
`
`
`
`
`
`
`
`
`signal when the DRAM receives data from a memory
`
`
`
`
`
`
`
`
`controller or sends data to the memory controller. For
`
`
`
`
`
`
`
`
`example, in a data receiving operation, the DDR synchro-
`
`
`
`
`
`
`
`
`nous DRAM receives data with a data strobe signal from the
`
`
`
`
`
`
`
`
`
`memory controller. Also, in a data outputting operation, the
`
`
`
`
`
`
`
`
`DDR synchronous DRAM outputs data with a data strobe
`
`
`
`
`
`
`
`
`signal to the memory controller.
`
`
`
`
`
`In high speed semiconductor memory devices such as
`
`
`
`
`
`
`
`DDR synchronous DRAMs, a single mode (SM)-type input
`
`
`
`
`
`
`
`buffer, which compares a data strobe signal with a reference
`
`
`
`
`
`
`
`voltage, is used as a data strobe input buffer. However, in a
`
`
`
`
`
`
`
`
`
`
`
`DDR synchronous DRAM having an SM-type data strobe
`
`
`
`
`
`
`
`signal input buffer, a data setup/hold time margin may be
`
`
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`
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`
`
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`degraded if noise is included in a data strobe signal or
`
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`
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`reference voltage.
`
`
`In order to compensate for this problem, a dual mode
`
`
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`
`
`
`
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`(DM)-type data strobe signal input buffer which compares a
`
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`
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`data strobe signal with the inverse signal of the data strobe
`
`
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`
`
`
`
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`
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`signal instead of reference voltage has been introduced.
`
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`
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`Since an output signal is determined at the cross point of
`
`
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`the two signals, that is, the data strobe signal and an inverse
`
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`
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`of the data strobe signal, in the DM-type data strobe signal
`
`
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`
`
`
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`
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`input buffer, noise immunity improves.
`
`
`
`
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`Also, more recently, in order to satisfy demands of a
`
`
`
`
`
`
`
`
`
`variety of users, an SM/DM dual-use data strobe signal input
`
`
`
`
`
`
`
`
`
`buffer has been developed. In an SM/DM dual-use data
`
`
`
`
`
`
`
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`strobe signal input buffer, propagation delay time from an
`
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`
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`
`
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`input terminal to an output terminal should be substantially
`
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`
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`
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`the same both in the single mode (SM) and in the dual mode
`
`
`
`
`
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`
`
`
`
`2
`
`
`(DM). However, since the gain of a differential amplifier in
`
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`
`
`
`the single mode is different from the gain in the dual mode,
`
`
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`
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`the propagation delay time in the single mode is different
`
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`
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`
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`from the propagation delay time in the dual mode.
`
`
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`
`
`
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`
`
`FIG. 1 illustrates waveforms produced in accordance with
`
`
`
`
`
`
`
`
`the prior art. As shown in FIG. 1, propagation delay time of
`
`
`
`
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`
`
`
`
`
`the differential output signal (DS) in the SM mode is much
`
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`
`
`
`
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`greater than in the DM mode. Outputting the differential
`
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`
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`output signal (DS) at a different time in the SM mode and the
`
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`DM mode degrades the uniformity of both the data setup
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`time (tDS) and the data hold time (tDH) as illustrated in FIG.
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`SUMMARY OF THE INVENTION
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`invention are
`Exemplary embodiments of the present
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`Exemplary embodiments of the present invention are also
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`dual-use and can improve a data setup/hold margin.
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`Exemplary embodiments of the present invention are also
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`SM/DM dual-use data buffer.
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`Exemplary embodiments of the present invention are also
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`directed to a data buffer including a differential amplifier
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`circuit including at least two switches for passing an inverse
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`data signal or a reference voltage, respectively, depending
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`on a level of a control signal, and a differential amplifier for
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`receiving a data signal, and either the inverse data signal or
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`the reference voltage and outputting at least two different
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`differentially amplified signals.
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`In exemplary embodiments of the present invention, the
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`data buffer is a data strobe input buffer, the inverse data
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`signal is an inverse data strobe signal, and the data signal is
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`a data strobe signal.
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`In exemplary embodiments of the present invention, the
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`data strobe input buffer is operable in both a single mode and
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`a dual mode, wherein in said single mode, the reference
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`voltage is applied to a first of the at least two switches and
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`the level of the control signal is a first logic state and in said
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`dual mode, the inverse data strobe signal is provided to a
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`second of the at least two switches 212 and the level of the
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`control signal is a second logic state.
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`In exemplary embodiments of the present invention, the
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`data strobe input buffer is part of a semiconductor memory
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`device. In exemplary embodiments of the present invention,
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`the semiconductor memory device also includes a control
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`circuit for outputting the control signal to the data strobe
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`input buffer.
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`In exemplary embodiments of the present invention, the
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`control circuit includes a mode register set for receiving an
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`external command and an address and generating the control
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`signal, wherein a level of the control signal determines a
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`mode of the semiconductor memory device.
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`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 17 of 24 PageID# 10533
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 17 of 24 Page|D# 10533
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`US 6,819,602 B2
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`3
`the
`In exemplary embodiments of the present invention,
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`control circuit
`includes a fuse circuit
`including a fuse,
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`wherein a state of the fuse determines a level of the control
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`4
`outputting a data input signal, a control circuit for outputting
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`the control signal to the data strobe input buffer, and a data
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`write circuit for receiving the data input signal from said
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`data input buffer and the writing even number data of the
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`data input signal into a first latch in response to a rising edge
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`of the output data signal and writing odd number data of the
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`data input signal into a second latch in response to a falling
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`edge of the output data strobe signal.
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`In exemplary embodiments of the present invention, the
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`first latch includes a plurality of latches and a plurality of
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`switches, arranged alternatively. In exemplary embodiments
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`of the present
`invention,
`the plurality of switches are
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`arranged to be triggered on the leading and falling edge of
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`an inverse of the differential output signal.
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`In exemplary embodiments of the present invention, a
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`first switch receives the even number data of the output
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`signal of the data input buffer and passes the even number
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`data of the output signal to a first of the plurality of latches.
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`In exemplary embodiments of the present invention, the
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`second latch including a plurality of latches and a plurality
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`of switches, arranged alternatively.
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`In exemplary embodiments of the present invention, the
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`plurality of switches are arranged to be triggered on the
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`leading and falling edge of an inverse of the differential
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`output signal.
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`In exemplary embodiments of the present invention, a
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`first switch receives the odd number data of the output signal
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`of the data input buffer and passes the odd number data of
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`the output signal to a first of the plurality of latches.
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`In exemplary embodiments of the present invention, the
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`data buffer is a data input buffer instead of, or in addition to,
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`a data strobe buffer.
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`In exemplary embodiments of the present invention, the
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`semiconductor memory device further includes a data strobe
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`input buffer for receiving an inverse data signal or a refer-
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`ence voltage, respectively, depending on a level of a control
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`signal, and outputting at least two differential output signals,
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`a control circuit for outputting the control signal to said data
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`strobe input buffer, and a data write circuit for receiving the
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`data input signal from the data input buffer and the writing
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`even number data of the data input signal into a first latch in
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`response to a rising edge of the output data signal and
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`writing odd number data of the data input signal into a
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`second latch in response to a falling edge of the output data
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`strobe signal.
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`Exemplary embodiments of the present invention are also
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`directed to a method of controlling propagation delay time
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`of a semiconductor memory, including receiving an inverse
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`data signal or a reference voltage, respectively, depending
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`on a level of a control signal, receiving a data signal and
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`either the inverse data signal or the reference voltage, and
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`amplifying and outputting at least two different differentially
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`amplified signals.
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`In exemplary embodiments of the method of the present
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`invention, the inverse data signal is an inverse data strobe
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`signal and the data signal is a data strobe signal.
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`In exemplary embodiments of the method of the present
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`invention, in a single mode, the reference voltage is received
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`and a level of the control signal is a first logic state and in
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`a dual mode, the inverse data strobe signal is received and
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`the level of the control signal is a second logic state.
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`In exemplary embodiments of the method of the present
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`invention, the control signal is received from an external
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`source.
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`In exemplary embodiments of the method of the present
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`invention, the method also includes receiving an external
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`command and an address and generating the control signal,
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`signal.
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`In exemplary embodiments of the present invention, the
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`control circuit includes a bonding pad circuit, wherein a
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`connection to Vcc or ground determines a level of the
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`control signal.
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`the
`In exemplary embodiments of the present invention,
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`differential amplifier unit
`includes a single differential
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`amplifier.
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`In exemplary embodiments of the present invention, the
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`semiconductor memory device further includes a compen-
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`sating circuit for compensating one of the inverse data strobe
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`signal, the reference voltage, or the data strobe signal or one
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`of the at least two different differentially amplified signals so
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`that each of at least two differential output signals have
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`substantially the same delay time.
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`In exemplary embodiments of the present invention, the
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`compensating circuit includes a delay circuit for receiving
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`the differentially amplified signal
`from said differential
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`amplifier circuit, said delay circuit including a delay for
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`delaying the differentially amplified signal, at
`two
`least
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`additional switches for passing the differentially amplified
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`signal or the delayed differentially amplified signal, as one
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`of the at least two differential output signals, depending on
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`the level of the control signal.
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`In exemplary embodiments of the present invention, the
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`compensating circuit includes a dummy load applied to one
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`of the inverse data strobe signal, the reference voltage, or the
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`data strobe signal.
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`In exemplary embodiments of the present invention, the
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`differential amplifier unit includes at least two differential
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`amplifiers.
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`In exemplary embodiments of the present invention, a
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`gain of a first of the at least two differential amplifiers is
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`substantially different from a gain of a second of the at least
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`two differential amplifiers so that each of at
`least
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`differential output signals have substantially the same delay
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`time.
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`In exemplary embodiments of the present invention, a
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`gain of a first of the at least two differential amplifiers is
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`substantially the same as a gain of a second of the at least
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`two differential amplifiers.
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`In exemplary embodiments of the present invention, the
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`semiconductor memory device further includes a compen-
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`sating circuit for compensating one of the inverse data strobe
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`signal, the reference voltage, or the data strobe signal or one
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`of the at least two different differentially amplified signals so
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`that each of at least two differential output signals have
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`substantially the same delay time.
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`In exemplary embodiments of the present invention, the
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`compensating circuit includes a delay circuit for receiving
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`the differentially amplified signal
`from said differential
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`amplifier circuit, said delay circuit including a delay for
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`delaying the differentially amplified signal, at
`two
`least
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`additional switches for passing the differentially amplified
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`signal or the delayed differentially amplified signal, as one
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`of the at least two differential output signals, depending on
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`the level of the control signal.
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`In exemplary embodiments of the present invention, the
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`compensating circuit includes a dummy load applied to one
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`of the inverse data strobe signal, the reference voltage, or the
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`data strobe signal.
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`In exemplary embodiments of the present invention, the
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`semiconductor memory device further includes data input
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`buffer for receiving a data signal and a reference voltage and
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`

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`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 18 of 24 PageID# 10534
`Case 3:14-cv-00757-REP-DJN Document 81-4 Filed 04/10/15 Page 18 of 24 Page|D# 10534
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`US 6,819,602 B2
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`wherein a level of the control signal determines an operation
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`mode of the semiconductor memory.
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`In exemplary embodiments of the method of the present
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`invention, a state of a fuse determines a level of the control
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`signal.
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`In exemplary embodiments of the method of the present
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`invention, a connection to Vcc or ground via a bonding pad
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`determines a level of the control signal.
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`In exemplary embodiments of the method of the present
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`invention, the amplifying is performed by a single differen-
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`tial amplifier.
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`In exemplary embodiments of the method of the present
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`invention, the method further comprises compensating one
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`of the inverse data strobe signal, the reference voltage, or the
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`least
`data strobe signal or one of the at
`two different
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`differentially amplified signals so that each of at least two
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`differential output signals have substantially the same delay
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`time.
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`In exemplary embodiments of the method of the present
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`invention, the compensating includes receiving the differ-
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`entially amplified signal and delaying the differentially
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`amplified signal, and outputting the differentially amplified
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`signal or the delayed differentially amplified signal, as one
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`of the at least two differential output signals, depending on
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`the level of the control signal.
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`In exemplary embodiments of the method of the present
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`invention, the compensating is performed with a dummy
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`load applied to one of the inverse data strobe signal, the
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`reference voltage, or the data strobe signal.
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`In exemplary embodiments of the method of the present
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`invention,
`the amplifying is performed by at
`least
`two
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`differential amplifiers.
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`In exemplary embodiments of the method of the present
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`invention, a gain of a first of the at least two differential
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`amplifiers is substantially different from a gain of a second
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`of the at least two differential amplifiers so that each of at
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`least two differential output signals have substantially the
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`same delay time.
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`In exemplary embodiments of the method of the present
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`invention, a gain of a first of the at least two differential
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`amplifiers is substantially the same as a gain of a second of
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`the at least two differential amplifiers.
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`In exemplary embodiments of the method of the present
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`invention, the method further comprises compensating one
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`of the inverse data strobe signal, the reference voltage, or the
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`least
`data strobe signal or one of the at
`two different
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`differentially amplified signals so that each of at least two
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`differential output signals have substantially the same delay
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`time.
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`In exemplary embodiments of the method of the present
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`invention, the compensating includes receiving the differ-
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`entially amplified signal, delaying the differentially ampli-
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`fied signal, and outputting the differentially amplified signal
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`or the delayed differentially amplified signal, as one of the
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`at least two differential output signals, depending on the
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`level of the control signal.
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`In exemplary embodiments of the method of the present
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`invention, the compensating is performed with a dummy
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`load applied to one of the inverse data strobe signal, the
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`reference voltage, or the data strobe signal.
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`In exemplary embodiments of the method of the present
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`invention,
`the method further includes receiving a data
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`signal and a reference voltage and outputting a data input
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`signal, outputting the control signal, and receiving the data
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`input signal and the writing even number data of the data
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`input signal into a first latch in response to a rising edge of
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`the output data signal and writing odd number data of the
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`data input signal into a second latch in response to a falling
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`edge of the output data strobe signal.
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`In exemplary embodiments of the method of the present
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`invention, the first latch includes a plurality of latches and a
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`plurality of switches, arranged alternatively.
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`In exemplary embodiments of the method of the present
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`invention,
`the plurality of switches are arranged to be
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`triggered on the leading and falling edge of an inverse of the
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`differential output signal.
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`In exemplary embodiments of the method of the present
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`invention, a first switch receives the even number data of the
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`output signal and passes the even number data of the output
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`signal to a first of the plurality of latches.
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`In exemplary