Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 1 of 22 PageID# 10486
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 1 of 22 Page|D# 10486
`
`
`
`
`EXHIBIT B
`
`EXHIBIT B
`
`
`
`
`
`
`
`

`

`ease3:14-cv-oo7s7-REP-DJN Documentsl-lllllllllllllllllllllllllllllllllllllllllllllllllllallllllllllllllllhs?
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 2 of 22 PageID# 10487
`USOO6262938B1
`
`(12) United States Patent
`Lee et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 6,262,938 B1
`Jul. 17, 2001
`
`(54) SYNCHRONOUS DRAM HAVING POSTED
`CAS LATENCY AND METHOD FOR
`CONTROLLING CAS LATENCY
`
`(75)
`
`Inventors: Jung-hoe Lee; Choong-sun Shin;
`Dong-yang lee, all of Kyungki-do
`(KR)
`
`5 4335.950
`6.088.255 "
`
`11.11998 Park et al. .
`7;"2000 Matsuzaki ct al.
`
`365/76
`
`* cited by examiner
`
`Primary Examiner—David Nelms
`Assistant Emetirrer—Thong Le
`(74) Attorney. Agent, or Firm—Jones Valentine, L.L.C.
`
`(73) Assignee: Samsung Electmnics Co., Ltd., Suwon
`(KR)
`
`(57)
`
`ABSTRACT
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`USO 154(h) by 0 days.
`
`(21) Appl. No.: 09/518,144
`
`(22)
`
`Filed:
`
`Mar. 3, 2000
`
`(30)
`
`Mar. 3, 1999
`Jun. 5 1000
`
`Int. Cl.7
`(51)
`(52) U.S. C].
`
`Foreign Application Priority Data
`
`
`(KR)
`(KR)
`
`.............. 9945939
`................................................. 00-20821
`
`GllC 8/00
`.......................... 365/23336519,4 365/240;
`3653236
`365-’78, 194, 205,
`36523002, 230.03, 236, 240, 233
`
`(58) Field of Search
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`A synchronous DRAM (SDRAM) having a posted column
`access strobe (CAS) latency and a method of controlling
`(.‘AS latency are provided. In order to control a delay time
`from the application of a CAS command and a column
`address to the beginning of memory, reading or writing
`operations in units of clock cycles, a first method of pro-
`graming the delay titne as a mode register set (MRS) and a
`second method of detecting the delay time using an internal
`signal and an external signal, are provided. In the second
`method, the SDRAM can include a counter for controlling
`the CAS latency. This counter controls the CAS latency of
`the SDRAM by generating a signal for controlling the (.‘AS
`latency according to the number of clock cycles of a clock
`signal from the generation of a row access command to a
`column access command in the same memory bank and
`reading the signal. It is therefore possible to appropriately
`perform a posted CAS latency operation and a general CAS
`latency operation by the SDRAM without an additional
`MRS command according to this SDRAM and the method
`of controlling the CAS latency.
`
`5,587,050 * 12/1006 Sawada etal.
`
`3655201
`
`24 Claims, 11 Drawing Sheets
`
`MEMORY
`CELL
`BANK
`
`-ECODE
`
`CLK
`
`
`
`
`RCLmin
`RACC
`CLK
`CACC
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 3 of 22 PageID# 10488
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 3 of 22 Page|D# 10488
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 4 of 22 PageID# 10489
`Case 3:14-cv-00757-REP-DJN Document 81
`-2 Filed 04/10/15 Page 4 of 22 Page|D# 10489
`
`US. Patent
`
`Jul. 17, 2001
`
`Sheet 2 0f 11
`
`US 6,262,938 B1
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 5 of 22 PageID# 10490
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 5 of 22 Page|D# 10490
`
`US. Patent
`
`Jul. 17,2001
`
`Sheet 3 of 11
`
`US 6,262,938 B1
`
`117
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 6 of 22 PageID# 10491
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 6 of 22 Page|D# 10491
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 7 of 22 PageID# 10492
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 7 of 22 Page|D# 10492
`
`FIG. 5
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 8 of 22 PageID# 10493
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 8 of 22 Page|D# 10493
`
`US. Patent
`
`Jul. 17, 2001
`
`Sheet 6 0f 11
`
`US 6,262,938 B1
`
`
`
`609
`
`611
`
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`
`
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`

`

`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 9 of 22 PageID# 10494
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 9 of 22 Page|D# 10494
`
`1110
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 10 of 22 PageID# 10495
`Case 3:14-cv-00757-REP-DJN Document 81
`-2 Filed 04/10/15 Page 10 0f 22 Page|D# 10495
`
`US. Patent
`
`Jul. 17, 2001
`
`Sheet 8 of 11
`
`US 6,262,938 B1
`
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 11 of 22 PageID# 10496
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 11 of 22 Page|D# 10496
`
`US. Patent
`
`Jul. 17,2001
`
`Sheet 9 of 11
`
`US 6,262,938 B1
`
`FIG. 9
`
`807
`
`/
`
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`
`RACC,CACC
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`
`
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`
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`
`(WU/S113
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 12 of 22 PageID# 10497
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 12 of 22 Page|D# 10497
`
`US. Patent
`
`Jul. 17,2001
`
`Sheet 10 of 11
`
`US 6,262,938 B1
`
`FIG. 12
`
`
`
`1201
`
`MEASURE RCL AND RSE
`
` 1203
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 13 of 22 PageID# 10498
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 13 of 22 Page|D# 10498
`
`US. Patent
`
`Jul. 17,2001
`
`Sheet 11 of 11
`
`US 6,262,938 B1
`
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 14 of 22 PageID# 10499
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 14 of 22 Page|D# 10499
`
`
`
`US 6,262,938 B1
`
`
`
`
`1
`SYNCHRONOUS DRAM HAVING POSTED
`
`
`
`CAS LATENCY AND METHOD FOR
`
`
`
`
`
`CONTROLLING CAS LATENCY
`
`
`
`
`
`
`This application relies for priority upon Korean Patent
`
`
`
`
`
`
`
`Application Nos. 99-6939 and 99-20821, filed on Mar. 3,
`
`
`
`
`
`
`
`
`1999, and Jun. 5, 1999, respectively, the contents of which
`
`
`
`
`
`
`
`
`
`are herein incorporated by reference in their entirety.
`
`
`
`
`
`
`
`
`BACKGROUND OF THE INVENTION
`
`
`
`
`
`
`
`
`
`
`The present invention relates to a synchronous DRAM
`
`
`
`
`
`
`
`
`(SDRAM). More particularly, the present invention relates
`
`
`
`
`
`
`
`to an SDRAM having a column access strobe (CAS) latency,
`
`
`
`
`
`
`
`
`
`
`as well as a method for controlling the CAS latency.
`
`
`
`
`
`
`
`
`
`
`In general, an SDRAM is synchronized with a clock
`
`
`
`
`
`
`
`
`
`signal input from outside the circuit and so the read or write
`
`
`
`
`
`
`
`
`
`
`
`
`operation of the SRAM is controlled. FIG. 13 describes the
`
`
`
`
`
`
`
`
`
`
`latency from the application of a row access command or a
`
`
`
`
`
`
`
`
`
`
`column access command to the output of data.
`
`
`
`
`
`
`
`
`The number of clock cycles of an external clock signal
`
`
`
`
`
`
`
`
`
`
`from the application of a row access command to the output
`
`
`
`
`
`
`
`
`
`
`of first data is called the RAS latency (RL). The number of
`
`
`
`
`
`
`
`
`
`
`
`
`clock cycles of the external clock signal from the application
`
`
`
`
`
`
`
`
`
`
`of a column access command to the output of the first data
`
`
`
`
`
`
`
`
`
`
`
`is called the CAS latency (CL). The number of clock cycles
`
`
`
`
`
`
`
`
`
`
`
`of the external clock signal from the application of the row
`
`
`
`
`
`
`
`
`
`
`
`access command to the application of the column access
`
`
`
`
`
`
`
`
`
`command with respect to the same memory bank is called
`
`
`
`
`
`
`
`
`
`
`the RAS-CAS latency (RCL). The relationship between
`
`
`
`
`
`
`
`RCL, RL, and CL is shown in Equation 1.
`
`
`
`
`
`
`
`
`
`
`RL=RCL+CL
`
`
`
`(1)
`
`
`When the minimum value of the RAS latency in the
`
`
`
`
`
`
`
`
`
`
`frequency of a specific external clock signal is RL
`then
`
`
`
`
`
`
`
`
`
`RL must satisfy Equation 2.
`
`
`
`
`
`
`RL iRLm-n
`
`(2)
`
`
`When the minimum value of the CAS latency in the
`
`
`
`
`
`
`
`
`
`
`frequency of the specific external clock signal is Cme, then
`
`
`
`
`
`
`
`
`
`
`min
`(the minimum RAS-CAS latency) is expressed as
`RCL
`
`
`
`
`
`
`
`
`shown in Equation 3.
`
`
`
`
`min—
`RCL —RL
`min
`min_
`
`CL
`
`(3)
`
`
`
`
`
`
`In a system using an SDRAM, a function of normally
`
`
`
`
`
`
`
`
`
`outputting data even when RCL<RCme, namely, in posted
`
`
`
`
`
`
`
`CAS latency, is required in order to improve the perfor-
`
`
`
`
`
`
`
`
`
`mance of the system. In this application, posted CAS latency
`
`
`
`
`
`
`
`
`
`refers to the fact that the CAS command comes earlier than
`
`
`
`
`
`
`
`
`
`
`the conventional RCLml—n. In other words,RL§RLml—n, which
`
`
`
`
`
`
`is generally the product specification, must be satisfied even
`
`
`
`
`
`
`
`
`when RCL<RCme.
`In order
`to satisfy the equality
`
`
`
`
`
`
`
`RLERLml-n in the posted CAS latency, the CAS latency CL
`
`
`
`
`
`
`
`
`must satisfy Equation 4
`
`
`
`
`mm
`CL>CL . +(RCme—RCL)
`
`
`
`
`
`
`
`
`(4)
`
`
`In a conventional SDRAM, since the specification of
`
`
`
`
`
`
`
`
`(RCLml—n—RCL)<0 is required, it is enough to determine the
`
`
`
`
`
`
`
`
`
`CL, which guarantees the minimum CAS latency Cme by
`
`
`
`
`
`
`
`
`
`a mode register set (MRS) command. However, in a posted
`
`
`
`
`
`
`
`
`
`
`CAS state, it is possible to input a CAS command (including
`
`
`
`
`
`
`
`
`
`
`a column address command), which controls an appropriate
`
`
`
`
`
`
`
`
`delay time and the latency of a data path only when each of
`
`
`
`
`
`
`
`
`
`
`
`
`the values in Equation 4, i.e., (RCLml—n—RCL) and Cme, are
`
`
`
`
`
`
`
`
`
`
`known.
`
`
`
`
`
`2
`SUMMARY OF THE INVENTION
`
`
`
`
`It
`invention to provide a
`is an object of the present
`
`
`
`
`
`
`
`
`
`
`
`synchronous DRAM (SDRAM) by which it is possible to
`
`
`
`
`
`
`
`
`
`perform a posted column access strobe (CAS) command.
`
`
`
`
`
`
`
`
`It is another object of the present invention to provide a
`
`
`
`
`
`
`
`
`
`
`method for outputting data using the SDRAM.
`
`
`
`
`
`
`
`Accordingly, to achieve the first object, A synchronous
`
`
`
`
`
`
`
`
`DRAM (SDRAM), operating in synchronization with a
`
`
`
`
`
`
`
`clock signal, is provided. The SDRAM comprises a memory
`
`
`
`
`
`
`
`
`
`bank having a plurality of memory cells arranged in rows
`
`
`
`
`
`
`
`
`
`
`and columns, a column decoder for selecting a column of the
`
`
`
`
`
`
`
`
`
`memory bank, a column address input port for inputting a
`
`
`
`
`
`
`
`
`
`
`column address that selects the column of the memory bank,
`
`
`
`
`
`
`
`
`
`
`a first shift register for delaying the column address by a first
`
`
`
`
`
`
`
`
`
`
`
`number of delay clock cycles between the column address
`
`
`
`
`
`
`
`
`
`input port and the column decoder, and a delay counter for
`
`
`
`
`
`
`
`
`
`
`
`sensing the number of clock cycles RCL of the clock signal
`
`
`
`
`
`
`
`
`
`
`
`from the application of the row access command to the
`
`
`
`
`
`
`
`
`
`
`application of the column access command with respect to
`
`
`
`
`
`
`
`
`
`the same bank, and for providing a first delay clock control
`
`
`
`
`
`
`
`
`
`
`
`signal
`to the first shift register. Rme is the minimum
`
`
`
`
`
`
`
`
`
`
`number of clock cycles of the clock signal required from the
`
`
`
`
`
`
`
`
`
`
`
`application of a row access command to the output of the
`
`
`
`
`
`
`
`
`
`
`
`data of the memory, and Cme is the minimum number of
`
`
`
`
`
`
`
`
`
`
`
`clock cycles of the clock signal required from the applica-
`
`
`
`
`
`
`
`
`
`tion of a column access command to the output of the data
`
`
`
`
`
`
`
`
`
`
`
`of the memory cell. The first delay clock control signal has
`
`
`
`
`
`
`
`
`
`
`
`information on the difference between RCL and (Rme—
`
`
`
`
`
`
`
`CLml—n), and the first number of delay clock cycles is
`
`
`
`
`
`
`
`
`
`
`determined in response to the difference between RCL and
`
`
`
`
`
`
`
`
`
`(Rme—Cme).
`
`
`The first shift register my comprise a plurality of registers
`
`
`
`
`
`
`
`
`
`serially coupled to each other for continuously transmitting
`
`
`
`
`
`
`
`
`the column address in response to the clock signal of every
`
`
`
`
`
`
`
`
`
`
`
`period, and a multiplexer for selectively providing one
`
`
`
`
`
`
`
`
`signal among the output signals of the plurality of registers
`
`
`
`
`
`
`
`
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`
`to the column decoder. The registers are preferably D
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`flip-flops.
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`The delay counter may comprise a down counter for
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`reducing the value of (RLml—n—CLml-n) by 1 in response to the
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`clock signal, a register for providing a first delay clock
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`control signal having information on an output value stored
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`as an output value of the down counter when the column
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`access command is generated or an output value of the down
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`counter having the value of 0 to the first shift register after
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`the row access command is generated, a clock controller that
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`is disabled when the output value of the down counter is 0,
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`for providing a first clock control signal which is enabled by
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`the generation of the row access command and responds to
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`the clock signal
`to the down counter, and a logic unit
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`disabled by the generation of the column access command,
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`for providing a second clock control signal that is enabled by
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`the generation of the row access command and responds to
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`the first clock control signal. The delay counter may further
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`comprise an RCL measuring unit for providing an output
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`signal activated by the generation of the row access com-
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`mand and disabled by the generation of the column access
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`command to the logic unit.
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`The synchronous DRAM may further comprise a second
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`shift register for delaying the output data of a selected
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`memory cell by CLml—n, and a buffer for buffering the output
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`signal of the second shift register and delaying the output
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`signal of the second shift register by a second number of
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`delay clock cycles in response to a second predetermined
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`delay clock control signal.
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`The SDRAM may further comprising a buffer controller
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`for generating a second delay clock control signal
`for
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`5
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`60
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`65
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`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 15 of 22 PageID# 10500
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 15 of 22 Page|D# 10500
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`US 6,262,938 B1
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`3
`controlling the buffer. The buffer controller itself may com-
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`prise a first register for delaying the column access com-
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`mand by the second number of delay clock cycles and
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`outputting the delayed column access command, every cycle
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`of the clock signal, and a second register for delaying the
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`output signal of the first register by Cme and generating a
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`second delay control signal for controlling the buffer.
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`A synchronous DRAM (SDRAM) operating in synchro-
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`nization with a clock signal, is also provided. The SDRAM
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`comprises a memory bank having a plurality of memory
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`cells arranged in rows and columns, a column decoder for
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`selecting a column of the memory bank, a pair of bit lines
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`for outputting data from the selected column, a sense ampli-
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`fier for amplifying the data of the bit lines, a column address
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`input port for inputting a column address for selecting the
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`column of the memory bank, a first shift register for delaying
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`the column address by a first number of delay clock cycles
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`between the column address input port and the column
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`decoder, and a delay counter for providing a first delay clock
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`control signal having information on the difference between
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`RCL and SAE to the first shift register. RCL is the number
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`of clock cycles of the clock signal from the application of a
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`row access command to the application of a column access
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`command with respect to the same bank; SAE is the number
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`of clock cycles of the clock signal from the application of the
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`row access command to the point of time at which the sense
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`amplifier is enabled are determined; and the first number of
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`delay clock cycles is determined in response to the differ-
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`ence between RCL and SAE.
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`The first shift register may comprise a plurality of regis-
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`ters serially coupled to each other, for continuously trans-
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`mitting the column address every cycle of the clock signal,
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`and a multiplexer for selectively providing one signal among
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`the output signals of the registers to the column decoder in
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`response to the difference between RCL and SAE.
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`Preferably, the registers are D flip-flops.
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`The delay counter may comprise a first counting circuit
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`for counting SAE and generating a first number of clock
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`cycles, a second counting circuit for counting RCL and
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`generating a second number of clock cycles, and a subtracter
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`for calculating a third number of clock cycles by subtracting
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`the first number of clock cycles from the second number of
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`clock cycles and using 0 as the third number of clock cycles
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`when the first number of clock cycles is larger than the
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`second number of clock cycles.
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`The first counting circuit may comprise a first logic latch
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`unit for generating a first logic latch output signal activated
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`by the generation of the row access command and deacti-
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`vated by the activation of the sense amplifier enable signal,
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`and a first counter enabled in a period when the first logic
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`latch output signal is activated, for counting the number of
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`clock cycles of the clock signal generated in the activation
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`period, and for generating the number of first clock cycles.
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`The second counting circuit may comprise a second logic
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`latch unit for generating a second logic latch output signal
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`activated by the generation of the row access command and
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`deactivated by the generation of the column access
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`command, and a second counter enabled in a period where
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`the second logic latch output signal is activated, for counting
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`the number of clock cycles of the clock signal generated in
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`the activation period, and for generating the number of
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`second clock cycles.
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`The delay counter may comprise a logic unit for gener-
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`ating a logic output signal that is activated in response to the
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`generation of the column access command and is deacti-
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`vated in response to a sense amplifier enable signal, the logic
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`4
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`output signal operating to enable the sense amplifier, and a
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`clock counter for counting the number of clock cycles of the
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`clock signal generated in a period where the output signal of
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`the logic unit is activated.
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`The synchronous DRAM may further comprise a second
`
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`
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`shift register for delaying the output data of the memory cell
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`by Cer-m where Cme is the minimum number of clock
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`cycles of the clock signal required from the application of a
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`column access command to the output of the data of the
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`memory cell, and a buffer for buffering the output signal of
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`the second shift register, and for delaying the output signal
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`of the second shift register by the first number of delay clock
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`cycles in response to a second delay clock control signal.
`
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`The synchronous DRAM may further comprise a buffer
`
`
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`
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`controller for generating a second delay clock control signal
`
`
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`
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`for controlling the buffer. The buffer controller may itself
`
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`comprise a first register for delaying the column access
`
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`command by the first number of delay clock cycles and
`
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`
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`outputting the delayed column access command, and a
`
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`second register for generating a second delay control signal
`
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`for delaying the output signal of the first register by the first
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`number of delay clock cycles and controlling the buffer
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`every cycle of the clock signal. The first delay clock signal
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`is preferably provided from outside of the SDRAM.
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`A synchronous DRAM (SDRAM) synchronized with a
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`clock signal after predetermined column access strobe
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`(CAS) latency has lapsed from a column access command,
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`is also provided. The SDRAM comprises a memory bank
`
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`having a plurality of memory cells arranged in rows and
`
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`columns, and a decoder for selecting one of the memory
`
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`cells based on a column address and a row address. The CAS
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`latency is determined by the number of clock cycles of the
`
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`clock signal from the application of a row access command
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`to the application of a column access command with respect
`
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`to the memory bank.
`
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`
`
`A synchronous DRAM (SDRAM) is also provided, com-
`
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`
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`prising a memory bank having a plurality of memory cells
`
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`arranged in rows and columns, and a decoder for selecting
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`one of the memory cells based on a column address and a
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`row address. RLml—n is the minimum number of clock cycles
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`of the clock signal required from the application of a row
`
`
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`access command to the output of the data of the selected
`
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`memory cell; Cme is the minimum number of clock cycles
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`of the clock signal required from the application of a column
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`access command to the output of the data of the selected
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`memory cell; and RCL is the number of clock cycles of the
`
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`clock signal from the application of a row access command
`
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`to the application of a column access command with respect
`
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`to the memory bank. A CAS latency, which is the number of
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`clock cycles of the clock signal required from the applica-
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`tion of the column access command to the output of data, is
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`determined to be (RLmin—RCL) when RCL is less than
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`(RLml—n—CLml-n), and is determined to be CL when RCL is
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`not less than (RLml—n—CLml-n). The quantity (RL —CL,m-n) is
`
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`
`
`preferably input from the outside of the SDRAM.
`
`
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`
`
`
`
`
`A synchronous DRAM (SDRAM), operating in synchro-
`
`
`
`
`
`
`
`nization with a clock signal, is also provided. The SDRAM
`
`
`
`
`
`
`
`
`
`
`comprises a memory bank having a plurality of memory
`
`
`
`
`
`
`
`
`
`cells arranged in rows and columns, a column decoder for
`
`
`
`
`
`
`
`
`
`
`selecting the column of the memory bank, a pair of bit lines
`
`
`
`
`
`
`
`
`
`
`
`
`for outputting data from a selected memory cell, and a sense
`
`
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`
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`
`
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`amplifier for amplifying the data of the pair of bit lines.
`
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`
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`RLml—n is the minimum number of clock cycles of the clock
`
`
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`
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`
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`signal required from the application of a row access com-
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`mand to the output of the data of the selected memory cell;
`
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`Cme is the minimum number of clock cycles of the clock
`
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`10
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`15
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`20
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`25
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`30
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`35
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`40
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`45
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`50
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`
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`55
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`60
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`
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`65
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 16 of 22 PageID# 10501
`Case 3:14-cv-00757-REP-DJN Document 81-2 Filed 04/10/15 Page 16 of 22 Page|D# 10501
`
`
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`US 6,262,938 B1
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`
`
`
`6
`According to the SDRAM and the method for controlling
`
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`the CAS latency of the present invention, a posted CAS
`
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`latency operation and a general CAS latency operation can
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`be appropriately performed by the SDRAM without a mode
`
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`register set (MRS) command.
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
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`5
`signal required from the application of a column access
`
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`command to the output of the data of the selected memory
`
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`cell; RCL is the number of clock cycles of the clock signal
`
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`
`
`
`
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`from the application of a row access command to the
`
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`
`
`
`
`
`
`
`application of a column access command with respect to the
`
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`
`
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`
`
`
`memory bank; and SAE is the number of clock cycles of the
`
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`
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`
`
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`clock signal from the application of the row access com-
`
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`mand to the point of time at which the sense amplifier is
`
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`enabled. The CAS latency, which is the number of clock
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`cycles of the clock signal required from the application of
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`the column access command to the output of data,
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`determined by the difference between RCL and SAE.
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`The CAS latency is preferably determined to be (RLml—n—
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`RCL) when RCL is less than SAE and the difference
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`between RCL and SAE is no less than the predetermined
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`number of reference clock cycles, and is determined to be
`Cme when RCL is no less than SAE and the difference
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`between RCL and SAE is no more than the number of
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`reference clock cycles.
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`A method of controlling CAS latency of an SDRAM,
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`synchronized with a clock signal, that includes a memory
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`bank having a plurality of memory cells arranged in rows
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`and columns and outputs the data of a selected memory cell,
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`is also provided. The method comprises inputting a quantity
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`(RLmin—CLml—n) from the outside of the SDRAM, where
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`RLml—n is the minimum number of clock cycles of the clock
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`signal required from the application of a row access com-
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`mand to the output of the data of the selected memory cell,
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`and Cme is the minimum number of clock cycles of the
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`clock signal required from the application of a column
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`access command to the output of the data of the selected
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`memory cell, comparing RCL with (RLmin—CLml—n), where
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`RCL is a number of clock cycles of the clock signal from the
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`application of a row access command to the application of
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`a column access command with respect to the memory bank,
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`determining CAS latency, which is the number of clock
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`cycles of the clock signal required from the application of
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`the column access command to the output of the data, to be
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`(RLmin—RCL) when RCL is less than (RLmin—Clmm), and
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`determining the CAS latency to be Cme when RCL is no
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`less than (RL - —CLmm
`min) ’
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`A of controlling CAS latency of an SDRAM which
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`includes a bank having a plurality of memory cells arranged
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`in rows and columns that outputs the data of a selected
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`memory cell in synchronization with the clock signal, is also
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`provided. The method comprises sensing RCL, where RCL
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`is the number of clock cycles of the clock signal from an
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`application of a row access command to an application of a
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`column access command, sensing SAE, where SAE is the
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`number of clock cycles of the clock signal from the appli-
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`cation of the row access command to a point of time at which
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`a sense amplifier is enabled, comparing RCL with SAE,
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`determining CAS latency, which is the number of clock
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`cycles of the clock signal required from the application of
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`the column access command to the output of the data, to be
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`m
`(RLm. —RCL) when RCL is less than SAE and the difference
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`between RCL and SAE is not less than a predetermined
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`number of reference clock cycles, and determining the CAS
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`latency to be Cme when RCL is not less than SAE or the
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`difference between RCL and SAE is less than the predeter-
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`mined number of reference clock cycles. RLml—nis the mini-
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`mum number of clock cycles of a clock signal required from
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`the application of a row access command to the output of the
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`data of the selected memory cell; and Cme is the minimum
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`number of clock cycles of the clock signal required from the
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`application of a column access command to the output of the
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`data of the selected memory cell.
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`10
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`15
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`25
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`60
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`65
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`The above objects and advantages of the present invention
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`will become more apparent by describing in detail preferred
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`embodiments thereof with reference to the attached draw-
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`ings in which:
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`FIG. 1 is a block diagram schematically showing a
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`synchronous DRAM (SDRAM) having a posted column
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`access strobe (CAS) latency according to a first preferred
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`embodiment of the present invention;
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`FIG. 2 is a detailed circuit diagram showing the counter
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`of FIG. 1;
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`FIG. 3 is a detailed circuit diagram showing the buffer
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`controller of FIG. 1;
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`FIG. 4 is a timing diagram of the main terminal of the
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`SDRAM in a posted CAS command mode according to the
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`first preferred embodiment;
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`FIG. 5 is a timing diagram of the main terminal of the
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`SDRAM in a general CAS command mode according to the
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`firs