Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 1 of 33 PageID# 10453
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 1 of 33 Page|D# 10453
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`EXHIBIT A
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`EXHIBIT A
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`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 2 of 33 PageID# 10454
`Case 3:14-CV-00757-REP-DJN Document 81-flllfllmmnflflMIHMHImmlmmlmfllr0454
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`U8005860158A
`
`Unlted States Patent
`
`[19]
`
`[11] Patent Number:
`
`5,860,158
`
`Pai et al.
`
`[45] Date of Patent:
`
`Jan. 12, 1999
`
`[54] CACHE CONTROL UNIT WITH A CACHE
`REQUEST 'l‘RANSAC’l‘lON-ORIEN’I‘ED
`PROTOCOL
`
`_
`[7“]
`
`.
`.
`.
`.
`.
`.
`‘
`[memors' $110112“;53:2,hgtltlII—illtgi’é‘llg' Nguyen’
`
`[73] Assignee: Samsung Eleetmnies Company, 1.111.,
`5‘70"], R311 Of Korea
`
`[21] Appl. No.: 751,149
`
`[22]
`
`Filed:
`
`Nov. 15, 1996
`
`Int. Cl.6 ...................................................... G061“ 13/00
`[51]
`[52] US. Cl. ............................................. 711/118; 711/130
`[58] Field of Search ..................................... 711t119, 120,
`711,130,140, 118
`
`[56]
`
`References Cited
`.
`..
`‘
`‘
`U'b‘ 1”“th DOCUMEN I 5
`911987 Keeley etal.
`4.1195943
`4.701.844 1011987 Thompson etal.
`4.707.734
`1111987 Ryan et al.
`
`
`
`7111140
`711.5119
`7111140
`
`711/3
`251990 Sachs ct al.
`4.890.275
`. 395x425
`12.31994 Chang etal.
`5.377.345
`
`. 395.5800
`551995 Fllis c1 al.
`......
`5.4l8,973
`.
`651906 Balmcr et al.
`..
`5.524.265
`
`.. 395/1821
`5574.849 1151.906 Sonnicr et al.
`.
`
`5.659.782
`8.1997 Senter et al.
`3951811023
`Primary Examiner—Tod R. Swann
`Assistant Examiner—Felix B. Lee
`Attorney, A gent, 0r FirmfiSkjerven, Morrill, MacPherson,
`Franklin & Friel, L.L.P.; Stephen A. Terrile
`
`[57J
`
`ABSTRACT
`
`A cache control unit and a method of controlling a cache.
`The cache is coupled to a cache accessing device. A first
`cache request is received from the device. A request iden-
`Iificalion information is assigned 10 the first cache request
`and provided to the requesting device.
`'lhc first cache
`request may begin to be processed. A second cache request
`is received from the cache accessing device. The second
`cache request
`is assigned to the first cache request and
`provided to the requesting device. The first and second cache
`PCQUCSIS are finally fUIIS'Scn’iCCd-
`
`37 Claims, 8 Drawing Sheets
`
`ARM_CCU INTERFACE STATE MACHINE (A_SM)
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 3 of 33 PageID# 10455
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 3 of 33 Page|D# 10455
`
`
`US. Patent
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`
`
`Jan. 12, 1999
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`
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`Sheet 1 of 8
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`5,860,158
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`VECTOR EJCESSOR
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`GENERAL PURPOSE
`PROCESSOR
`
`
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`m
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`
`
`CACHE SYSTEM 130
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`
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`ROM L52
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`CACHE CONTROL UNIT @
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`182 ~
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`BITSTREAM
`PROCESSOR Lag .
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`INTERRUPT
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`CONTROLLER @ h
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`FIG.
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`1
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`INTERFACE
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`LOCAL BUS
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`MEMORY
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` SYSTEM TIMER
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`DEVICE
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`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 4 of 33 PageID# 10456
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 4 of 33 Page|D# 10456
`
`
`US. Patent
`
`
`
`Jan. 12, 1999
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`
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`
`
`
`Sheet 2 0f 8
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`5,860,158
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`
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`130
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`
`
`SRAM 210
`TAG 212 ROM 150
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`GPP ICACHE
`AG
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`1428
`42A
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`
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`
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`140
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`170
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`
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`ROM CACHE
`
`
`
`TAG
`
`
`M
`1%
`
`
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`
`
`TAG
`VECTOR ICACHE
`
`
`7_2A
`1728
`
`
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`
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`
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`TAG
`
`_7___14B
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`
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`CACHE CONTROL
`
`
`UNIT
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`m
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`VECTOR DCACHE
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`‘____74A
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`I'll
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`GPP
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`ADDRESS PIPELINE2—30
`232234236
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`
`I...
`VECTOR (INSTR)
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`GPP
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`_ATAPIPELINE—2_0
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`
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`IOBUS
`
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`FIG. 2
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 5 of 33 PageID# 10457
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 5 of 33 Page|D# 10457
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`SRAM m
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`||||||
`340 CACHE
`I MUX
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`GENERAL
`VECTOR
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`PURPOSE
`PROCESSOR
`
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`PROCESSOR
`12g
`
`
`m
`
`L __________
`
`
`FIG. 3
`
`
`
`
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 6 of 33 PageID# 10458
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 6 of 33 Page|D# 10458
`
`IOBUS ' 130
`
`
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`101 _RD_LAT
`
`FBUS
`190
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`
`421
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`CCU_DOUT
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`__________________
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`A‘iM-PAIA. _ _l
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`FIG. 4
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`mama'S'fl
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`89I‘098‘S
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`

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`---
`l' ——————————————————————————— ___7
`I
`|
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`I
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`:
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`
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 7 of 33 PageID# 10459
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 7 of 33 Page|D# 10459
`
`505— I
`
`505— 2
`
`150
`
`
`
`CACHE_-RAM
`
`WR_TAG
`
`RDT_AG
`
`CACHE_ROM
`
`MCP_BASE _AM_WRITE_ADR
`
`r ———————— 4—1]
`:
`ADR_03
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`
`I __ADR_MUXLAT
`
`WR_ADR_Q
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`
`VECTOR PROCESSOR
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`OPP
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`FBUS
`190
`
`IOBUS
`180
`
`FIG. 5
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 8 of 33 PageID# 10460
`Case 3:14-cv-OO757-REP-DJN Document 81-1 Filed 04/10/15 Page 8 of 33 Page|D# 10460
`
`
`US. Patent
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`
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`
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`Jan. 12, 1999
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`
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`Sheet 6 0f 8
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`5,860,158
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`ARM_CCU INTERFACE STATE MACHINE (A_SM)
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`CCU_FBUS INTERFACE STATE MACHINE (F_SM)
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`

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`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 9 of 33 PageID# 10461
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 9 of 33 Page|D# 10461
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`
`US. Patent
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`
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`Jan. 12, 1999
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`
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`Sheet 7 0f 8
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`5,860,158
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`DATA RECEIVER STATE MACHINE (D_SM)
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`FIG. 8
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`

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`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 10 of 33 PageID# 10462
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 10 of 33 Page|D# 10462
`
`US. Patent
`
`Jan. 12, 1999
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`Sheet 8 of 8
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`5,860,158
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`
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`READ STATE MACHINE
`(RD_SM)
`
`WRITE STATE MACHINE
`(WR_SM)
`
`
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`FIG. 9
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`

`

`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 11 of 33 PageID# 10463
`Case 3:14-cv-OO757-REP-DJN Document 81-1 Filed 04/10/15 Page 11 of 33 Page|D# 10463
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`5,860,158
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`1
`CACHE CONTROL UNIT WITH A CACHE
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`REQUEST TRANSACTION-ORIENTED
`
`PROTOCOL
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`COPYRIGHT NOTICE
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`A portion of the disclosure of this patent document
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`contains material which is subject to copyright protection.
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`The copyright owner has no objection to the facsimile
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`reproduction by anyone of the patent document or the patent
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`disclosure, as it appears in the Patent and Trademark Office
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`patent file or records, but otherwise reserves all copyright
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`rights whatsoever.
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`BACKGROUND OF THE INVENTION
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`1. Field of the Invention
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`This invention relates to providing processors with fast
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`memory access and, more particularly, to providing control
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`of cache memory systems.
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`2. Description of the Related Art
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`Processors often employ memories which are relatively
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`slow when compared to the clock speeds of the processors.
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`To speed up memory access for such processors, a relatively
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`small amount of fast memory can be used in a data cache.
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`A cache can mediate memory accesses and lessen the
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`average memory access time for all or a large portion of the
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`address space of a processor even though the cache is small
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`relative to the address space. Caches do not occupy a
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`specific portion of the address space of the processor but
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`instead include tag information which identifies addresses
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`for information in lines of the cache.
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`Typically, a cache compares an address received from a
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`processor to tag information stored in the cache to determine
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`whether the cache contains a valid entry for the memory
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`address being accessed. If such a cache entry exists (i.e. if
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`there is a cache hit), the processor accesses (reads from or
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`writes to) the faster cache memory instead of the slower
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`memory.
`In addition to tag information, a cache entry
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`typically contains a “validity” bit and a “dirty” bit which
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`respectively indicated whether the associated information in
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`the entry is valid and whether the associated information
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`contains changes to be written back to the slower memory.
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`there is a cache miss), access to the slower memory is
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`required for the cache to create a new entry for the just
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`accessed memory address.
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`Caches use cache policies such as “least recently used” or
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`“not last used” replacement techniques to determine which
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`existing entries are replaced with new entries. Typically,
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`computer programs access the same memory addresses
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`repeatedly. Therefore, the most recently accessed data is
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`likely to be accessed again soon after the initial access.
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`Because recently accessed data is available in the cache for
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`subsequent accesses, caches can improve access time across
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`the address space of the processor.
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`tasks, a “very long instruction word” (VLIW)
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`processor can perform multiple functions through a single
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`instruction. Also, a general purpose processor and a vector
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`processor may be integrated to operate in parallel. An
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`integrated multiprocessor is able to achieve high perfor—
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`mance with low cost since the two processors perform only
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`tasks ideally suited for each processor. For example, the
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`and performs overall system management while the vector
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`processor is used to perform parallel calculations using data
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`structures called “vectors”. (A vector is a collection of data
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`elements typically of the same type.) Multiprocessor con-
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`figurations are especially advantageous for operations
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`involving digital signal processing such as coding and
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`decoding video, audio, and communications data.
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`SUMMARY OF THE INVENTION
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`It has been discovered that accesses to a cache by multiple
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`devices may be managed by a cache control unit
`that
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`includes transaction identification logic to identify cache
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`accesses. Such an apparatus provides the advantage of
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`improving performance by increasing the speed of memory
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`apparatus allows the cache to service later arriving requests
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`before earlier arriving requests.
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`In one embodiment of the present invention, a cache is
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`coupled to a cache accessing device. Afirst cache request is
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`tion is assigned to the first cache request and provided to the
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`requesting device. The first-cache request may begin to be
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`cache accessing device. The second cache request
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`requesting device. The first and second cache requests are
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`finally fully serviced.
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`In another embodiment, a cache system includes a cache
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`for temporarily storing information and a cache control unit.
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`The cache control unit includes access control logic, iden-
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`tification logic, and result logic. The access control logic
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`receives and executes cache accesses by a cache accessing
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`device. The identification logic assigns request identification
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`request identification information to the cache accessing
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`device. The identification logic is capable of providing the
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`request identification information prior to the execution of
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`the cache accesses by the access control logic. The result
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`logic provides the request identification information and the
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`data requested by the cache accessing device to the cache
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`accessing device if the cache access was a read.
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`BRIEF DESCRIPTION OF THE DRAWINGS
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`The present invention may be better understood, and its
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`numerous objects, features, and advantages made apparent
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`to those skilled in the art by referencing the accompanying
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`drawings.
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`FIG. 1 shows a block diagram of a multimedia signal
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`processor in accordance with an embodiment of the inven-
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`tion.
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`FIG. 2 shows a block diagram of a cache system in
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`accordance with an embodiment of the invention.
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`FIG. 3 shows a block diagram of a data pipeline used in
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`a cache system in accordance with an embodiment of the
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`invention.
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`FIG. 4 shows a block diagram of a data pipeline used in
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`a cache system in accordance with an embodiment of the
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`invention.
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`FIG. 5 shows a block diagram of an address pipeline used
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`in a cache system in accordance with an embodiment of the
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`invention.
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`FIG. 6 shows a state diagram of a cache control unit and
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`processor interface in accordance with an embodiment of the
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`invention.
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`FIG. 7 shows a state diagram of a cache control unit and
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`bus interface in accordance with an embodiment of the
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`invention.
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`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 12 of 33 PageID# 10464
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 12 of 33 Page|D# 10464
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`5,860,158
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`3
`FIG. 8 shows a state diagram of a data receiver state
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`machine in accordance with an embodiment of the inven-
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`tion.
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`FIG. 9 shows a state diagram of a read/write state machine
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`in accordance with an embodiment of the invention.
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`The use of the same reference symbols in different draw-
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`ings indicates similar or identical items.
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`DESCRIPTION OF THE PREFERRED
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`EMBODIMENT(S)
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`The following sets forth a detailed description of the
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`preferred embodiments. The description is intended to be
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`illustrative of the invention and should not be taken to be
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`limiting. Many variations, modifications, additions and
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`improvements may fall within the scope of the invention as
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`defined in the claims that follow.
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`Referring to FIG. 1, processor 100 includes a general
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`purpose processor 110 coupled to a vector processor 120.
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`General purpose processor 110 and vector processor 120 are
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`coupled via control bus 112 and interrupt line 114. General
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`purpose processor 110 and vector processor 120 are coupled
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`to cache system 130 via bus 116 and bus 118, respectively.
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`Cache system is coupled to input/output bus (IOBUS) 180
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`and fast bus (FBUS) 190. IOBUS 180 is coupled to system
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`timer 182, universal asynchronous receiver-transmitter
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`(UART) 184, bitstream processor 186 and interrupt control-
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`ler 188. FBUS 190 is coupled to device interface 192, direct
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`memory access (DMA) controller 194, local bus interface
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`196 and memory controller 198.
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`General purpose processor 110 and vector processor 120
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`execute separate program threads in parallel. General pur-
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`pose processor 110 typically executes instructions which
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`manipulate scalar data. Vector processor 120 typically
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`executes instructions having vector operands, i.e., operands
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`each containing multiple data elements of the same type. In
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`some embodiments, general purpose processor 110 has a
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`limited vector processing capability. However, applications
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`that require multiple computations on large arrays of data are
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`not suited for scalar processing or even limited vector
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`processing. For example, multimedia applications such as
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`audio and video data compression and decompression
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`require many repetitive calculations on pixel arrays and
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`strings of audio data. To perform real—time multimedia
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`operations, a general purpose processor which manipulates
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`scalar data (e.g. one pixel value or sound amplitude per
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`operand) or only small vectors must operate at a high clock
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`frequency. In contrast, a vector processor executes instruc-
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`tions where each operand is a vector containing multiple
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`data elements (e.g. multiple pixel values or sound
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`amplitudes). Therefore, vector processor 120 can perform
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`real-time multimedia operations at a fraction of the clock
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`frequency required for general purpose processor 110 to
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`perform the same function. Thus, by allowing an efficient
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`division of the tasks required for, e.g., multimedia
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`applications, the combination of general purpose processor
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`110 and vector processor 120 provides high performance per
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`cost. Although in the preferred embodiment, processor 100
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`is for multimedia applications, processor 100 may be any
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`type of processor.
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`In one embodiment, general purpose processor 110
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`executes a real-time operating system designed for a media
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`circuit board communicating with a host computer system.
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`The real—time operating system communicates with a pri—
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`mary processor of the host computer system, services input/
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`output (I/O) devices on or coupled to the media circuit
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`board, and selects tasks which vector processor 120
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`4
`executes.
`In that embodiment, vector processor 120 is
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`designed to perform computationally intensive tasks requir-
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`ing the manipulation of large data blocks, while general
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`purpose processor 110 acts as the master processor to vector
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`processor 120.
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`In the exemplary embodiment, general purpose processor
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`110 is a 32-bit RISC processor which operates at 40 Mhz and
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`conforms to the standard ARM7 instruction set. The archi-
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`tecture for an ARM7 reduced instruction set computer
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`(RISC) processor and the ARM7 instruction set is described
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`in the ARM7DM Data Sheet available from Advanced RISC
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`Machines Ltd. General purpose processor 110 also imple-
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`ments an extension of the ARM7 instructions set which
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`includes instructions for an interface with vector processor
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`120. The extension to the ARM7 instruction set for the
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`exemplary embodiment of the invention is described in
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`copending, U.S. patent application Ser. No. 08/699,295,
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`attorney docket No. M-4366 U.S., filed on Aug. 19, 1996,
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`entitled “System and Method for Handling Software Inter-
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`rupts with Argument Passing,” naming Seungyoon Peter
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`Song, Moataz A. Mohamed, Heon-Chul Park and Le
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`Nguyen as inventors, which is incorporated herein by ref-
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`erence in its entirety. General purpose processor 110 is
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`coupled to vector processor 120 by control bus 112 to carry
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`out the extension of the ARM7 instruction set. Furthermore,
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`interrupt line 114 is used by vector processor 120 to request
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`an interrupt on general purpose processor 110.
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`In the exemplary embodiment, vector processor 120 has
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`a single-instruction-multiple-data (SIMD) architecture and
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`manipulates both scalar and vector quantities. In the exem-
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`plary embodiment, vector processor 120 consists of a pipe-
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`lined reduced instruction set computer (RISC) central pro-
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`cessing unit (CPU) that operates at 80 Mhz and has a 288-bit
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`vector register file. Each vector register in the vector register
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`file can contain up to 32 data elements. Avector register can
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`hold thirty—two 8—bit or 9—bit integer data elements, sixteen
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`16-bit
`integer data elements, or eight 32-bit
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`floating point elements. Additionally,
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`embodiment can also operate on a 576—bit vector operand
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`spanning two vector registers.
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`The instruction set for vector processor 120 includes
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`instructions for manipulating vectors and for manipulating
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`scalars. The instruction set for the exemplary embodiment of
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`the invention and an architecture for implementing the
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`instruction set
`is described in the pending U.S. patent
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`application Ser. No. 08/699,597, attorney docket No.
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`M—4355 U.S., filed on Aug. 19, 1996, entitled “Single—
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`Instruction-Multiple-Data Processing in a Multimedia Sig-
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`nal Processor,” naming Le Trong Nguyen as inventor, which
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`is incorporated herein by reference in its entirety.
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`General purpose processor 110 performs general tasks and
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`executes a real—time operating system which controls com—
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`munications with device drivers. Vector processor 120 per-
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`forms vector tasks. General purpose processor 110 and
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`vector processor 120 may be scalar or superscalar proces—
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`sors. The multiprocessor operation of the exemplary
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`embodiment of the invention is more fully described in
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`pending U.S. patent application Ser. No. 08/697,102, attor-
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`ney docket No. M-4354 U.S., filed on Aug. 19, 1996,
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`entitled “Multiprocessor Operation in a Multimedia Signal
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`Processor,” naming Le Trong Nguyen as inventor, which is
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`incorporated herein by reference in its entirety.
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`Referring again to FIG. 1, cache system 130 contains a
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`fast random access memory (RAM) block (shown graphi-
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`cally as blocks 140 and 170), read only memory (ROM) 150
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`and a cache control unit 160. Cache system 130 can con-
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`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 13 of 33 PageID# 10465
`Case 3:14-cv-00757-REP-DJN Document 81-1 Filed 04/10/15 Page 13 of 33 Page|D# 10465
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`figure the RAM block into (i) an instruction cache 142 and
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`a data cache 144 for general purpose processor 110, and (ii)
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`an instruction cache 172 and data cache 174 for vector
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`processor 120. In the preferred embodiment, RAM block
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`140, 170 includes static RAM (SRAM).
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`In an embodiment of a computer system according to the
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`invention, general purpose processor 110 and vector proces-
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`sor 120 share a variety of on-chip and off-chip resources
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`which are accessible through a single address space. Cache
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`system 130 couples a memory to any of several memory
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`mapped devices such as bitstream processor 186, UART
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`184, DMA controller 194, local bus interface 196, and a
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`coder-decoder (CODEC) device interfaced through device
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`interface 192. Cache system 130 can use a transaction-
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`oriented protocol to implement a switchboard for data access
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`among the processors and memory mapped resources. For
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`example, the transaction-oriented protocol provides that if
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`completion of an initial cache transaction is delayed (e.g.,
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`due to a cache miss), other cache access transactions may
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`proceed prior to completion of the initial transaction. Thus,
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`“step-aside-and-wait” capability is provided in this embodi-
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`ment of a cache management system according to the
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`invention. A similar transaction-oriented protocol is further
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`described in pending, US. patent application Ser. No.
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`08/731,393, attorney docket No. M-4398 U.S., filed on Oct.
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`18, 1996, entitled “Shared Bus System with Transaction and
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`Destination ID,” naming Amjad Z. Qureshi and Le Trong
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`Nguyen as inventors, which is incorporated herein by ref—
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`erence in its entirety.
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`Cache system 130 couples general purpose processor 110
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`and vector processor 120 to two system busses: IOBUS 180
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`and FBUS 190. IOBUS 180 typically operates at a slower
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`frequency than FBUS 190. Slower speed devices are
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`coupled to IOBUS 180, while higher speed devices are
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`coupled to FBUS 190. By separating the slower speed
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`devices from the higher speed devices, the slower speed
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`devices are prevented from unduly impacting the perfor-
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`mance of the higher speed devices.
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`Cache system 130 also serves as a switchboard for
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`communication between IOBUS 180, FBUS 190, general
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`purpose processor 110, and vector processor 120. In most
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`embodiments of cache system 130, multiple simultaneous
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`accesses between the busses and processors are possible. For
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`example, vector processor 120 is able to communicate with
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`FBUS 190 at the same time that general purpose processor
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`110 is communicating with IOBUS 180. In one embodiment
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`of the invention, the combination of the switchboard and
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`caching function is accomplished by using direct mapping
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`techniques for FBUS 190 and IOBUS 180. Specifically, the
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`devices on FBUS 190 and IOBUS 180 can be accessed by
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`general purpose processor 110 and vector processor 120 by
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`standard memory reads and write at appropriate addresses.
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`FBUS 190 provides an interface to the main memory. The
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`interface unit to the memory is composed of a four-entry
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`address queue and a one—entry write—back latch. The inter—
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`face can support one pending refill (read) request from
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`general purpose processor instruction cache 142, one pend-
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`ing refill (read) request from vector processor instruction
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`cache 172, one write request from vector processor data
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`cache 174, and one write-back request from vector processor
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`data cache due to a dirty cache line.
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`FBUS 190 is coupled to various high speed devices such
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`as a memory controller 198 and a DMA controller 194, a
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`local bus interface 196, and a device interface 192. Memory
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`controller 198 and DMA controller 194 provide memory
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`interfaces. Local bus interface 196 provides an interface to
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`10
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`20
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`30
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`40
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`60
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`6
`a local bus coupled to a processor. Device interface 192
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`provides interfaces to various digital-to-analog and analog-
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`to—digital converters (DACs and ACDs, respectively) that
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`may be coupled to processor 100 for Video, audio or
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`communications applications.
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`Memory controller 198 provides an interface for a local
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`memory if a local memory is provided for processor 100.
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`Memory controller 198 controls reads and writes to the local
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`memory. In the exemplary embodiment, memory controller
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`198 is coupled to and controls one bank of synchronous
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`dynamic RAMs (two 1M><16 SDRAM chips) configured to
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`use 24 to 26 address bits and 32 data bits and having the
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`features of: (i) a “CAS-before-RAS” refresh protocol, per-
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`formed at a programmable refresh rate, (ii) partial writes that
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`initiate Read-Modify-Write operations, and (iii) internal
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`bank interleave. Memory controller 198 also provides a 1:1
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`frequency match between the local memory and FBUS 190,
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`manual “both bank precharge”, and address and data queu-
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`ing to better utilize FBUS 190. Synchronous DRAM are
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`known to effectively operate at such frequencies (80 MHZ),
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`and standard fast page DRAMs and extended data out
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`(EDO) DRAMs could also be used. DRAM controllers with
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`capabilities similar to memory controller 198 in the exem-
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`plary embodiment are known in the art.
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`DMA controller 194 controls direct memory accesses
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`between the main memory of a host computer and the local
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`memory of processor 100. Such DMA controllers are well
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`known in the art. In some embodiments of the invention, a
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`memory data mover is included. The memory data mover
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`performs DMA from one block of memory to another block
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`of memory.
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`Local bus interface 196 implements the required protocol
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`for communications with a host computer via a local bus. In
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`the exemplary embodiment, local bus interface 196 provides
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`an interface to a 33-MHZ, 32-bit PCI bus. Such interfaces are
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`well known in the art.
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`Device interface 192 provides a hardware interface for
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`devices such as audio, Video and communications DACs and
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`ADCs which would typically be on a printed circuit board
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`with a