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`Case 3:14-cv-OO757-REP-DJN Document 1-7 Filed 11/04/14 Page 1 of 28 Page|D# 139
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`EXHIBIT E
`EXHIBIT E
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 2 of 28 PageID# 140
`Ill III II III III II11 III II11II 111
`
`US008252675B2
`
`(12) United States Patent
`Lee et al.
`
`(io) Patent No.:
`(45) Date of Patent:
`
`US 8,252,675 B2
`Aug. 28,2012
`
`(54) METHODS OF FORMING CMOS
`TRANSISTORS WITH HIGH CONDUCTIVITY
`GATE ELECTRODES
`
`(75)
`
`inventors: Jongwon Lee, Hwaseong-si (KR); Boun
`Yoon, Seoul (KR); Sang Yeob Han,
`Anyang-si (KR); Chae Lyoung Kim,
`Hwaseong-si (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd. (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl.No.: 12/942,763
`
`(22)
`
`Filed:
`
`Nov. 9, 2010
`
`(65)
`
`(30)
`
`Prior Publication Data
`
`US 2011/0136313 Al
`
`Jun. 9,2011
`
`Foreign Application Priority Data
`
`Dec. 8, 2009
`
`(KR)
`
`10-2009-0121108
`
`(51)
`
`IntCI.
`H01L 21/336
`(2006.01)
`H01L 21/44
`(2006.01)
`H01L 21/88
`(2006.01)
`H01L 21/4763
`(2006.01)
`438/592; 438/299; 438/637; 438/926;
`(52) U.S.CI
`438/183; 257/E21.177; 257/E21.621; 257/E21.626;
`257/E21.64
`438/296
`(58) Field of Classification Search
`See application file for complete search history.
`
`(56)
`
`References Cited
`
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`Joseph M,
`Steigerwald,
`Enabling Technology," 2008 IEEE, pp. 37-40.
`
`PrimaryExaminer — Fernando L Toledo
`Assistant Examiner — Valerie N Brown
`(74) Attorney, Agent, or Firm— Myers Bigel Sibley &
`Sajovec, P.A.
`
`ABSTRACT
`
`(57)
`Provided is a method for manufacturing a MOS transistor.
`The method comprises providing a substrate having a first
`active region and a second active region; forming a dummy
`gate stack on the first active region and the second active
`region, the dummy gate stack comprising a gate dielectric
`layer and a dummy gate electrode; forming source/drain
`regions in the first active region and the second active region
`disposed at both sides of the dummy gate stack; forming a
`mold insulating layer on the source/drain region; removing
`the dummy gate electrode on the first active region to form a
`first trench on the mold insulating layer, forming a first metal
`pattern to form a second trench at a lower portion ofthe first
`trench, and removing the dummy gate electrode on the second
`active region to from a third trench on the mold insulating
`layer; and forming a second metal layer in the second trench
`and the third trench to form a first gate electrode on the first
`activeregionand a second gate electrode on the secondactive
`region.
`
`15 Claims, 19 Drawing Sheets
`
`

`

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`U.S. PATENT DOCUMENTS
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`6,939,815 B2
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`7,037,845 B2
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`7,060,568 B2
`7,064,066 Bl
`7,074,680 B2
`7,078,282 B2
`7,084,038 B2
`7,087,476 B2
`7,122,870 B2
`7,125,762 B2
`7,126,199 B2
`7,129,182 B2
`7,138,323 B2
`7,144,783 B2
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`438/637
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 4 of 28 PageID# 142
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`U.S. Patent
`
`Aug. 28,2012
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`Sheet 1of19
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`US 8,252,675 B2
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`Fig. 1
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`16
`
`14
`
`Fig. 2
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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 5 of 28 PageID# 143
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`U.S. Patent
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`Aug. 28,2012
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`Sheet 2of19
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`US 8,252,675 B2
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`Fig. 3
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`16
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`Fig. 4
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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 6 of 28 PageID# 144
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`U.S. Patent
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`Aug. 28,2012
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`Sheet 3of19
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`US 8,252,675 B2
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`Fig. 5
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`Fig. 6
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`

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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 7 of 28 PageID# 145
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`Aug. 28,2012
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`Sheet 4of19
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`US 8,252,675 B2
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`Fig. 7
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`Fig. 8
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`30-
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`Aug. 28,2012
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`Sheet 5of19
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`US 8,252,675 B2
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`Fig. 9
`
`, 1 V^^Jr-ib >24
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`28
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`Fig. 10
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`16
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`

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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 9 of 28 PageID# 147
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`Aug. 28,2012
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`Sheet 6of 19
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`US 8,252,675 B2
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`Fig. 11
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`Fig. 12
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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 10 of 28 PageID# 148
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`Sheet 7of19
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`Fig. 13
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`22
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`38
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`Fig. 14
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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 11 of 28 PageID# 149
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`Fig. 15
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`Fig. 18
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`14
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`Sheet 10 of 19
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`Fig. 19
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`wriJFffrtt>f'> 'ffp y j
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`Sheet 11 of19
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`Fig. 22
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`Fig. 24
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`Fig. 25
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`Fig. 28
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`Sheet 15 of 19
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`Fig. 29
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`Fig. 36
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`Fig. 37
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`US 8,252,675 B2
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`1
`METHODS OF FORMING CMOS
`TRANSISTORS WITH HIGH CONDUCTIVITY
`GATE ELECTRODES
`
`REFERENCE TO PRIORITY APPLICATION
`
`2
`layer using the dummy filler layer and the mold layer as an
`etching mask. This first metal layer may include titanium
`nitride.
`Still further embodiments ofthe invention include methods
`5 Qf forming CMOS transistors by forming first and second
`gate insulating layers on a substrate and forming first and
`second dummy gate electrodes on the first and second gate
`insulating layers, respectively. First and second electrically
`insulating spacers are formed on sidewalls of the first and
`second dummy gate electrodes, respectively. These first and
`second spacers and the first and second dummy gate elec-
`trodes are covered with an electrically insulating mold layer.
`^ m
`^
`ion ofthe mo]d layer .g removed ,Q
`uppersurfaceofme first dummy gate electrode and an upper
`si^faceoftheseconddunimygateelec^cxle.Thefirstdummy
`gate electrode is selectively removed from between the first
`spacers using a mask to prevent removal of the second
`dummy gate electrode. A first metal layer is deposited onto an
`AMOS transistor iswidely used asswitching devices. In 20 uppersurface ofthe mold layer andonto innersidewallsofthe
`contrast to conventional MOS transistors containing a gate
`first spacers. A space between theinnersidewalls of thefirst
`electrode which is formed of poly silicon, a metal material
`spacers is filled with a dummy filler layerthatcontacts the
`withsuperiorelectric conductivity betterthanthepolysilicon
`first metal layer. An upperportion of the first metal layeris
`havebeenusedas thegateelectrodeof MOStransistors.MOS
`removedfrombetweenthe innersidewallsofthe firstspacers
`transistors are classified as n-MOS transistors or p-MOS tran- 25 and the dummy filler layer. The dummy filler layer is removed
`sistorsin accordance with the channeltype which is induced
`frombetweentheinnersidewalls of thefirst spacersto expose
`beneath thegateelectrode. Thegateelectrodes of then-MOS
`thefirst metal layer. Thisstep is performed concurrently with
`transistor and thep-MOS transistor may beformed ofdiffer-
`removing the second dummy gate electrode from between
`mner sjdewaiis ofthesecond spacers. Asecond metal layer is
`ent metals sothat then-MOS transistor and thep-MOS tran-
`sistor have different threshold voltages.
`30 mendepos;tedonto aportion ofthe first metal layerextending
`between the inner sidewalls of the first spacers to thereby
`define a firstmetal gate electrode including a composite ofthe
`•
`rr
`c u «•.._• .
`.
`i . j
`-
`w,.j
`first and second metal layers. This step is performed concur-
`Methods of forming insulated-gate field effect transistors
`,
`. . .
`;
`.
`,,
`according to embodiments ofthe invention includes forming 35 J"** Wlth depos.tmg the second metal layer mto aspace
`between me inner Sldewalls ofthe ""^ *****t0 ^^
`agate insulating layer on asubstrate and forming adummy
`define asecond metaI 8ate electrode,
`gate electrode on the gate insulating layer. Electrically insu-
`noinn nccranrnma nx: the no Aunwrc
`lating spacers are formed on sidewalls of the dummy gate
`electrode. These spacers and the dummy gate electrode are
`BRIEF DESCRIPTION OF THE DRAWINGS
`covered with an electrically insulating mold layer. An upper 40
`The accompanying drawings are included to provide a
`portion ofthe mold layer isthen removed to expose an upper
`surface ofthedummy gate electrode. The dummy gate elec-
`further understanding oftheinventive concept, and are incor-
`trode isthen removed from between thespacers byselectively
`porated in and constitute a part of this specification. The
`etching back thedummy gateelectrode using themold layer
`drawings illustrate exemplary embodiments of theinventive
`and the spacers as an etching mask. A first metal layer is 45 conceptand, togetherwith the description, serve to explain
`deposited onto an upper surface of the mold layer and onto
`principlesofthe inventiveconcept. In the figures:
`inner sidewalls of the spacers. A space between the inner
`FIGS. 1 through 17 are cross-sectional views illustrating a
`sidewalls of the spacers is filled with a dummy filler layer
`methodfor manufacturing a MOS transistoraccording to a
`(e.g.,polysilicon) thatcontactsthe firstmetallayer. Anupper
`first embodiment of the inventive concept; and
`portion of the first metal layer is removedfrom between the 50
`FIGS. 18 through37 are cross-sectionalviews illustrating
`innersidewallsofthe spacersand the dummyfillerlayer.The
`a methodfor manufacturinga MOS transistoraccordingto a
`dummy filler layer is then removed from between the inner
`second embodiment ofthe inventiveconcept,
`sidewalls of the spacers to expose the first metal layer. A
`second metal layer is then deposited onto a portion ofthe first
`metal layer extending between the inner sidewalls of the 55
`spacers, to thereby define a metal gate electrode containing a
`Exemplary embodiments ofthe inventive concept will be
`composite ofthe first and second metal layers.
`described below in more detail with reference to the accom-
`According to some ofthese embodiments ofthe invention,
`panying drawings. The embodiments ofthe inventive concept
`the step of filling a space between the inner sidewalls of the
`spacers is followed by a step ofplanarizing the dummy filler 60 may, however, be embodied in different forms and should not
`layer to expose a portion ofthe first metal layer on the upper
`be construed as limited to the embodiments set forth herein,
`surface of the mold layer. In addition, the step of forming a
`Rather, these embodiments are provided so that this disclo-
`dummy gate electrode on the gate insulating layer may be
`sure will be thorough and complete, and will fully convey the
`preceded by forming a buffer gate electrode containing tita-
`scope of the inventive concept to those skilled in the art.
`nium nitride or tantalum nitride on the gate insulating layer. In 65
`Hereinafter, exemplary embodiments ofthe inventive con-
`addition, the step of removing an upper portion of the first
`cept will be described in detail with reference to the accom-
`metal layer may include selectively etching the first metal
`panying drawings.
`
`This application claims priority to Korean Patent Applica-
`tionNo. 10-2009-0121108, filedDec. 8,2009, the contents of
`whichare herebyincorporated hereinby reference.
`
`FIELD OF THE INVENTION
`_
`This invention relates to methods for manufacturing MOS
`transistors and, more particularly, to methods for manufac-
`Sm^a1stranS,St0re
`atC
`C°
`BACKGROUND OFTHE INVENTION
`
`SUMMARY
`
`DETAILED DESCRIPTION OF THE
`EMBODIMENTS
`
`

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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 24 of 28 PageID# 162
`
`US 8,252,675 B2
`
`FIGS. 1 through 17 are cross-sectional views illustrating a
`method for manufacturing a MOS transistor according to a
`first embodiment ofthe inventive concept.
`Referring to FIG. 1, a first well and a second well may be
`respectively formed in a first active region 14 and a second 5
`active region 16 which are defined by a device isolation layer
`12 on a substrate 10. The first well may be formed in an ion
`implantation process in which impurities ofa first conductiv
`ity type are injected in the substrate 10. The impurity ofthe
`first conductivity type may comprise a donor ion such as 10
`phosphorusor arsenic. For example, the impuritiesofthe first
`conductivity type may be injected at an energy of about 100
`KeV~300 KeV and a concentration of about
`lxlO13
`ea/cm3--lxl016 ea/cm3. The second well may be formedby
`an ion implantation process in which impurities of a second 15
`conductivity type opposite to the first conductivity type are
`injected in the substrate 10. The impurity ofthe second con
`ductivity type may comprise an acceptor ion such as boron.
`For example, the impurities ofthe second conductivity type
`may be injected at an energy ofabout 70 KeV~200 KeV and 20
`a concentration of about 1xl 013 ea/cm3~l x 1016 ea/cm3. The
`device isolation layer 12 may be formed after forming the first
`well and the second well. The device isolation layer 12 may
`comprise silicon oxide that is formed by a plasma enhanced
`chemical vapor deposition (PECVD). The silicon oxide is 25
`formed in a trench where a predetermined depth ofthe sub
`strate 10 is removed
`Referring to FIG. 2, a gate insulating layer 18, a buffer gate
`electrode 20 and a dummy gate electrode 22 may be stacked
`on the substrate 10. The gate insulating layer 18 may be 30
`formed of a high-k dielectric layer such as a hafnium oxide
`layer, a tantalum oxide layer and a silicon oxide layer. The
`gate insulating layer 18 may be formed to have thickness of
`about 30 A-200 A by a method such as chemical vapor
`deposition (CVD), atomic layer deposition (ALD) or rapid 35
`thermal process (RTP). The buffer gate electrode 20 may
`comprise a titanium nitride layer or a tantalum nitride layer.
`The buffergate electrode 20 may be formed to have thickness
`of about20 A-50 A by a method suchas CVDor ALD.The
`dummy gate electrode 22 may comprise poly silicon that is 40
`formed by a chemical vapor deposition.
`Referring to FIG. 3, a dummy gate stack 24 comprising the
`gate insulating layer 18, the buffer gate electrode 20 and the
`dummy gate electrode 22 may be formed on the first active
`region 14 and the second active region 16. The dummy gate 45
`stack 24 may be patterned using a photo lithography process
`and an etching process. The photo lithography and the etching
`process may be performed as follows. Initially, a first photo
`resist pattern (not shown) may be formed on the dummy gate
`electrode 22. The dummy gate electrode 22, the buffer gate 50
`electrode 20 and the gate insulating layer 18 may be succes
`sively etched using the first photo resist pattern as an etch
`mask.
`Referring to FIG. 4, a second photo resist pattern 25 may be
`formed to cover the second active region 16. A lightly doped 55
`drain (LDD) 26 is formed using the second photo resist pat
`tern 25 and the dummy gate electrode 22 as an ion implanta
`tion mask. The impurities of the second conductivity type
`may be injected into the first active region 14. The impurities
`ofthe second conductivity type may be injected at an energy 60
`ofabout 1 KeV ~20 KeV and a concentration ofabout lxlO13
`ea/cm3~lxl016 ea/cm3. Thesecond photoresistpattern 25is
`removed.
`Referring to FIG. 5, a third photo resist pattern 27 may be
`formed to cover the first active region 14. A LDD 26 may be 65
`formed in the second active region using the third photo resist
`pattern 27 and the dummy gate electrode 22 as an ion implan
`
`tation mask. Impurities ofthe first conductivity type may be
`injected into the second active region 16. The impurities ofthe
`first conductivity type may be injected at an energy ofabout
`5 KeV~30 KeV and a concentration of about
`lxlO13
`ea/cm3-lxl016ea/cm3. The LDDs 26 maybe formed ofthe
`same depth in the first active region 14 and the second active
`region 16, and diffused to the same distant below the dummy
`gate stack 24. The photo resist pattern 27 is removed.
`Referring to FIG. 6, a spacer 28 may be formed on a
`sidewall of the dummy gate stack 24. The spacer 28 may
`comprise a silicon nitride layerwhich is formed by a chemical
`vapor deposition process. The spacer 28 may be formed by a
`selfalignment method. For example, a silicon nitride layer is
`formed to cover the dummy gate stack 24, and the silicon
`nitride layer is then anisotropically etched to remain on the
`sidewall ofthe dummy gate stack 24.
`Referring to FIG. 7, a fourth photo resist pattern 29 may be
`formed to cover the second active region 16. A source/drain
`region 30 may be formed in the first active region using the
`fourth photo resist pattern 29, the dummy gate electrode 22
`and the spacer 28 as an ion implantation mask. The source/
`drain region 30 may comprise impurities ofthe second con
`ductivity type. The impurities ofthe second conductivity type
`may be injected at an energy ofabout 10 KeV~40 KeV and a
`concentration ofabout lxlO16 ea/cm3~lxl017 ea/cm3. The
`fourth photo resist pattern 29 on the second active region 16 is
`removed.
`Referring to FIG. 8, a fifth photo resist pattern 31 is formed
`to cover the first active region 14. A source/drain region 30
`may be formed in the second active region 16 using the fifth
`photo resist pattern 31, the dummy gate electrode 22 and the
`spacer 28 as an ion implantation mask. The source/drain
`region 30 in the second active region 16 may comprise impu
`rities ofthe first conductive type. For example, The impurities
`of the first conductivity type may be injected in the second
`active region 16 at an energy ofabout 10 KeV-50 KeV and a
`concentration ofabout lxlO16 ea/cm3~lxl017 ea/cm3. The
`source/drain regions 30 in the first active region 14 and the
`second active region may be the same depth. The photo resist
`pattern 31 may be then removed.
`Although not shown in drawings, the source/drain region
`30 may be formed by removing portions of the first active
`region 14 and the second active region 16 and filling an
`epitaxial silicon germanium with impurities of respective
`conductivity type in the removed portions ofthe first active
`region 14 and the second active region 16.
`Referring to FIG. 9, a mold insulating layer 32 is formed to
`cover the source/drain region 30 and the dummy gate stack
`24. The mold insulating layer 32 may comprise a silicon
`oxide layer. The mold insulating layer 32 may be formed in a
`low pressure chemical vapor deposition (LPCVD) process or
`plasma enhanced chemical vapor deposition (PECVD) pro
`cess. The mold insulating layer 32 may be planarized such
`that the dummy gate electrode 22 may be formed. The pe
`nalization ofthe mold insulating layer 32 may be performed
`by a method such as chemical mechanical polishing (CMP) or
`etch-back.
`Referring to FIG. 10, the dummy gate electrode 22 on the
`first active region 14 may be selectively removed to form a
`first trench 35. The removing ofthe dummy gate electrode 22
`may comprise forming a sixth photo resist pattern 34 to cover
`the second active region 16 while exposing the dummy gate
`electrode 22 on the first active region 14, and etching the
`dummy gate electrode 22 in a dry or wet etching process. The
`sixth photo resist pattern 34, the mold insulating layer 32 and
`the spacer 28 on the substrate 10 may be used as an etch mask
`while the dummy gate electrode 22 is removed. The buffer
`
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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 25 of 28 PageID# 163
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`US 8,252,675 B2
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`25
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`30
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`gate electrode 20 may be used as an etch stop layer during the
`dummy gate electrode 22 etching. The sixth photo resist
`pattern 34 formed on the second active region 16 is removed.
`Referring to FIG. 11, a first metal layer 36 may be formed
`on the entire surface ofthe substrate 10. The first metal layer 5
`36 may comprise a titanium nitride layer that is formed by a
`chemical vapor deposition (CVD) or an atomic layer deposi
`tion (ALD). The first metal layer 36 may be formed of the
`same thickness on the bottom surface and the sidewall ofthe
`mold insulating layer 32 as well as a top surface ofthe mold io
`insulating layer 32. If the first metal layer 36 is buried in the
`first trench 35, the first metal layer 36 in the first trench 35
`may comprise a void formed by overhang of the first metal
`layer 36. The void may be caused by losing conductive reli
`ability ofthe first metal layer 36. Therefore, the first metal 15
`layer 36 may be formed of uniform thickness on the bottom
`and the sidewall ofthe first trench 35.
`Referring to FIG. 12, a dummy filler layer 38 may be
`stacked on the first metal layer 36. The dummy filler layer 38
`may be formed of the same material as the dummy gate 20
`electrode 22. The dummy filler layer 38 may comprise poly
`silicon. The dummy filler 38 may be completely fill the first
`trench 35 on the first active region 14. The poly silicon may be
`formed by a chemical vapor deposition method. The dummy
`filler layer 38 may comprise a void in the first trench 35.
`Referring to FIG. 13, the dummy filler layer 38 may be
`planarized to expose the first metal layer 36. The planariza-
`tion of the dummy filler layer 38 may be performed by a
`chemical mechanical polishing (CMP) or an etch-back. The
`dummy filler layer 38 may remain in the first trench 35.
`Referring to FIG. 14, the first metal layer 36 on the mold
`insulating layer 32 is removed And, an upper portion of the
`first metal layer 36 disposed between the mold insulating
`layer32 and the dummy filler layer 38 becomes recessed. The
`removing process ofthe firstmetal layer 36 may be performed 35
`in a dry or wet etching method in which etching selectivity to
`the first metal layer 36 is two or more times greater than to the
`dummy filler layer 38 and the mold insulating layer 32. The
`first metal layer 36 may remain on the bottom surface and a
`lower sidewall ofthe first trench 35. The first metal layer 36 40
`may be formed symmetrically on both sidewall of the first
`trench 35. Therefore, the first metal layer 36 may be remained
`in the first trench 35 to form a first metal pattern with a 'U'
`shaped section.
`Referring to FIG. 15, the dummy filler layer 38 on the first 45
`active region 14 and the dummy gate electrode 22 on the
`second active region 15 may be removed to form a second
`trench 40 on the first active region 14 and a third trench 43 on
`the second active region. The dummy gate electrode 22 and
`the dummy filler layer 38 may be removed simultaneously in 50
`an etching process because the dummy gate electrode 22 and
`the dummy filler layer38 are formed ofpoly silicon. Thus, the
`method for manufacturing a MOS transistor according to first
`embodiment can improve or maximize the productivity.
`The first metal layer 36 may be exposed in the second 55
`trench 40 on the first active region 14, and the buffer gate
`electrode 20 may be exposed in the third trench 43 on the
`second active region 16. The second trench 40 may be shal
`lower than the third trench 43. The first metal layer 36 may be
`disposed on the bottom surface and the lower sidewall ofthe 60
`second trench 40. The second trench 40 and the third trench
`43 may be different from each other in thickness.
`Referring to FIG. 16, a second metal layer 42 may be
`formed on the entire surface ofthe substrate 10. The second
`metal layer 42 may fill the second trench 40 and the third 65
`trench 43. The second metal layer 42 may comprise at least
`one of aluminum, tungsten, titanium and tantalum that is
`
`formed by a method such as PVD or CVD. The second metal
`layer 42 may be formed without a void in the second trench 40
`on the first active region 14.
`Referring to FIG. 17, the second metal layer 42 is pla
`narized to expose the mold insulating layer 32. A first gate
`electrode 46 and a second gate electrode 48 may be formed on
`the first active region 14 and the second active region, respec
`tively. The first gate electrode 46 and the second gate elec
`trode 48 may be extended in a vertical direction to the direc
`tion ofthe source/drain regions 30 arrangement. The second
`metal layer 42 may be planarized by a method such as CMP
`or etch-back. The second metal layer 42 may be planarized to
`separate the first gate electrode 46 and the second gate elec
`trode 48. The first gate electrode 46 and the second gate
`electrode 48 may be formed to have top surfaces ofsubstan
`tially equal level. The first gateelectrode 46 may comprisethe
`buffer gate electrode 20, the first metal
`layer 36 and the
`second metal layer 42. The first gate electrode 46 may com
`pose a p-MOS transistor on the first active region 14. The
`second gate electrode 48 may comprise the buffer gale elec
`trode 20 and the second metal layer 42. The second gate
`electrode 48 may compose an n-MOS transistor on the second
`active region 16.
`In general, the operating voltage ofthe n-MOS transistor
`and the p-MOS transistor may be different from each other.
`Current of the n-MOS transistor may be adjusted in accor
`dance with a switching voltage. Thus, the second gate elec
`trode 48 may comprise less than two metal layers in order to
`simplify the estimation of an electric resistance or a work
`function according to combination of the metal layers. The
`p-MOS transistor may be different from the n-MOS transistor
`in operating voltage. The first gate electrode 46 may comprise
`at least two metal layers because the p-MOS transistor per
`forms a simple switching operation. For example, the oper
`ating voltage may be lowerto the p-MOS transistorthan to the
`n-MOS transistor. If a void is formed in the first gate electrode
`46, operation characteristic ofthe p-MOS transistor may be
`deteriorated. According to the first embodiment, the first gate
`electrode 46 does not have a void to thereby prevent the
`operation characteristic of the p-MOS transistor from dete
`rioration.
`Not shown in drawings, the mold insulating layer 32 on the
`source/drain region 30 may be removed to form a contact
`hole, and a source/drain electrode may be formed in the
`contact hole.
`FIGS. 18 through 37 are cross-sectional views illustrating
`a method for manufacturing a MOS transistor according to a
`second embodiment of the inventive concept. Referring to
`FIG. 18, a first well and a second well may be formed in a first
`active region 14 and a second active region 16 that are defined
`by a device isolation layer 12 on a substrate 10. The first well
`may be formed by injecting impurities ofa first conductivity
`type. The impurities ofthe first conductivity type may com
`prise donor ions such as phosphorus or arsenic ions. The
`impurities ofthe first conductivity type may be injected in the
`first well at an energy of about 100 KeV-300 KeV and a
`concentration ofabout lxlO13 ea/cm3-lxl016 ea/cm3. The
`second well may be formed by injecting impurities ofa sec
`ond conductivity type opposite to the first conductivity type.
`The impurities of the second conductivity type may be
`injected in the second well at an energy ofabout 70 KeV~200
`KeV and a concentration ofabout lxlO13 ea/cm3~lxl016
`ea/cm3. The device isolation layer 12 may be formed after
`forming the first and the second wells. The device isolation
`layer 12 may comprise a silicon oxide layer that is formed in
`a trench by a PECVD method. The substrate may be removed
`at a predetermined depth to form the trench.
`
`

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`Case 3:14-cv-00757-REP-DJN Document 1-7 Filed 11/04/14 Page 26 of 28 PageID# 164
`
`US 8,252,675 B2
`
`Referring to FIG. 19, a gate insulating layer 18, a buffer
`gate electrode 20 and a dummy gate electrode 22 may be
`stacked on the substrate 10. The gate insulating layer 18 may
`comprise at least one of hafnium oxide, tantalum oxide, sili
`con oxide and other high-k dielectric layer. The gate insulat
`inglayer18maybeformed tohavea depthofabout30A~200
`A by a method suchas CVD,ALD or RTP. The buffergate
`electrode 20 may comprise a titanium nitride layer or a tan
`talum nitride layer. The buffer gate electrode 20 may be
`formed tohavea depthofabout20A-50 A.Thedummy gate
`electrode 22 may comprise poly silicon that is formed by
`CVD.
`Referring to FIG.