Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 1 of 24 PageID# 115
`Case 3:14-cv-OO757-REP-DJN Document 1-6 Filed 11/04/14 Page 1 of 24 Page|D# 115,
`
`EXHIBIT D
`EXHIBIT D
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 2 of 24 PageID# 116
`(cid:127)(cid:127)(cid:127)llinilHHH
`
`US006819602B2
`
`(12) United States Patent
`Seo et al.
`
`(io) Patent No.:
`(45) Date of Patent:
`
`US 6,819,602 B2
`Nov. 16,2004
`
`(54) MULTIMODE DATA BUFFER AND METHOD
`FOR CONTROLLING PROPAGATION
`DELAY TIME
`
`(75)
`
`Inventors: Seong-young Seo, Suwon (KR);
`Jung-bae Lee, Yongin (KR); Byong-mo
`Moon, Seoul (KR)
`
`(73) Assignee: Samsung Electronics Co., Ltd.,
`Kyungki-Do (KR)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 77 days.
`
`5/2002 Ooishi
`6,396,768 B2 •
`7/2002 Kim et al.
`6,414,517 Bl
`7/2002 Taruishi et al
`6,424,590 Bl *
`9/2002 Iwamoto
`6,452,849 Bl *
`1/2003 Wu et al
`6,512,704 Bl ♦
`2003/0090294 Al * 5/2003 Chang
`
`365/233
`
`365/230.08
`365/201
`365/189.07
`326/93
`
`FOREIGN PATENT DOCUMENTS
`
`EP
`
`KR
`
`0322915 A3
`
`2002046826
`
`7/1989
`6/2002
`
`* cited by examiner
`
`(21) Appl. No.: 10/278,071
`
`(22) Filed:
`
`Oct. 23, 2002
`
`(65)
`
`Prior Publication Data
`
`US 2003/0210575 Al Nov. 13, 2003
`
`Related VS. Application Data
`(60) Provisional application No. 60/379,665, filed on May 10,
`2002
`Int. CI.7
`(51)
`(52) U.S. CI
`
`G11C 7/00
`365/193; 365/189.05; 365/191;
`365/194
`365/189.05, 191,
`365/193, 194
`
`(58) Field of Search
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`PrimaryExaminer—Van Thu Nguyen
`(74) Attorney, Agent, or Firm—Harness, Dickey & Pierce,
`P.L.C.
`
`(57)
`
`ABSTRACT
`
`A data buffer, such as a data strobe input buffer or a data
`input buffer, which may operate in multiple modes, such as
`a single mode (SM) and a dual mode (DM) and where the
`mode is selected by providing a signal, such as an external
`signal such as an address signal or an external command
`signal. A data buffer which can be used for a SM/DM
`dual-use and can improve a data setup/hold margin. A
`semiconductor memory device including one or more of the
`data buffers described above. A method for controlling
`propagation delay times which can improve a data setup/
`hold margin in a SM/DM dual-use data buffer.
`
`6,279,073 Bl *
`
`8/2001 McCracken et al
`
`711/105
`
`29 Claims, 13 Drawing Sheets
`
`21
`
`213
`_1_
`
`DIFFERENTIAL
`AMPLIFIER
`
`DO
`
`DQSO
`
`DQSBO
`
`CNTB/CNT
`
`CNT/CNTB,_
`
`VREFO
`
`^211
`
`13
`
`/
`
`~i
`
`23
`
`^
`
`CNT/CNTB
`
`k 232
`
`7T
`N2
`
`-DS
`
`231CNTB/CNT
`J
`' 233
`DELAY ^
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 3 of 24 PageID# 117
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 1 of 13
`
`US 6,819,602 B2
`
`FIG. 1
`
`Prior Art
`
`i
`
`i
`
`t
`
`i
`
`FIG. 2
`
`21
`
`13
`
`/
`
`213
`
`uC
`
`DIFFERENTIAL
`AMPLIFIER
`
`DO
`
`DQSO
`
`DQSBO-
`
`VREFO
`
`CNT8/CNT
`
`CNT/CNTB
`
`^211
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 4 of 24 PageID# 118
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 2 of 13
`
`US 6,819,602 B2
`
`DQSB
`
`CNTB
`
`VREF
`
`FIG. 3A
`
`212
`
`V
`
`"
`
`£
`
`t t
`
`N.
`-7-"211
`
`FIG. 3B
`
`—
`
`CNT
`
`CNT
`
`o
`
`— CNTB
`
`FIG. 4
`
`CNT/CNTB
`
`15
`
`jL
`
`MODE
`REGISTER SET
`
`COMMAND
`
`ADD
`
`(cid:141)
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 5 of 24 PageID# 119
`
`U.S. Patent
`
`Nov. 16, 2004
`
`Sheet 3 of13
`
`US 6,819,602 B2
`
`251
`
`/
`
`712
`
`714
`
`£>°
`
`CNT
`
`FIG. 5A
`
`VDD
`
`VDD
`
`<| [_ P3
`
`P4l t>
`
`,i
`
`—+
`
`®- 710
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`N6
`
`FIG. 5B
`
`VCCH>-
`
`VOLTAGE LEVEL
`
`POWER
`
`VCCH
`
`,
`
`T1
`
`T2
`
`— TIME
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 6 of 24 PageID# 120
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 4of 13
`
`US 6,819,602 B2
`
`FIG.
`
`6
`
`VOD
`
`1410a—U 142O0 1440a
`
`J>o
`
`-CNT
`
`1430a
`
`FIG. 7
`
`DQSO
`
`DQSBO
`
`VREFO
`
`21
`
`213
`
`CNTB/CNT
`
`212
`
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB,^
`
`4*1^211
`
`i
`
`r*
`
`DO
`
`.J
`
`L.
`
`13
`
`/
`
`23
`
`CNT/CNTB
`
`4f232
`
`-7T
`N2
`
`DS
`
`231CNTB/CNT
`
`DELAY
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 7 of 24 PageID# 121
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 5 of 13
`
`US 6,819,602 B2
`
`FIG. 8
`
`DO
`
`in-.232
`i /
`
`CNT
`
`DEUY
`
`231
`
`.
`
`£
`
`DS
`
`*v
`
`233
`
`I —CNTB
`
`FIG.
`
`9
`
`X
`
`/
`
`/
`
`/
`
`/
`
`\
`
`X
`
`—
`
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`
`\
`
`\
`
`\
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`)
`(
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`VI
`
`X
`V /
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`x
`A (!
`!
`I'
`\!/—'—
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`i
`!\ i
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`i i
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`DQ
`
`DOS
`
`DIN
`
`SM mode
`
`-DS
`
`DM mode
`
`-DS
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 8 of 24 PageID# 122
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 6of 13
`
`US 6,819,602 B2
`
`FIG. 10
`
`CNTB/CNT
`
`^2 J
`
`CNT/CNTB
`
`21
`
`./I
`
`213
`
`JL
`
`DIFFERENTIAL
`AMPLIFIER
`
`13
`
`/
`
`DO
`
`DQSO
`
`2^
`
`DOSB O
`
`'dummy I
`T
`
`vss
`
`VREF O
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`211
`
`FIG. 11
`
`DQSO
`
`VREFO
`
`<
`
`DQSBE>
`
`31
`
`^-
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`32
`
`JL
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`
`13a
`
`/
`
`CNTB/CNT
`
`•
`
`- DS
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 9 of 24 PageID# 123
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 7 of 13
`
`US 6,819,602 B2
`
`FIG. 12
`
`DOS O
`
`VREFD
`
`i
`
`31
`
`/
`
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`
`-4^
`
`32
`
`JL
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`CNTB/CNT
`
`-4^
`
`DQSBO
`
`13o
`
`/
`
`DS
`
`DELAY —231
`
`FIG. 13
`
`31
`
`-z:
`
`CNT/CNTB
`
`13a
`
`/
`
`DQSO
`
`VREFD
`
`i
`
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNTB/CNT
`
`— DS
`
`32
`
`^L
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`C dummy
`
`i v
`
`ss
`
`DQSBO
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 10 of 24 PageID# 124
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 8of 13
`
`US 6,819,602 B2
`
`FIG. 14
`
`21
`
`jC
`
`213
`
`^L
`
`DIFFERENTIAL
`AMPLIFIER
`
`11
`
`/
`
`DO
`
`DQO
`
`DQBO
`
`VREFO
`
`CNTB/CNT
`
`CNT/CNTB
`
`-A-^21
`
`FIG. 15
`
`DQO
`
`DQBO
`
`VREFO
`
`21
`
`jl
`
`213
`
`CNTB/CNT
`
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB,^
`
`-4211
`
`i
`
`r-
`
`DO
`
`.J
`
`L.
`
`11
`
`/
`
`23
`
`CNT/CNTB
`
`232k 7T
`
`N2
`
`— DIN
`
`231CNTB/CNT
`
`DELAYYk 233
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 11 of 24 PageID# 125
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 9 of13
`
`US 6,819,602 B2
`
`21
`
`.jC
`
`213
`
`.z:
`
`DIFFERENTIAL
`AMPLIFIER
`
`11
`
`/
`
`DO
`
`FIG. 16
`
`DQO-
`
`DOBO
`
`VREF E>
`
`CNTB/CNT
`212
`
`T-H^
`
`CNT/CNTB
`
`4t211
`
`rT
`
`'dummy
`
`VSS
`
`FIG. 17
`
`DQO
`
`VREF CD
`
`k
`
`31
`
`JL
`
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`
`-4£
`
`32
`
`X
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`CNTB/CNT
`
`-4^
`
`D08O
`
`11a
`
`/
`
`— DIN
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 12 of 24 PageID# 126
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 10 of 13
`
`US 6,819,602 B2
`
`FIG. 18
`
`31
`
`X
`
`CNT/CNTB
`
`DQO
`
`VREFD
`
`*
`
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`33
`
`32
`
`/
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`CNTB/CNT
`
`-4-
`
`DQBO
`
`11a
`
`/
`
`— DIN
`
`DELAY — 231
`
`FIG. 19
`
`DQD
`
`VREFD
`
`4
`
`31
`
`JL
`1st
`DIFFERENTIAL
`AMPLIFIER
`
`CNT/CNTB
`
`-4^-
`
`11a
`
`/
`
`CNTB/CNT
`
`— DIN
`
`32
`
`jL
`
`2nd
`DIFFERENTIAL
`AMPLIFIER
`
`DQBO
`
`C dummy
`
`VSS
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 13 of 24 PageID# 127
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 11 of 13
`
`US 6,819,602 B2
`
`FIG. 20
`
`-!
`
`DINE
`
`-DINO
`
`DQO
`
`DATA
`INPUT BUFFER
`
`DQSO
`
`DQSBO
`
`VREFO
`
`DATA
`STROBE SIGNAL
`INPUT BUFFER
`
`CNT/CNTB
`
`15
`
`j^L
`
`MODE
`REGISTER SET
`
`6
`COMMAND
`
`6
`ADD
`
`FIG. 21
`
`COMMAND
`
`©
`
`d>
`
`DOS
`
`DQ
`
`Q0XQ1XQ2XQ3
`
`tt)0XD1XD2XD3
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 14 of 24 PageID# 128
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 12 of 13
`
`US 6,819,602 B2
`
`17
`
`17a
`
`/ /
`
`FIG. 22
`
`DINO
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`
`KH
`
`U<3J
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 15 of 24 PageID# 129
`
`U.S. Patent
`
`Nov. 16,2004
`
`Sheet 13 of 13
`
`US 6,819,602 B2
`
`FIG. 23
`
`DQO
`DQBO
`
`^1
`
`DATA
`INPUT BUFFER
`
`DQSO-<
`dqsbo-h;
`
`VREFO
`
`^L
`
`DATA
`STROBE SIGNAL
`INPUT BUFFER
`
`CNT
`
`15
`
`jL
`
`MODE
`REGISTER SET
`
`A
`COMMAND
`
`0
`ADD
`
`-DINE
`
`-DINO
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 16 of 24 PageID# 130
`
`US 6,819,602 B2
`
`MULTIMODE DATA BUFFER AND METHOD
`FOR CONTROLLING PROPAGATION
`DELAY TIME
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`This U.S. nonprovisional application claims priority
`under 35 U.S.C. § 119 to U.S. Provisional Patent Applica
`tion No. 60/379,665 filed May 10, 2002, the entire contents
`of which are incorporated by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a semiconductor memory
`device, and more particularly, to a multimode data buffer and
`a method for controlling propagation time delay.
`2. Description of the Related Art
`To improve system performances, innovations in the
`design of semiconductor memory devices in general, and the
`design of dynamic random access memories (DRAMs) in
`particular,continueto focus on higher integrationand higher
`speed operation. That is, DRAMs capable of processing
`more data at higher speed are desired. For higher speed
`operations, DRAMs synchronized with a system clock have
`been developed. This synchronous feature of DRAMs has
`increased data transmission speeds.
`However, since a data input/output operation in a syn
`chronous DRAM should be performed in a cycle of a system
`clock, there is a limit to increasing the bandwidth between
`the synchronousDRAM and a DRAMcontroller,that is, the
`amount of data which is input/output from a memory device
`in a unit time is limited. In order to increase data transmis
`sion speed, dual data rate (DDR) synchronous DRAMs in
`which data is input/output synchronized both with the rising
`edge and falling edge of a clock have been developed.
`In general, a DDR synchronous DRAM uses a data strobe
`signal when the DRAM receives data from a memory
`controller or sends data to the memory controller. For
`example, in a data receiving operation, the DDR synchro
`nous DRAM receives data with a data strobe signal from the
`memorycontroller. Also, in a data outputtingoperation, the
`DDR synchronous DRAM outputs data with a data strobe
`signal to the memory controller.
`In high speed semiconductor memory devices such as
`DDR synchronousDRAMs, a single mode (SM)-type input
`buffer, which compares a data strobe signal with a reference
`voltage, is used as a data strobe input buffer. However, in a
`DDR synchronous DRAM having an SM-type data strobe
`signal input buffer, a data setup/hold time margin may be
`degraded if noise is included in a data strobe signal or
`reference voltage.
`In order to compensate for this problem, a dual mode
`(DM)-type data strobe signal input buffer which compares a
`data strobe signal with the inverse signal of the data strobe
`signal instead of reference voltage has been introduced.
`Since an output signal is determined at the cross point of
`the two signals, that is, the data strobe signal and an inverse
`of the data strobe signal, in the DM-type data strobe signal
`input buffer, noise immunity improves.
`Also, more recently, in order to satisfy demands of a
`variety of users, an SM/DM dual-use data strobe signal input
`buffer has been developed. In an SM/DM dual-use data
`strobe signal input buffer, propagation delay time from an
`input terminal to an output terminal should be substantially
`the same both in the single mode (SM) and in the dual mode
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`(DM). However, since the gain of a differential amplifier in
`the single mode is different from the gain in the dual mode,
`the propagation delay time in the single mode is different
`from the propagation delay time in the dual mode.
`FIG. 1 illustrates waveforms produced in accordance with
`the prior art. As shown in FIG. 1, propagation delay time of
`the differential output signal (DS) in the SM mode is much
`greater than in the DM mode. Outputting the differential
`output signal (DS) at a different time in the SM mode and the
`DM mode degrades the uniformity of both the data setup
`time (tDS) and the data hold time (tDH) as illustrated in FIG.
`1. The difference in the propagation delay time may cause a
`difference in the setup/hold timing in each mode such that a
`data setup/hold margin is degraded.
`
`SUMMARY OF THE INVENTION
`
`invention are
`Exemplary embodiments of the present
`directed to a data buffer, which operates in a multiple modes,
`such as a data strobe input buffer or a data input buffer, each
`of which may operate a single mode (SM) and a dual mode
`(DM) and where a mode is selected by providing a signal,
`such as an external signal such as an address signal or an
`external command signal. The signal may be supplied by a
`number of sources, such as an internal mode register set
`(MRS), a fuse circuit, or a bonding pad circuit.
`Exemplary embodiments of the present invention are also
`directed to a data buffer which can be used for a SM/DM
`dual-use and can improve a data setup/hold margin.
`Exemplary embodiments of the present invention are also
`directed to a semiconductor memory device including one or
`more of the data buffers described above.
`In addition, exemplary embodiments of the present inven
`tion are directed to a method for controlling propagation
`delay time which can improve a data setup/bold margin in a
`SM/DM dual-use data buffer.
`Exemplary embodiments of the present invention are also
`directed to a data buffer including a differential amplifier
`circuit including at least two switches for passing an inverse
`data signal or a reference voltage, respectively, depending
`on a level of a control signal, and a differential amplifier for
`receiving a data signal, and either the inverse data signal or
`the reference voltage and outputting at least two different
`differentially amplified signals.
`In exemplary embodiments of the present invention, the
`data buffer is a data strobe input buffer, the inverse data
`signal is an inverse data strobe signal, and the data signal is
`a data strobe signal.
`In exemplary embodiments of the present invention, the
`data strobe input buffer is operable in both a single mode and
`a dual mode, wherein in said single mode,
`the reference
`voltage is applied to a first of the at least two switches and
`the level of the control signal is a first logic state and in said
`dual mode, the inverse data strobe signal is provided to a
`second of the at least two switches 212 and the level of the
`control signal is a second logic state.
`In exemplary embodiments of the present invention, the
`data strobe input buffer is part of a semiconductor memory
`device. In exemplary embodiments of the present invention,
`the semiconductor memory device also includes a control
`circuit for outputting the control signal to the data strobe
`input buffer.
`In exemplary embodiments of the present invention, the
`control circuit includes a mode register set for receiving an
`external command and an address and generating the control
`signal, wherein a level of the control signal determines a
`mode of the semiconductor memory device.
`
`

`

`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 17 of 24 PageID# 131
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`US 6,819,602 B2
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`the
`invention,
`In exemplary embodiments of the present
`control circuit
`includes a fuse circuit
`including a fuse,
`wherein a state of the fuse determines a level of the control
`signal.
`In exemplary embodiments of the present invention, the
`control circuit includes a bonding pad circuit, wherein a
`connection to Vcc or ground determines a level of the
`control signal.
`the
`invention,
`In exemplary embodiments of the present
`differential amplifier unit
`includes a single differential
`amplifier.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes a compen
`sating circuit for compensating one of the inverse data strobe
`signal, the reference voltage, or the data strobe signal or one
`of the at least two different differentially amplified signals so
`that each of at least
`two differential output signals have
`substantially the same delay time.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a delay circuit for receiving
`the differentially amplified signal from said differential
`amplifier circuit, said delay circuit including a delay for
`delaying the differentially amplified signal, at least two
`additional switches for passing the differentially amplified
`signal or the delayed differentially amplified signal, as one
`of the at least two differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the present invention, the
`compensatingcircuit includes a dummy load applied to one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal.
`In exemplary embodiments of the present invention, the
`differential amplifier unit includes at least two differential
`amplifiers.
`In exemplary embodiments of the present invention, a
`gain of a first of the at least two differential amplifiers is
`substantially different from a gain of a second of the at least
`two differential amplifiers so that each of at least two
`differential output signals have substantially the same delay
`time.
`In exemplary embodiments of the present invention, a
`gain of a first of the at least two differential amplifiers is
`substantially the same as a gain of a second of the at least
`two differential amplifiers.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes a compen
`sating circuit for compensatingone of the inverse data strobe
`signal,the reference voltage,or the datastrobesignalor one
`of the at least two different differentially amplified signals so
`that each of at least
`two differential output signals have
`substantially the same delay time.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a delay circuit for receiving
`the differentially amplified signal
`from said differential
`amplifier circuit, said delay circuit including a delay for
`delaying the differentially amplified signal, at least two
`additional switches for passing the differentially amplified
`signal or the delayed differentially amplified signal, as one
`of the at least two differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the present invention, the
`compensating circuit includes a dummy load applied to one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes data input
`buffer for receiving a data signal and a reference voltage and
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`outputting a data input signal, a control circuit for outputting
`the control signal to the data strobe input buffer, and a data
`write circuit for receiving the data input signal from said
`data input buffer and the writing even number data of the
`data input signal into a first latch in response to a rising edge
`of the output data signal and writing odd number data of the
`data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`In exemplary embodiments of the present invention, the
`first latch includes a plurality of latches and a plurality of
`switches, arranged alternatively. In exemplary embodiments
`of the present
`invention,
`the plurality of switches are
`arranged to be triggered on the leading and falling edge of
`an inverse of the differential output signal.
`invention, a
`In exemplary embodiments of the present
`first switch receives the even number data of the output
`signal of the data input buffer and passes the even number
`data of the output signal to a first of the plurality of latches.
`In exemplary embodiments of the present invention, the
`second latch including a plurality of latches and a plurality
`of switches, arranged alternatively.
`In exemplary embodiments of the present invention, the
`plurality of switches are arranged to be triggered on the
`leading and falling edge of an inverse of the differential
`output signal.
`In exemplary embodiments of the present invention, a
`first switch receives the odd number data of the output signal
`of the data input buffer and passes the odd number data of
`the output signal to a first of the plurality of latches.
`In exemplary embodiments of the present invention, the
`data buffer is a data input buffer instead of, or in addition to,
`a data strobe buffer.
`In exemplary embodiments of the present invention, the
`semiconductor memory device further includes a data strobe
`input buffer for receiving an inverse data signal or a refer
`ence voltage, respectively, depending on a level of a control
`signal, and outputting at least two differential output signals,
`a control circuit for outputting the control signal to said data
`strobe input buffer, and a data write circuit for receiving the
`data input signal from the data input buffer and the writing
`even number data of the data input signal into a first latch in
`response to a rising edge of the output data signal and
`writing odd number data of the data input signal into a
`second latch in response to a falling edge of the output data
`strobe signal.
`Exemplary embodiments of the present invention are also
`directed to a method of controlling propagation delay time
`of a semiconductor memory, including receiving an inverse
`data signal or a reference voltage, respectively, depending
`on a level of a control signal, receiving a data signal and
`either the inverse data signal or the reference voltage, and
`amplifying and outputting at least two different differentially
`amplified signals.
`In exemplary embodiments of the method of the present
`invention, the inverse data signal is an inverse data strobe
`signal and the data signal is a data strobe signal.
`In exemplary embodiments of the method of the present
`invention, in a single mode, the reference voltage is received
`and a level of the control signal is a first logic state and in
`a dual mode, the inverse data strobe signal is received and
`the level of the control signal is a second logic state.
`In exemplary embodiments of the method of the present
`invention, the control signal is received from an external
`source.
`In exemplary embodiments of the method of the present
`invention, the method also includes receiving an external
`command and an address and generating the control signal,
`
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`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 18 of 24 PageID# 132
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`US 6,819,602 B2
`
`wherein a level of the control signal determines an operation
`mode of the semiconductor memory.
`In exemplary embodiments of the method of the present
`invention, a state of a fuse determines a level of the control
`signal.
`In exemplary embodiments of the method of the present
`invention, a connection to Vcc or ground via a bonding pad
`determines a level of the control signal.
`In exemplary embodiments of the method of the present
`invention, the amplifying is performed by a single differen
`tial amplifier.
`In exemplary embodiments of the method of the present
`invention, the method further comprises compensating one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal or one of the at
`least
`two different
`differentially amplified signals so that each of at least two
`differential output signals have substantially the same delay
`time.
`In exemplary embodiments of the method of the present
`invention, the compensating includes receiving the differ
`entially amplified signal and delaying the differentially
`amplified signal, and outputting the differentially amplified
`signal or the delayed differentially amplified signal, as one
`of the at least two differential output signals, depending on
`the level of the control signal.
`In exemplary embodiments of the method of the present
`invention, the compensating is performed with a dummy
`load applied to one of the inverse data strobe signal, the
`reference voltage, or the data strobe signal.
`In exemplary embodiments of the method of the present
`invention,
`the amplifying is performed by at
`least
`two
`differential amplifiers.
`In exemplary embodiments of the method of the present
`invention, a gain of a first of the at least two differential
`amplifiers is substantiallydifferent from a gain of a second
`of the at least two differential amplifiers so that each of at
`least two differential output signals have substantially the
`same delay time.
`In exemplary embodimentsof the method of the present
`invention, a gain of a first of the at least two differential
`amplifiers is substantiallythe same as a gain of a second of
`the at least two differential amplifiers.
`In exemplary embodiments of the method of the present
`invention, the method further comprises compensating one
`of the inverse data strobe signal, the reference voltage, or the
`data strobe signal or one of the at least two different
`differentially amplified signals so that each of at least two
`differentialoutput signals have substantially the same delay
`time.
`In exemplary embodiments of the method of the present
`invention, the compensating includes receiving the differ
`entially amplified signal, delaying the differentially ampli
`fied signal, and outputting the differentially amplifiedsignal
`or the delayed differentially amplified signal, as one of the
`at least two differential output signals, depending on the
`level of the control signal.
`In exemplary embodiments of the method of the present
`invention,
`the compensating is performed with a dummy
`load applied to one of the inverse data strobe signal, the
`reference voltage, or the data strobe signal.
`In exemplary embodiments of the method of the present
`invention,
`the method further includes receiving a data
`signal and a reference voltage and outputting a data input
`signal, outputting the control signal, and receiving the data
`input signal and the writing even number data of the data
`input signal into a first latch in response to a rising edge of
`the output data signal and writing odd number data of the
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`data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`In exemplary embodiments of the method of (he present
`invention, the first latch includes a plurality of latches and a
`plurality of switches, arranged alternatively.
`In exemplary embodiments of the method of the present
`invention,
`the plurality of switches are arranged to be
`triggered on the leading and falling edge of an inverse of the
`differential output signal.
`In exemplary embodiments of the method of the present
`invention, a first switch receives the even number data of the
`output signal and passes the even number data of the output
`signal to a first of the plurality of latches.
`In exemplary embodiments of the method of the present
`invention, the second latch includes a plurality of latches and
`a plurality of switches, arranged alternatively.
`In exemplary embodiments of the method of the present
`invention,
`the plurality of switches are arranged to be
`triggered on the leading and falling edge of an inverse of the
`differential output signal.
`In exemplary embodiments of the method of the present
`invention, a first switch receives the odd number data of the
`output signal and passes the odd number data of the output
`signal to a first of the plurality of latches.
`In exemplary embodiments of the method of the present
`invention, the data buffer is a data input buffer instead of, or
`in addition to, a data strobe buffer.
`In exemplary embodiments of the method of the present
`invention,
`the method further includes receiving a data
`signal and a reference voltage and outputting a data input
`signal, outputting the control signal, and receiving the data
`input signal and the writing even number data of the data
`input signal into a first latch in response to a rising edge of
`the output data signal and writing odd number data of the
`data input signal into a second latch in response to a falling
`edge of the output data strobe signal.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The present invention will become more apparent by
`describing in detail exemplary embodiments thereof with
`reference to the attached drawings in which:
`FIG. 1 illustrates waveforms produced in accordance with
`the prior art;
`FIG. 2 is a block diagram of a data strobe input buffer
`according to an exemplary embodiment of the present
`invention;
`FIG. 3A is a block diagram of the switches according to
`an exemplary embodiment of the present invention;
`FIG. 3B is a block diagram which illustrates the conver
`sion from the control signal (CNT) to the inverse control
`signal (CNTB) according to an exemplary embodiment of
`the present invention;
`FIG. 4 is a block diagram of a control circuit according to
`an exemplary embodiment of the present invention;
`FIG. 5A is a block diagram of a control circuit according
`to another exemplary embodiment of the present invention;
`FIG. 5B illustrates a time versus voltage level plot relative
`to VCCH for the exemplary circuit of FIG. 5A;
`FIG. 6 is a block diagram of another control circuit
`according to another exemplary embodiment of the present
`invention;
`FIG. 7 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 8 is a block diagram of the switches according to an
`exemplary embodiment of the present invention;
`
`

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`Case 3:14-cv-00757-REP-DJN Document 1-6 Filed 11/04/14 Page 19 of 24 PageID# 133
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`US 6,819,602 B2
`
`FIG. 9 illustrates waveforms produced in accordance with
`one or more exemplary embodiments of the present inven
`tion;
`FIG. 10 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 11 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 12 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 13 is a block diagram of a data strobe input buffer
`according to another exemplary embodiment of the present
`invention;
`FIG. 14 is a block diagram of a data input buffer according
`to an exemplary embodiment of the present invention;
`FIG. 15 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 16 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 17 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 18 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 19 is a block diagram of a data input buffer according
`to another exemplary embodiment of the present invention;
`FIG. 20 is a block diagram of a semiconductor memory
`device according to an exemplary embodiment of the
`present invention;
`FIG. 21 illustrates the output of the data strobe signal
`(DQS) and the data signal (DQ) during DDR operation
`according to a semiconductor memory device according to
`an exemplary embodiment of the present invention;
`FIG. 22 is a block diagram of the latch circuit according
`to an exemplary embodiment of the present invention;
`FIG. 23 is a block diagram of a semiconductor memory
`device according to another exemplary embodiment of the
`present invention.
`
`DETAILED DESCRIPTION OF THE
`EXEMPLARY EMBODIMENTS OF THE
`PRESENT INVENTION
`FIG. 2 is a block diagram of a data strobe input buffer
`according to an exemplary embodiment of the present
`invention. The data strobe input buffer 13 is a multimode
`data strobe input buffer, for example, a single mode/dual
`mode (SM/DM) double-use data strobe input buffer. In
`response to a control signal (CNT/CNTB), the data strobe
`input buffer 13 differentially amplifies a data strobe signal
`(DQS) and a reference voltage (VREF), or the data strobe
`signal (DQS) and an inverse data strobe signal (DQSB).
`More specifically, the data strobe input buffer 13 includes
`a differential amplification circuit 21. The differential ampli
`fication circuit 21 further includes one or more switches 211
`and 212, and a differential amplifier 213. In an exemplary
`embodiment,
`the switches 211 and 212 are formed as
`transmission gates.
`If the control signal (CNT) is at a first logic state, for
`example, in a "high" logic level, the switch 211 is turned on
`and the switch 212 is turned off. Accordingly, the differential
`amplifier 213 differentially amplifies the data strobe signal
`(DQS) and the reference voltage (VREF), and the differen
`tial amplified signal (DO) is output. This is operation in the
`single mode (SM).
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`If the control signal (CNT) is at a "low" logic level, for
`example, if the inverse control signal (CNTB) is at a "high"
`logic level, the switch 212 is turned on, and the switch 211
`is turned off. Accordingly,
`the differential amplifier 213
`differentially amplifies the data strobe signal (DQS) and the
`inverse data strobe signal (DQSB), and the differentially
`amplified signal (DO) is output. This is operation in the dual
`mode (DM).
`FIG. 3A is a block diagram of the switches 211 and 212
`according to an exemplary embodiment of
`the present
`invention, where each switch 211,212 is implemented as a
`transmission gate. As illustrated, each transmission gate
`receives the control signal (CNT) and the inverse control
`signal (CNTB) and either the