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`Case 2:17'°V'0°547'RAJ'RJK D°°”"‘e“t lllllllllllllfllIIllllWllllllllllFllllfilllllflfllllfillfillfilll“9
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`USOO7620800B2
`
`US 7,620,800 B2
`(10) Patent No.:
`(12) Unlted States Patent
`Huppenthal et a].
`(45) Date of Patent:
`*Nov. 17, 2009
`
`
`(54) MULTI-ADAPTIVE PROCESSING SYSTEMS
`AND TECHNIQUES FOR ENHANCING
`PARALLELISM AND PERFORMANCE OF
`COMPUTATIONAL FUNCTIONS
`
`(75)
`
`Inventors: Jon M. Huppenthal, Colorado Springs,
`CO (US); David E. Caliga, Colorado
`Springs, CO (US)
`
`(73) Assignee: SRC Computers, Inc., Colorado
`Springs, CO (US)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 95 days.
`
`This patent is subject to a terminal dis-
`claimer.
`
`(21) Appl.No.: 11/733,064
`.
`Flledi
`
`APE 9: 2007
`
`(22)
`
`(65)
`
`Prior Publication Data
`US 2007/0204131A1
`Aug. 30, 2007
`
`Related U.S.Application Data
`(63) Continuation of application No. 10/285,318, filed on
`Oct. 31, 2002, now Pat. No. 7,225,324.
`
`(51)
`
`Int. Cl.
`G06F 15/82
`712/226
`(52) US. Cl.
`(58) Field of ClasslficatlonSearch""""""""""""" 712/226
`712/15,19,215
`See application file for complete search history.
`
`(2006.01)
`
`(56)
`
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`d
`C t'
`( Onmue)
`Primary ExamineriEric Coleman
`(74) Attorney, Agent, or FirmiMichael C. Martensen;
`William J‘ Kubida; Hogan & Hartson LLP
`(57)
`ABSTRACT
`
`.
`.
`.
`.
`for
`Multl-adaptlve process1ng systems and techmques
`enhancing parallelism and performance of computational
`functions are disclosed which can be employed in a myriad of
`.
`.
`.
`.
`.
`.
`.
`.
`.
`app11catlons 1nclud1ng mult1-d1mens1onal p1pe11ne computa-
`tions for seismic applications, search algorithms, information
`security, chemical and biological applications, filtering and
`the like as well as for systolic wavefront computations for
`fluid flow and structures analysis, bioinformatics etc. Some
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`pipeline and systolic wavefront methodologies disclosed.
`
`52 Claims, 20 Drawing Sheets
`
`
`9‘?
`
`o8'90,0
`
`
`‘0’2‘0oz.9C
`o
`O
`0:.0:.‘9
`o9.'9"
`
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`Awmuu.MINEmacaw:
`.3.0:.‘3‘3
`
`0:.0:..0
`cars
`
`e 9.e
`
`
`
`
`
`
`3:..:§:§:9::::::°~
`
`ADAPTIVE PROCESSOR CHIP
`
`
`
`
`
`
`INYEIOONNEG'
`
`

`

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`US 7,620,800 B2
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`Automatic Target Recognition, Colorado State University & USAF,
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`Secret-Key Block Ciphers Using Mixed Inner- and Outer-Round
`Pipelining, George Mason University, Feb. 11-13, 2001, pp. 9.
`Hastie, Neil, et a1., “The Implementation of Hardware Subroutines on
`Field Programmable Gate Arrays”, XPO 1 000 5485, Plessey Semicon-
`ductors, Tamerton Rd., Plymouth, Devon, England, IEEE, May 13,
`1990, Custom Integrated Circuits Conference, pp. 314. 1-4. *the
`whole document*.
`Harbaum, Till, et a1., “Design of a Flexible Coprocessor Unit”, Insti-
`tute
`of Operating
`Systems
`and Computer Networks,
`XP000879556TU Braunschweig, Germany, Proceedings of the
`Euromicro Conference, Sep. 1999, pp. 335-342. *whole document*.
`Mathias P C; Patnaik L M: “Systolic Evaluation of Polynomial
`Expressions,” IEEE Transactions on Computers, vol. 39, No. 5, May
`1, 1990, pp. 653-665, XP000116659.
`
`* cited by examiner
`
`

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`1
`MULTI-ADAPTIVE PROCESSING SYSTEMS
`AND TECHNIQUES FOR ENHANCING
`PARALLELISM AND PERFORMANCE OF
`COMPUTATIONAL FUNCTIONS
`
`CROSS REFERENCE TO RELATED PATENT
`APPLICATIONS
`
`The present application is a Continuation of US. patent
`application Ser. No. lO/285,318 filed Oct. 31, 2002 which is
`related to the subject matter of US. patent application Ser.
`No. 09/755,744 filed Jan. 5, 2001 for: “Multiprocessor Com-
`puterArchitecture Incorporating a Plurality ofMemory Algo-
`rithm Processors in the Memory Subsystem” and is further
`related to the subject matter of US. Pat. No. 6,434,687 for:
`“System and Method for Accelerating Web Site Access and
`Processing Utilizing a Computer System Incorporating
`Reconfigurable Processors Operating Under a Single Oper-
`ating System Image”, all of which are assigned to SRC Com-
`puters, Inc., Colorado Springs, C010. and the disclosures of
`which are herein specifically incorporated in their entirety by
`this reference.
`
`COPYRIGHT NOTICE/PERMISSION
`
`A portion of the disclosure of this patent document may
`contain material which is subject to copyright protection. The
`copyright owner has no objection to the facsimile reproduc-
`tion by anyone ofthe patent document or the patent disclosure
`as it appears in the United States Patent and Trademark Office
`patent file or records, but otherwise, reserves all copyright
`rights whatsoever. The following notice applies to the soft-
`ware and data and described below, inclusive of the drawing
`figures where applicable: Copyright © 2000, SRC Comput-
`ers, Inc.
`
`BACKGROUND OF THE INVENTION
`
`The present invention relates, in general, to the field of
`computing systems and techniques. More particularly, the
`present invention relates to multi-adaptive processing sys-
`tems and techniques for enhancing parallelism and perfor-
`mance of computational functions.
`Currently, most large software applications achieve high
`performance operation through the use ofparallel processing.
`This technique allows multiple processors to work simulta-
`neously on the same problem to achieve a solution in a frac-
`tion of the time required for a single processor to accomplish
`the same result. The processors in use may be performing
`many copies of the same operation, or may be performing
`totally different operations, but in either case all processors
`are working simultaneously.
`The use of such parallel processing has led to the prolif-
`eration of both multi-processor boards and large scale clus-
`tered systems. However, as more and more performance is
`required, so is more parallelism, resulting in ever larger sys-
`tems. Clusters exist today that have tens of thousands of
`processors and can occupy football fields of space. Systems
`of such a large physical size present many obvious down-
`sides, including, among other factors, facility requirements,
`power, heat generation and reliability.
`
`SUMMARY OF THE INVENTION
`
`However, if a processor technology could be employed that
`offers orders of magnitude more parallelism per processor,
`these systems could be reduced in size by a comparable
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
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`
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`
`factor. Such a processor or processing element is possible
`through the use of a reconfigurable processor. Reconfigurable
`processors instantiate only the functional units needed to
`solve a particular application, and as a result, have available
`space to instantiate as many functional units as may be
`required to solve the problem up to the total capacity of the
`integrated circuit chips they employ.
`At present, reconfigurable processors, such as multi-adap-
`tive processor elements (MAPTM, a trademark of SRC Com-
`puters, Inc.) can achieve two to three orders of magnitude
`more parallelism and performance than state-of-the-art
`microprocessors. Through the advantageous application of
`adaptive processing techniques as disclosed herein, this type
`ofreconfigurable processing parallelism may be employed in
`a variety of applications resulting in significantly higher per-
`formance than that which can now be achieved while using
`significantly smaller and less expensive computer systems.
`However, in addition to these benefits, there is an addi-
`tional much less obvious one that can have even greater
`impact on certain applications and has only become available
`with the advent of multi-million gate reconfigurable chips.
`Performance gains are also realized by reconfigurable pro-
`cessors due to the much tighter coupling of the parallel func-
`tional units within each chip than can be accomplished in a
`microprocessor based computing system.
`In a multi-processor, microprocessor-based system, each
`processor is allocated but a relatively small portion ofthe total
`problem called a cell. However, to solve the total problem,
`results of one processor are often required by many adjacent
`cells because their cells interact at the boundary and upwards
`of six or more cells, all having to interact to compute results,
`would not be uncommon. Consequently, intermediate results
`must be passed around the system in order to complete the
`computation of the total problem. This, of necessity, involves
`numerous other chips and busses that run at much slower
`speeds than the microprocessor thus resulting in system per-
`formance often many orders ofmagnitude lower than the raw
`computation time.
`On the other hand, in the use of an adaptive processor-
`based system, since ten to one thousand times more compu-
`tations can be performed within a