Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 1 of 25
`
`Exhibit C
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 2 of 25
`I 1111111111111111 11111 1111111111 11111 111111111111111 IIIII lll111111111111111
`US007804435B2
`
`c12) United States Patent
`Sadowski et al.
`
`(IO) Patent No.:
`(45) Date of Patent:
`
`US 7,804,435 B2
`Sep.28,2010
`
`(54) VIDEO DECODER WITH REDUCED POWER
`CONSUMPTION AND METHOD THEREOF
`
`(75)
`
`Inventors: Greg Sadowski, Cambridge, MA (US);
`George Jacobs, Sterling, MA (US); Paul
`Chow, Riclnnond Hill (CA)
`
`(73) Assignee: ATI Technologies ULC, Markham,
`Ontario (CA)
`
`( *) Notice:
`
`Subject to any disclaimer, the term ofthis
`patent is extended or adjusted under 35
`U.S.C. 154(b) by O days.
`
`(21) Appl. No.: 11/469,335
`
`(22) Filed:
`
`Aug. 31, 2006
`
`(65)
`
`(51)
`
`(52)
`(58)
`
`(56)
`
`Prior Publication Data
`
`US 2008/0055119 Al
`
`Mar. 6, 2008
`
`Int. Cl.
`H03M 1112
`(2006.01)
`U.S. Cl. ...................................................... 341/155
`Field of Classification Search ................. 341/155,
`341/157, 158; 375/222, 219, 316, 345
`See application file for complete search history.
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,711,672 A
`5,719,800 A
`5,734,779 A *
`6,332,168 Bl
`6,477,654 Bl
`6,795,930 Bl
`6,957,422 B2
`6,978,085 Bl *
`7,174,392 B2
`
`1/1998 Redford et al.
`2/1998 Mirta! et al.
`3/1998 Okino ......................... 386/38
`12/2001 House et al.
`11/2002 Dean et al.
`9/2004 Laurenti et al.
`10/2005 Hunt
`12/2005 Maeda et al.
`2/2007 Tervo
`
`............... 386/112
`
`6/2007 Gluck
`7,227,847 B2
`7,372,999 B2 *
`5/2008 Oneda et al. ................ 382/232
`7/2008 Heller et al.
`7,401,240 B2
`10/2003 Aisaka et al.
`2003/0184271 Al
`2004/0010785 Al
`1/2004 Chauvel et al.
`2/2004 White et al.
`2004/0039954 Al
`2004/0136596 Al*
`7/2004 Oneda et al. ................ 382/232
`2004/0158748 Al*
`8/2004 Ishibashi et al.
`............ 713/300
`8/2004 Borza et al.
`2004/01587 52 Al
`12/2004 Fisher et al.
`2004/0268316 Al
`4/2005 DeWitt, Jr. et al.
`2005/0081107 Al
`9/2005 Desylva
`2005/0200627 Al
`2005/0232136 Al* 10/2005 Kwak ......................... 370/208
`12/2005 Grohman
`2005/0273636 Al
`2006/0044468 Al *
`3/2006 Chowdhury et al.
`2006/0123262 Al
`6/2006 Bullman
`
`........ 348/465
`
`(Continued)
`
`OTHER PUBLICATIONS
`
`International Search Report and Written Opinion; International
`Application No. PCT/US2007/077346; dated Aug. 14, 2008.
`
`Primary Examiner-Brian Young
`(74) Attorney, Agent, or Firm-Vedder Price P.C.
`
`(57)
`
`ABSTRACT
`
`A video decoder (10) with reduced power consumption
`includes a power management controller ( 45) that is operative
`to select one of a plurality of different power consumption
`states for a video decoder (10), and, in response to the deter(cid:173)
`mination, vary power consumption of at least one operational
`portion of the video decoder (10). In addition, in one example,
`a method (200) for reducing power consumption for a video
`decoder (10) includes determining input stream encoding
`description data (34) to select one of a plurality of different
`power consumption states for a video decoder (10) and, in
`response to the determination, varying power consumption of
`at least one operational portion of the video decoder (10).
`
`26 Claims, 12 Drawing Sheets
`
`CODE AND
`APPLICATION
`PROFILE DATA
`FROM
`WIRELESS
`NETv\lORK
`
`BATTERY-POWERED
`DEVICE
`
`10
`
`15
`
`80
`
`POWER
`MANAGEMENT
`CONTROLLER
`
`70
`
`IDLE
`REGISTER
`
`108
`
`102
`
`96
`
`SCLKPROG
`
`MCLKPROG
`POWER SUPPLY PROG
`
`GPU WITH POWER
`MANAGEMENT
`
`..,------,~=--r::e=ow:,:E:::-R-::SU-:::P-:',PL,.,.Y /
`VOLTAGE
`
`73
`
`Ex. C, p. 1
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 3 of 25
`
`US 7,804,435 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`2006/0136764 Al
`6/2006 Munguia
`2007 /0064159 Al * 3/2007 Kim et al. ................... 348/730
`
`2008/0059823 Al
`
`3/2008 Balatsos et al.
`
`* cited by examiner
`
`Ex. C, p. 2
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 4 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 1 of 12
`
`US 7,804,435 B2
`
`BATTERY-POWERED
`DEVICE
`
`10
`
`15
`
`80
`
`118
`
`POWER
`MANAGEMENT
`CONTROLLER
`
`CODE; APPLICATION CODE; APPLICATION
`PROFILE DATA
`PROFILE DATA
`
`CONTROLLER
`
`CODE AND
`APPLICATION
`PROFILE DATA
`FROM
`WIRELESS
`NETWORK
`
`112
`
`116
`
`54
`
`MCLK
`
`94
`
`SCLK
`
`3D
`ENGINE
`
`56
`
`MEMORY
`CONTROLLER
`
`MEMORY
`CONTROL
`
`MEMORY
`
`IDLE BITS
`
`110
`
`108
`
`IDLE
`REGISTER
`
`102
`
`96
`
`98
`
`90
`
`OSCILLATOR 40
`
`45
`
`CRYSTAL
`
`MCLKPROG
`
`POWER SU PPL Y PROG
`
`GPU WITH POWER
`MANAGEMENT
`
`68
`
`GENERAL PURPOSE 1/0
`
`72
`
`66
`
`POWER SUPPLY
`VOLTAGE INPUT
`
`50
`
`POWER SUPPLY SET
`
`73
`
`POWER SUPPLY
`VOLTAGE
`
`FIG. 1
`
`Ex. C, p. 3
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 5 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 2 of 12
`
`US 7,804,435 B2
`
`START
`
`EXECUTE CODE INCLUDING APPLICATION
`PROFILE DATA IDENTIFYING USAGE OF
`PORTIONS OF PROCESSOR DURING
`RUNTIME
`
`210
`
`IN RESPONSE TO APPLICATION PROFILE
`DATA IDENTIFYING USAGE OF PORTIONS OF
`THE PROCESSOR, CONTROL POWER
`CONSUMPTION OF IDENTIFIED PORTIONS OF
`PROCESSOR
`
`220
`
`END
`
`FIG. 2
`
`Ex. C, p. 4
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 6 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 3 of 12
`
`US 7,804,435 B2
`
`START
`
`PROFILE APPLICATION USAGE OF
`PORTIONS OF PROCESSOR USED
`DURING EXECUTION OF APPLICATION
`CODE BASED ON IDLE BITS
`
`STORE APPLICATION PROFILE DATA
`IDENTIFYING USAGE OF PORTIONS OF
`PROCESSOR WITH APPLICATION
`CODE
`
`310
`
`320
`
`330
`
`NO
`
`END
`
`YES
`
`FIG. 3
`
`Ex. C, p. 5
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 7 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 4 of 12
`
`US 7,804,435 B2
`
`START
`
`ACCESS APPLICATION PROFILE
`DATA IN APPLICATION
`
`DETERMINE PROCESSOR PORTION
`USAGE BY APPLICATION BASED ON
`APPLICATION PROFILE DATA
`
`CONTROL POWER CONSUMPTION
`OF PROCESSOR PORTIONS BASED
`ON PROCESSOR PORTION USAGE
`
`410
`
`420
`
`430
`
`END
`
`FIG.4
`
`Ex. C, p. 6
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 8 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 5 of 12
`
`US 7,804,435 B2
`
`START
`
`RECORD IDLE REGISTER VALUES AND
`CLOCK/VOLTAGE REGISTER VALUES
`DURING APPLICATION RUNTIME
`
`TRANSFER IDLE REGISTER VALUES AND
`CLOCK/VOLTAGE REGISTER VALUES AS
`APPLICATION PROFILE DATA TO OFFLINE
`STORAGE
`
`510
`
`520
`
`NO
`
`540
`
`STORE APPLICATION PROFILE DATA WITH
`APPLICATION
`
`FIG. 5
`
`END
`
`Ex. C, p. 7
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 9 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 6 of 12
`
`US 7,804,435 B2
`
`START
`
`IDENTIFY CALLS TO PROCESSOR
`IN APPLICATION DURING RUNTIME
`
`MAP CALLS TO PROCESSOR TO
`SPECIFIC PORTIONS OF THE
`PROCESSOR
`
`610
`
`620
`
`STORE CALLS TO PROCESSOR PORTIONS AS
`APPLICATION PROFILE DATA TO OFFLINE STORAGE
`
`630
`
`STORE APPLICATION PROFILE DATA IN
`APPLICATION
`
`FIG. 6
`
`END
`
`Ex. C, p. 8
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 10 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 7 of 12
`
`US 7,804,435 B2
`
`,---B-A_T_T_E_R_Y_-P_O_W_E_R_E_D ____ 7_2_0 _ _ _ _ _ ---:::=~==============:::;-----3-5-------,-,-:---......-,:IDENTIFYING
`DEVICE
`MEMORY
`DATA FROM
`WIRELESS
`NETWORK
`
`APPLICATION
`
`CODE
`
`710
`
`APPLICATION USAGE PROFILER
`CO-PROCESSOR
`
`740
`
`CODE
`
`PROFILER
`
`730
`
`15 APPLICATION PROFILE DATA
`
`118
`
`, - - -
`I
`I
`POWER
`8ZJ. MANAGEMENT I
`I CONTR~'=-=_RJ
`
`116
`
`54
`
`56
`
`2D
`ENGINE
`
`SCLK
`
`3D
`ENGINE
`
`MCLK
`
`MEMORY
`CONTROL
`MEMORY
`CONTROLLER11----,~ ..
`
`IDLE BITS
`
`108
`
`IDLE
`REGISTER
`
`110
`
`90
`
`OSCILLATOR
`
`45
`
`CRYSTAL
`
`MCLKPROG
`
`POWER SUPPLY PROG
`
`GPU WITH POWER
`MANAGEMENT
`
`68
`
`GENERAL PURPOSE 1/0
`
`66
`
`POWER SUPPLY
`VOLTAGE INPUT
`
`50
`
`106
`
`POWER SUPPLY SET
`POWER SUPPLY
`VOLTAGE
`
`VOLTAGE
`GENERATOR
`
`73
`
`FIG. 7
`
`Ex. C, p. 9
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 11 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 8 of 12
`
`US 7,804,435 B2
`
`VOLTAGE CONTROL
`
`CLOCK
`87c)
`CONTROL
`~ CLOCK GENERATOR
`~ sis
`
`85l...,
`
`~
`
`/
`850
`
`µ54
`
`828
`
`POWER SUPPLY
`
`MCLK
`
`UVD
`VOLTAGE ...../874
`~866
`
`39
`
`llQ-5.
`
`DRAM
`VOLTAGE
`
`878)
`
`+
`
`MEMORY
`INTERFACE
`
`882
`_ VMBUS2)
`
`-
`
`822
`~
`
`+ i
`-
`- CONTROLLE
`
`MEMORY
`
`R
`
`810
`'-'
`
`UVD
`
`1J
`
`DCLK
`
`SCLK
`
`8~ ....
`
`--820
`
`V
`
`POWER
`MANAGEMENT
`CONTROLLER
`
`ro -
`
`-
`
`VMBUS1
`-
`
`LEVEL
`FORMATION
`IN
`go-/
`8
`
`REC EIVE INPUT
`
`STR EAM FROM
`w
`IRELESS
`ETWORK
`N
`
`815
`'---
`
`~ 894 u
`Y,
`
`I
`Ix
`CVR
`I
`
`I
`I
`.J
`
`)
`
`830
`
`)
`
`896
`
`VIDEO
`PROCESSING
`UNIT(VPU)
`
`ll
`
`834 -
`
`/
`
`VBUS
`
`,:::::
`
`-
`
`REVERSE ENTROPY
`PROCESSOR
`
`)
`838
`
`VMBUS3
`
`-
`
`-
`
`8~,) -
`
`' - -
`
`DRAM
`
`826
`
`VBUS2
`
`'--s24
`
`'--" 847
`
`/844
`I
`+ '
`
`DECODED
`STREAM -
`84J
`
`MACROBLOCK
`PROCESSOR
`
`842
`_)
`
`DECODER
`
`811
`
`FIG. 8
`
`Ex. C, p. 10
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 12 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 9 of 12
`
`US 7,804,435 B2
`
`(
`
`START
`
`)
`
`~---------------,-Je---__ -_________ ,
`I
`I
`910
`DETERMINE IF MORE THAN ONE INPUT STREAM AND
`INCREASE POWER CONSUMPTION OF AT LEAST ONE ~
`I
`I PORTION OF THE VIDEO DECODER IN RESPONSE TO THE I
`L_ _______ _?ETERMINATION ________ J
`
`DETERMINE INPUT STREAM ENCODING DESCRIPTION DATA
`TO SELECT ONE OF A PLURALITY OF DIFFERENT POWER
`CONSUMPTION STATES FOR THE VIDEO DECODER
`
`VARY POWER CONSUMPTION OF AT LEAST ONE
`OPERATIONAL PORTION OF THE VIDEO DECODING IN
`RESPONSE TO THE DETERMINATION
`
`920
`
`930
`
`FIG. 9
`
`END
`
`Ex. C, p. 11
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 13 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 10 of 12
`
`US 7,804,435 B2
`
`START
`
`ANALYZE HEADER INFORMATION TO OBTAIN PROFILE AND
`LEVEL INFORMATION ON A PER BLOCK, SLICE, FRAME, OR
`STREAM BASIS
`
`1000
`
`1010
`
`USE POWER MANAGEMENT CONTROL TABLE TO OBTAIN
`CLOCK SETTINGS AND POWER SUPPLY SETTINGS FOR
`VARIOUS DECODER CIRCUITS
`
`CONTROL CLOCK GENERA TOR AND POWER SUPPLY TO
`PROVIDE LEVELS FROM TABLE
`
`1030
`
`FIG. 10
`
`END
`
`Ex. C, p. 12
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 14 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 11 of 12
`
`US 7,804,435 B2
`
`1140
`
`LEVEL
`INFORMATION
`
`1170
`
`845
`
`POWER
`MANAGEMENT
`CONTROLLER
`(HOST
`DRIVER)
`
`HOST
`PROCESSOR
`
`VOLTAGE CONTROL
`
`1160
`
`CLOCK GENERATOR
`
`VCLK
`
`854
`
`858
`
`828
`
`862
`
`.11.Q_Q_
`
`POWER SUPPLY
`
`829
`
`878
`
`DRAM
`VOLTAGE
`
`UVD
`VOLTAGE
`
`874
`
`RECEIVE INPUT
`STREAM FROM
`WIRELESS
`NETWORK
`
`1120
`
`VIDEO
`PROCESSOR
`UNIT (VPU)
`
`DCLK
`
`SCLK
`
`882
`
`880
`
`VMBUS1
`
`MEMORY
`INTERFACE
`
`- - - -~ -~ MEMORY
`CONTROL
`
`VMBUS3
`
`822
`
`847
`
`824 826
`
`~ 9 4
`
`Y.
`I -I INPUT
`XCVR STREAM
`LJ_
`I
`I
`
`815
`
`83
`
`896
`
`83
`
`REVERSE ENTROPY
`PROCESSOR
`
`DECODED
`STREAM
`
`843
`
`DECODER
`
`MACROBLOCK
`PROCESSOR
`
`842
`
`811
`
`FIG. 11
`
`Ex. C, p. 13
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 15 of 25
`
`U.S. Patent
`
`Sep.28,2010
`
`Sheet 12 of 12
`
`US 7,804,435 B2
`
`HOST REGISTER
`-
`PORT
`
`1204
`
`810
`
`122
`12~
`RI
`---------:-12-::-:2:'_ ~
`
`CM
`
`VPU
`
`SHARED
`REGISTER
`
`QUEUE 0
`
`QUEUE1
`
`820
`
`1200
`
`MEMORY
`READ/WRITE
`PORT
`
`\.1208
`
`BITSTREAM
`READ PORT
`
`MEMORY
`WRITE PORT
`
`MEMORY
`READ PORT
`
`\.1206
`
`\.1210
`
`~212
`
`1202
`
`FIG. 12
`
`Ex. C, p. 14
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 16 of 25
`
`US 7,804,435 B2
`
`1
`VIDEO DECODER WITH REDUCED POWER
`CONSUMPTION AND METHOD THEREOF
`
`RELATED CO-PENDING APPLICATION
`
`This is a related application of copending application Ser.
`No. 11/469,326, entitled BATTERY-POWERED DEVICE
`WITH REDUCED POWER CONSUMPTION AND
`METHOD THEREOF, filed on Aug. 31, 2006, having as
`inventors Aris Balatsos et al., and owned by instant assignee
`and incorporated by reference in its entirety.
`
`FIELD OF THE INVENTION
`
`The invention relates generally to video decoders and,
`more particularly, to a video decoder with reduce power con(cid:173)
`sumption and method thereof.
`
`BACKGROUND OF THE INVENTION
`
`2
`FIG. 3 is one example of a method of determining identi(cid:173)
`fying data for use in controlling power consumption depicting
`one embodiment of the invention;
`FIG. 4 is one example of a method of controlling power
`5 consumption depicting one embodiment of the invention;
`FIG. 5 is one example of a method of determining identi(cid:173)
`fying data for use in controlling power consumption depicting
`one embodiment of the invention;
`FIG. 6 is one example of a method of determining identi-
`10 fying data for use in controlling power consumption depicting
`one embodiment of the invention;
`FIG. 7 is one example of a battery-powered device depict(cid:173)
`ing one embodiment of the invention;
`FIG. 8 is one example of a video decoding system depict-
`15 ing one embodiment of the invention;
`FIG. 9 is one example of a method of controlling power
`consumption depicting one embodiment of the invention;
`FIG. 10 is one example of a method of controlling power
`consumption depicting one embodiment of the invention;
`FIG. 11 is one example of a video decoding system depict(cid:173)
`ing one embodiment of the invention; and
`FIG. 12 is a block diagram illustrating one example of a
`decoder that can be controlled as described herein.
`
`20
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`50
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention and the corresponding advantages
`and features provided thereby will be best understood and
`appreciated upon review of the following detailed description
`of the invention, taken in conjunction with the following
`drawings, where like numerals represent like elements, in
`which:
`FIG. 1 is one example of a battery-powered device depict(cid:173)
`ing one embodiment of the invention;
`FIG. 2 is one example of a method of controlling power
`consumption depicting one embodiment of the invention;
`
`Despite improvements in rechargeable battery technology,
`battery capability continues to limit performance of mobile
`electronic devices. In particular, limited energy capacity
`results in relatively short device run-times, of, for example,
`only a few hours, between recharging or switching batteries. 25
`In addition, functional integration, such as in the example of
`integrating camera functions onto a cellular telephone hand(cid:173)
`set, results in popular multiple function devices yet may
`increase energy consumption. Video encoding/decoding
`operations such as MPEG, H.264, VC-1 based encoding and/ 30
`or decoding or other video coding circuits can consume lim(cid:173)
`ited battery power.
`Power conservation techniques may be used to compensate
`for battery limitations in battery-powered devices. For
`example, low power modes may be used to conserve power by
`selectively shutting down certain components or functional
`blocks within components. Alternatively, power may be
`saved by reducing power supply voltages or clocking fre(cid:173)
`quencies. Typical low power modes are entered either by
`direct operator interaction, such as by placing the device to
`low power mode, or by a triggering event. A triggering event
`may occur when, for example, the battery capacity drops
`below a certain threshold. Alternatively, a low power mode
`may be triggered when certain functional blocks in the device
`have not been used or accessed for some period of time. These
`triggering events may be useful for conserving battery power;
`however, each is reactive rather than proactive. That is, sig(cid:173)
`nificant battery may be consumed prior to triggering. As a
`result, the triggering techniques may not be sufficient to pro-
`vide sufficient energy conservation in all cases. Since video
`decoders in battery-powered devices can consume significant
`energy, improved video decoders with reduce power con(cid:173)
`sumption and methods thereof would be desirable.
`
`40
`
`45
`
`Briefly, an apparatus employs a power management con(cid:173)
`troller, in response to a determination of encoding description
`data and varies power consumption of at least one operational
`portion of a video decoder. The apparatus may also include
`the decoder. In addition, in one example, a method for reduc(cid:173)
`ing power consumption for a video decoder includes deter-
`mining input stream encoding description data to select one
`of a plurality of different power consumption states for a
`35 video decoder and, in response to the determination, varying
`power consumption of at least one operational portion of the
`video decoder.
`In one example, a video decoder is disclosed with reduced
`power consumption. Power is proactively and automatically
`conserved prior to significant battery discharge and without
`operator intervention. Power consumption is varied in por-
`tions of the video decoder in response to encoding character(cid:173)
`istics from an input data stream to minimize power consump(cid:173)
`tion while achieving required performance. Other advantages
`will be recognized by one of ordinary skill in the art.
`In another embodiment, a device includes a processor that
`is operative to process a data stream such as executable code,
`encoded video or other suitable data stream, and has a plural(cid:173)
`ity of processor portions. The device further includes a power
`management controller coupled to the processor portions that
`controls power consumption of the processor portions based
`on information associated with or in the data stream. The
`information may include application profile data included
`with executable code that directly indicates usage/nonusage
`55 of portions of the processor or the data stream may have use
`data inherent in the stream, that indirectly identifies usage of
`the processor portions. In addition, in one example, a method
`for reducing power consumption for a battery powered device
`includes executing code that includes application profile data
`60 identifying usage of portions of a first processor during runt(cid:173)
`ime of an application; and, in response to the application
`profile data, controlling power consumption of the identified
`first processor portions during runtime. In addition, in one
`example, a battery-powered device includes memory that
`65 stores the code and a first processor coupled to the memory
`and operative to execute the code. The power management
`controller may be part of the processor or external thereto.
`
`Ex. C, p. 15
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 17 of 25
`
`US 7,804,435 B2
`
`3
`The application profiling data may be generated by an appli(cid:173)
`cation developer and embedded as header information in the
`code or may be generated by the device the first time the
`application is run on the device, or at any other suitable time.
`In such a case, it may be necessary to create header informa(cid:173)
`tion specific to a particular device or class of devices reflec(cid:173)
`tive of the differing capabilities and/ or processors ( or portions
`thereof). In this case, it may be desirable applications with
`embedded header information that is specific to a particular
`device ( or class of devices). Alternatively, the header infor(cid:173)
`mation may include more than one header information por(cid:173)
`tions with each portion associated with a particular device ( or
`class of devices). In a further alternative, the application could
`be transferred to a device without any header information but,
`instead, be transferred with associated (but separate) applica(cid:173)
`tion profile data. In such an embodiment, the application
`could be unchanged for a variety of devices ( or classes of
`devices) while only device (or device class) specific applica(cid:173)
`tion profile data would vary between the variety of devices ( or
`classes of devices).
`As such, a battery-powered device is disclosed with
`reduced power consumption wherein power is proactively
`and automatically conserved prior to significant battery dis(cid:173)
`charge and, if desired, without operator intervention. Portions
`of a processor included in the device are automatically iden- 25
`tified for power consumption based on application runtime
`profiling. Power is conserved in the identified portions using
`any desired power saving method. The power consumption
`technique is useful for a wide variety of battery-powered
`devices. Other advantages will be recognized by one of ordi- 30
`nary skill in the art.
`FIG. 1 is one example of a battery-powered device 10
`depicting one example of one embodiment of the invention.
`The battery-powered device 10 may be a handheld device or
`a non-handheld device. For purposes of illustration only, and 35
`not limitation, FIG. 1 illustrates an example where a data
`stream is considered executable code with header informa(cid:173)
`tion that includes application profile data. A later example
`will be set forth below where the data stream is an encoded
`video data stream. However it will be recognized that any
`suitable data stream and device may be employed. It should
`be recognized that while in many instances the "header infor(cid:173)
`mation" may be placed at or near the beginning of a data
`stream it could, in many instances, be placed elsewhere in the
`data stream.
`The battery-powered device 10 may have wireless capabil(cid:173)
`ity and/or non-wireless capability. The battery-powered
`device 10 may, for example, be a wireless telephone, a per(cid:173)
`sonal computer, a digital assistant (such as a personal digital
`assistant-PDA), a digital entertainment/playback device, a
`radio communication device, a tracking device, a personal
`training device, a global positioning device, a camera, a video
`recorder, a video game controller, a television receiver, a
`digital video player, a printing device, a digital display, a
`combination thereof or any suitable device.
`The battery-powered device 10 includes a processor 15 and
`a memory 20 including application code 25 in any suitable
`format. As used herein code or application can also include
`data if desired. The battery-powered device 10 may further
`include a wireless network interface including a wireless
`transceiver 30 operatively coupled to a controller 35. The
`battery-powered device 10 may further include additional
`memory 40, a crystal oscillator 45, and a voltage generator 50
`operatively to the processor 15.
`For purposes of illustration only, the processor 15 is shown
`as a graphics processing core (GPU) or multimedia process(cid:173)
`ing core. However, processors of other types, architectures,
`
`4
`and capabilities may be used as will be recognized by one
`skilled in the art. For example, a digital signal processor
`(DSP), microcontroller, central processing unit, baseband
`processor, co-processor, or any suitable processing circuit(s)
`5 may be used. In addition the processor 15 may be discrete
`logic, or any suitable combination of hardware, software or
`firmware or any suitable structure. The processor 15 may be
`made up of several portions, or functional blocks. The por(cid:173)
`tions provide or control functions contributing to the function
`10 of the overall processor 15. The operating portions may
`include, but are not limited to, a 2D engine 52, a 3D engine 54,
`a memory controller 56, a phase-lock loop (PLL) circuit
`including system PLL 60 and memory PLL 62, clock fre(cid:173)
`quency registers including system clock register 64 and main
`15 clock register 66, a general purpose input/output registers 68,
`an idle bit register 70, and a power supply voltage input 72.
`The processor 15 further includes a power management con(cid:173)
`troller 80. The processor 15 may further include arithmetic
`units, on-chip memory, address decoders and encoders, video
`20 decoders and encoders, co-processors, and other portions as
`are known in the art.
`The operational instructions, such as executable code 25,
`or software, executed by the processor 15 are stored in
`memory 20 which may include any suitable digital storage
`medium including, but not limited to, RAM, ROM, flash
`memory, hard disk drive, distributed memory such as servers
`with memory on a network, CD-ROM or any suitable storage
`medium. It will be recognized that such memory may be
`integrated with the controller or take any suitable configura(cid:173)
`tion.
`The memory 20 stores application code 25 that is executed
`by the processor 15. The application code 25 may further
`include application profile data 84, such as in headers of the
`code, identifying usage of portions, during code runtime,
`within the plurality of portions included in the processor 15.
`The application profile data 84 may provide usage informa-
`tion including which portions of the processor 15 are active or
`are idle during execution of the code, how frequently various
`portions are active/idle or accessed/not accessed, and para-
`40 metric settings associated with various portions of the pro(cid:173)
`cessor such as clocking frequency and power supply voltage
`settings for the relevant portions of the processor. The appli(cid:173)
`cation profile data 84 is further defined and described below.
`The code 25 with application profile data 84 may be passed
`45 from the memory 20 to the processor 15 through the system
`bus 88, or any suitable link, for execution by the processor 15.
`For example, the application profile data 84 may be included
`with the code 25 as a header section. Alternatively, the appli(cid:173)
`cation profile data 84 may be associated with the code using
`50 pointers or may be associated with the code by any means
`recognized by one skilled in the art.
`The processor 15 may include a power management con(cid:173)
`troller 80. The power management controller 80 evaluates
`header information of a data stream and varies parametric
`55 settings of portions of the processor 15 to reduce power
`consumption of the processor 15 based on the header infor(cid:173)
`mation. In this example, the data stream includes executable
`code and header information that includes application profile
`data identifying which portions of the processor are exercised
`60 during runtime of the executable code. In an alternative or
`combined embodiment, the device processor 15 may include
`a video decoder, and the data stream includes encoded video.
`In such an example, described further below, the header infor(cid:173)
`mation in the encoded video is used by the power manage-
`65 ment controller to determine which parametric settings of the
`video decoder are to be controlled. The encoded video stream
`need not include additional data, instead data inherent data in
`
`Ex. C, p. 16
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 52-2 Filed 12/21/22 Page 18 of 25
`
`US 7,804,435 B2
`
`5
`encoded streams ( e.g., H.264, VC-1, MPEG or other encoded
`schemes typically include identifiers in the encoded data
`identifying the codec employed to encode the data stream) is
`used to determine how to control the video encoder to save
`power. Additional control data may be included in the stream 5
`if desired, but this can add additional data that may be unde(cid:173)
`sirable in some instances.
`Referring again to FIG. 1, The power management control-
`ler 80 is operative to control power consumption of processor
`portions based on the application profile data 84 and may be 10
`in any suitable form including but limited to executing soft(cid:173)
`ware, dedicated circuitry or any suitable structure. The power
`management controller 80 may be operatively coupled to the
`system clock register 64, the main clock register 66 and the
`general purpose I/O 68. The crystal oscillator 45 generates an 15
`oscillator signal 90 that oscillates at a specific frequency
`based on the crystal 45. The oscillator signal 90 may be used
`by the PLL block 58 to generate a plurality of clock signals
`each of a specified frequency. For example, the system PLL
`60 may generate a system clock (SCLK) 84 that may be used 20
`to synchronize operations in the 2D engine 52 and the 3D
`engine 54. Meanwhile, the memory PLL 62 may generate a
`memory clock (MCLK) 94 that is used to synchronize opera(cid:173)
`tions of the memory controller 56. The system PLL 60 may be
`adapted to generate the SCLK 92 with various frequencies. To 25
`select a specific frequency to change power consumption of
`the device based on the profile information 84, the power
`management controller 80 writes a system clock program
`value (SCLK PROG) 96 into the system clock register 64. The
`system clock register 64 generates a system clock frequency 30
`(SCLK FREQ) 98 that is used as the frequency selection input
`to the system PLL 60. Similarly, the memory PLL 62 may be
`adapted to generate the MCLK 94 with various frequencies.
`To select a specific frequency, the power management con(cid:173)
`troller 80 may write a memory clock program value (MCLK 35
`PROG) 102 into the memory clock register 66. The memory
`clock register 66 generates a memory clock frequency
`(MCLK FREQ) 104 that is used as the frequency selection
`input to the memory PLL 62. As a result, the power manage(cid:173)
`ment controller 80 is operative to vary the clocking frequen- 40
`cies of several portions of the processor 15, such as the 2D
`engine 52, the 3D engine 54, and the memory controller 56 or
`any other desired portions of the processor.
`The power supply voltage input 72 may be operatively
`coupled to the processor 15 to provide a voltage supply for 45
`operating the processor 15. A plurality of such power supply
`voltage inputs 72 may be used to provide a plurality of sepa(cid:173)
`rate adjustable voltage supplies for different portions of the
`processor 15. The power supply voltage input 72 may be
`operatively coupled to the output 73 of the voltage generator 50
`50. The voltage generator 50, in tum may be coupled to and
`controlled by a power supply set signal 106 from processor
`15. For example, the power management controller 80 may
`write a power supply program value 108 to the general pur(cid:173)
`pose I/O 68. The general purpose I/O 68, in turn may generate 55
`the power supply set signal 106. As a result, the power man(cid:173)
`agement controller 80 is operative to vary the power supply
`voltage of the processor 15 or of several portions of the
`processor 15, such as the 2D engine 52, the 3D engine 54, and
`the memory controller 56. While not shown, a similar 60
`approach may be used to allow the power management con(cid:173)
`troller 80 to vary transistor back bias voltages for portions of
`the processor 15 using known transistor back biasing tech(cid:173)
`niques if desired.
`It is known that power consumption in a processor may be 65
`altered by altering parametric values such as clocking fre(cid:173)
`quency, power supply voltage, or transistor back biases. For
`
`6
`example, reducing clocking frequency, reducing the operat(cid:173)
`ing power supply voltage, or increasing the transistor back
`bias voltage are known to reduce power consumption during
`runtime. However, these parametric changes, such as reduc(cid:173)
`ing clock frequency, may also reduce the operating speed of
`the processor or portions thereof. Therefore, to reduce power
`consumption while minimizing the effect on performance, it
`is useful to only affect the operating parameters of portions of
`the processor that are not in use or that are minimally used.
`The power management controller 80 may therefore be
`adapted to use the application profile data 84, where the
`usage, in the running of application 25, of various portions of
`the processor is provided along with the application code 25,
`to selectively adjust the parametric settings of identified por(cid:173)
`tions of the processor 15. For example, if a particular portion
`of the processor, such as the 2D engine 52, is not active or not
`used in the execution of application 25, as indicated by the
`application profile data 84, then the power management con(cid:173)
`troller 80 may simply turn OFF the 2D engine 52 during
`runtime of the application code 25, prior to the runtime of
`application code 25 or during the initialization of application
`25. Alternatively, the power management controller 80 may
`reduce the clocking frequency of SCLK 98 to reduce the
`power consumption of the 2D engine 52. Alternatively, the
`power management controller 80 may reduce the value of the
`power supply voltage 72 for the 2D engine 52 to reduce the
`power consumption of the 2D engine 52. Of course, reducing
`the clock frequency ofSCLK 98 to zero or reducing the power
`supply voltage 72 to zero may effectively reduce power con(cid:173)
`sumption to near zero. If the 2D engine 52 is not used in the
`application code 25, then this approach may be optimal for
`reducing power consumption. Alternatively, if a portion, such
`as the m