Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 1 of 26
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`
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`UNITED STATES DEPARTMENT OF COMMERCE
`United States Patent and Trademark Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alexandria, Virginia 22313-1450
`www.uspto.gov
`
`APPLICATION NO.
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`
`
`
` FILING DATE
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`FIRST NAMED INVENTOR
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`ATTORNEY DOCKET NO.
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`
`
`
`CONFIRMATIONNO.
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`10/459,797
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`06/12/2003
`
`Mark M.Leather
`
`00100.02.0053
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`4148
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`29153
`
`7590
`
`04/05/2011
`
`ADVANCED MICRO DEVICES, INC.
`C/O VEDDERPRICEP.C.
`222 N.LASALLE STREET
`CHICAGO, IL 60601
`
`HSU, JONI
`
`2628
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`MAIL DATE
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`04/05/2011
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`DELIVERY MODE
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`PAPER
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`Please find below and/or attached an Office communication concerning this application or proceeding.
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`The time period for reply, if any, is set in the attached communication.
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`PTOL-90A (Rev. 04/07)
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`Ex. 10, p. 1
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`Ex. 10, p. 1
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 2 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 2 of 26
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`
`
`Commissioner for Patents
`United States Patent and Trademark Office
`P.O. Box 1450
`Alexandria, VA 22313-1450
`www.uspto. gov
`
`BEFORE THE BOARD OF PATENT APPEALS
`AND INTERFERENCES
`
`Application Number: 10/459,797
`Filing Date: June 12, 2003
`Appellant(s): LEATHER ET AL.
`
`Christopher J. Reckamp
`
`For Appellant
`
`Ex. 10, p.2
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`Ex. 10, p. 2
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 3 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 3 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 2
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`EXAMINER'S ANSWER
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`This is in response to the appeal brief filed February 22, 2011 appealing from the Office
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`action mailed April 22, 2010.
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`(1) Real Party in Interest
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`The examiner has no commentonthe statement, or lack of statement, identifying by
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`namethereal party in interest in the brief.
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`(2) Related Appeals and Interferences
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`The examineris not aware of any related appeals, interferences, or judicial proceedings
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`whichwill directly affect or be directly affected by or have a bearing on the Board’s decision in
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`the pending appeal.
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`(3) Status of Claims
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`The followingis a list of claims that are rejected and pending in the application:
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`Claims 1-7, 10-22, 24 and 25 are pending andstand rejected.
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`(4) Status of Amendments After Final
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`The examiner has no commenton the appellant’s statement of the status of amendments
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`after final rejection containedin thebrief.
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`(5) Summary of Claimed Subject Matter
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`The examiner has no commenton the summary of claimed subject matter contained in
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`the brief.
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`(6) Grounds of Rejection to be Reviewed on Appeal
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`The examiner has no commenton the appellant’s statement of the groundsofrejection to
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`be reviewed on appeal. Every groundof rejection set forth in the Office action from which the
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`Ex. 10, p. 3
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`Ex. 10, p. 3
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 4 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 4 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 3
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`appealis taken (as modified by any advisory actions) is being maintained by the examiner except
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`for the groundsofrejection (if any) listed under the subheading “WITHDRAWN
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`REJECTIONS.” New groundsofrejection (if any) are provided under the subheading “NEW
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`GROUNDSOF REJECTION.”
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`(7) Claims Appendix
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`The examiner has no commenton the copy of the appealed claims contained in the
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`Appendix to the appellant’s brief.
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`(8) Evidence Relied Upon
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`6,570,579
`
`6,864,896
`
`5,794,016
`
`6,778,177
`
`5,905,506
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`MACINNIS
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`PEREGO
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`KELLEHER
`
`FURTNER
`
`HAMBURG
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`2003/0164830
`
`KENT
`
`5-2003
`
`3-2005
`
`8-1998
`
`8-2004
`
`5-1999
`
`9-2003
`
`(9) Groundsof Rejection
`
`The following ground(s) of rejection are applicable to the appealed claims:
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`Claim Rejections - 35 USC § 103
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`1.
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`The following is a quotation of 35 U.S.C. 103(a) which formsthe basisfor all
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`obviousnessrejections set forth in this Office action:
`
`(a) A patent may not be obtained thoughthe inventionis not identically disclosed or described as set forth in
`section 102 ofthistitle, if the differences between the subject matter sought to be patented andthe prior art are
`such that the subject matter as a whole would have been obviousat the time the invention was made to a person
`having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the
`manner in which the invention was made.
`
`Ex. 10, p. 4
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`Ex. 10, p. 4
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 5 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 5 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 4
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`2.
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`The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459
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`(1966), that are applied for establishing a background for determining obviousness under 35
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`U.S.C. 103(a) are summarized as follows:
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`FwNS
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`Determining the scope and contents of the prior art.
`Ascertaining the differences between the prior art and the claimsatissue.
`Resolving the level of ordinary skill in the pertinentart.
`Considering objective evidence present in the application indicating obviousness
`or nonobviousness.
`
`3.
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`Claims1-4, 7, 10, 12, 14, and 25 are rejected under 35 U.S.C. 103(a) as being
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`unpatentable over MacInnis (US006570579B 1) in view of Perego (US006864896B2).
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`4,
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`Asper Claim 1, MacInnis teaches a graphics processing circuit, comprising: a graphics
`
`pipeline (58, Fig. 2) on a chip (10); a memory controller (54) on the chip (10), as shown in Fig. 2
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`(col. 4, lines 65-67; col. 5, lines 36-41), in communication with the graphics pipeline (58),
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`operative to transfer pixel data between the pipeline (58) and a memory(col. 6, lines 10-13, 59-
`
`66).
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`However, MacInnis does notteach at least two graphics pipelines on the same chip
`
`operative to process data in a correspondingsetoftiles of a repeating tile pattern corresponding
`
`to screen locations, a respective one of the at least two graphics pipelines operative to process
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`data in a dedicated tile; wherein the repeating tile pattern includes a horizontally and vertically
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`repeating pattern of square regions. However, Perego teaches graphics processing circuit (300,
`
`Fig. 3; col. 3, lines 61-63) having at least 2 graphics pipelines (312) operative to process data in
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`correspondingset oftiles of repeating tile pattern corresponding to screen locations, respective
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`one of at least 2 graphics pipelines operative to process data in dedicatedtile (col. 5, lines 19-27,
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`38-44); and memorycontroller (310, Fig. 3) in communication with at least 2 graphics pipelines
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`Ex. 10, p. 5
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`Ex. 10, p. 5
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 6 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 6 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 5
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`312, operative to transfer pixel data between each of 1“pipeline and am pipeline and shared
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`memories 314 (col. 3, lines 65-67; col. 4, lines 1-10, 48-65). Shared memories 314 are each part
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`of main memory(col. 1, lines 44-54; col. 3, lines 3-6), and so are considered to be one memory
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`that is shared amongtheat least two graphics pipelines. Repeating tile pattern includes
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`horizontally and vertically repeating pattern of regions of square regions, as shownin Fig. 5 (col.
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`5, lines 19-27, 38-44). Perego describes “Improvements in integrated circuit design and
`
`manufacturing technologies allow higher levels of integration, thereby allowing an increasing
`
`number of subsystemsto be integrated into a single device. This increased integration reduces
`
`the total number of components in a system, such as a computer system. As subsystems with
`
`high memory performance requirements (such as graphics subsystems) are combined with the
`
`traditional main memorycontroller, the resulting architecture may provide a single high-
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`performance main memory interface” (col. 1, lines 34-43). Perego showsin Fig. 8 that in one
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`embodiment, a memory module 800 contains two different rendering engines 802 and 810 (Fig.
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`8; col. 6, lines 61-62), and therefore at least two graphics pipelines (802, 810) are on a same
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`memory module 800. From Fig. 8 and from the description in Perego, one of ordinary skill in
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`the art would understand that a memory module is equivalent to a chip. Therefore, Perego
`
`teaches that two graphics pipelines are on the same chip.
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`It would have been obvious to one of ordinary skill in the art at the time of invention by
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`applicant to modify MacInnisto include at least two graphics pipelines on the same chip
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`operative to process data in a correspondingsetoftiles of a repeating tile pattern corresponding
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`to screen locations, a respective one of the at least two graphics pipelines operative to process
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`data in a dedicated tile; wherein the repeating tile pattern includes a horizontally and vertically
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`Ex. 10, p. 6
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`Ex. 10, p. 6
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 7 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 7 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 6
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`repeating pattern of square regions because Perego suggeststhat this parallel processing
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`significantly reduces the processing burden on the memorycontroller/graphics controller (col. 5,
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`lines 38-46).
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`5.
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`Asper Claim 2, MacInnis does not teaches that the square regions comprise a two
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`dimensional partitioning of memory. However, Perego teaches square regions have two
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`dimensional partitioning of memory (col. 5, lines 19-33). This would be obvious for the reasons
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`given in the rejection for Claim 1.
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`6.
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`Asper Claim 3, MacInnis teaches wherein the memoryis a frame buffer (col. 6, line 66-
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`col. 7, line 2).
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`7.
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`Asper Claim 4, MacInnis does not teach that each of the at least two graphics pipelines
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`further includes front end circuitry operative to receive vertex data and generate pixel data
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`corresponding to a primitive to be rendered, and back endcircuitry, coupled to the front end
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`circuitry, operative to receive and process a portion of the pixel data. However, Perego teaches
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`each ofat least 2 graphics pipelines includes front end circuitry (308, Fig. 3) operative to
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`generate pixel data corresponding to primitive to be rendered, and back endcircuitry (312),
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`coupled to front end circuitry, operative to receive and process portion of pixel data (col. 3, line
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`64-col. 4, line 2; col. 5, lines 19-44). In order for front end circuitry (308) to generate pixel data,
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`it must receive vertex data. Perego teaches that the CPU sorts the primitive data according to the
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`spatial region of the rendering surface (e.g., the x and y coordinates) covered by that primitive,
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`and the rendering surface is divided into multiple rectangular regions of pixels (col. 5, lines 19-
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`27). One of ordinary skill in the art would understand that data pertaining to the x and y
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`coordinates covered by the primitive would include vertex data. The main memoryis used to
`
`Ex. 10, p. 7
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`Ex. 10, p. 7
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 8 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 8 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 7
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`store data which are referenced during the execution of the programs(col. 1, lines 18-21).
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`Therefore, the CPU is operative to receive vertex data (data pertaining to the x and y coordinates
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`covered by the primitive) from the main memory andgenerate pixel data corresponding to a
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`primitive to be rendered (col. 5, lines 19-27; col. 1, lines 18-21). Perego teaches that rendering
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`engine 312 is coupled to the CPU, and is operative to receive and process a rectangular region of
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`pixel data (col. 3, line 64-col. 4, line 2; col. 5, lines 19-44). Since the CPU is coupled to the
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`rendering engine 312, and the CPU and the rendering engine 312 both perform graphics
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`processing, and, the CPU performs the operations of the front end circuitry, and the rendering
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`engine 312 performsthe operations of the back end circuitry, the CPU and the rendering engine
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`312 are considered to be part of a graphics pipeline, and the CPUis considered to be the front
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`end circuitry included in the graphics pipeline. This would be obviousfor the reasons given in
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`the rejection for Claim 1.
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`8.
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`Asper Claim 7, MacInnis does not teach that the at least two graphics pipelines
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`separately receive the pixel data from the front end circuitry. However, Perego teachesat least
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`two graphics pipelines (312) separately receive pixel data from front end circuitry (308) (col. 3,
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`line 64-col. 4, line 2; col. 5, lines 19-44). This would be obvious for the reasons given in the
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`rejection for Claim 1.
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`
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`9. Asper Claim 10, MacInnis doesnotteachthatafirst of the at least two graphics pipelines
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`processes the pixel data only in the first set oftiles in the repeating tile pattern. However, Perego
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`teachesfirst of at least two graphics pipelines (first rendering engine of 312, Fig. 3) processes
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`pixel data only infirst set oftiles (tiles labeled “REO” in Fig. 5) in repeatingtile pattern (col. 5,
`
`lines 23-44). This would be obviousfor the reasons given in the rejection for Claim 1.
`
`Ex. 10, p. 8
`
`Ex. 10, p. 8
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 9 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 9 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 8
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`10.
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`Asper Claim 12, MacInnis doesnotteach that a second ofthe at least two graphics
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`pipelines processes the data only in a secondsetoftiles in the repeating tile pattern. However,
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`Perego teaches secondofat least two graphics pipelines (second rendering engine of 312, Fig. 3)
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`processespixel data only in secondset oftiles (tiles labeled “RE1” in Fig. 5) in repeatingtile
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`pattern (col. 5, lines 23-44). This would be obviousfor the reasons given in the rejection for
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`Claim 1.
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`11.
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`Asper Claim 14, Claim 14 is similar to Claims 4 and 10, except that Claim 14 is for a
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`third and fourth graphics pipeline. Perego teaches four graphicspipelines(col. 5, lines 41-44).
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`So Claim 14 is rejected under the samerationale as Claims 4 and 10.
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`12.
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`Asper Claim 25, Claim 25 is similar in scope to Claim 1, and therefore is rejected under
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`the samerationale.
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`13.
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`Claims 5, 18, and 24 are rejected under 35 U.S.C. 103(a) as being unpatentable over
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`MacInnis (US006570579B 1) in view of Perego (US006864896B2), further in view of Kelleher
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`(US005794016A).
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`14.
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`Asper Claim 5, MacInnis and Perego are relied on for teachings for Claim 4.
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`But, MacInnis and Perego do not explicitly teach at each of 2 graphics pipelines includes
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`scan converter, coupled to back end circuitry, operative to determine portion of pixel data to be
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`processed by back endcircuitry. But, Kelleher teaches each ofat least 2 graphics pipelines (20A,
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`20B, Fig. 3; col. 3, lines 22-23; col. 4, lines 9-14) includes scan converter (update stage, Fig. 7),
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`coupled to back end circuitry, operative to determine portion of pixel data to be processed by
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`back end circuitry (col. 8, lines 52-61; col. 9, lines 1-23; col. 6, lines 26-28).
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`Ex. 10, p. 9
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`Ex. 10, p. 9
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 10 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 10 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 9
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`It would have been obvious to one of ordinary skill in the art at the time of invention by
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`applicant to modify MacInnis and Peregoso at each of at least two graphics pipelines includes a
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`scan converter, coupled to the back end circuitry, operative to determine the portion of the pixel
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`data to be processed by the back end circuitry because Kelleher suggests scan converters are
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`neededin order to define image data as array of pixels by calculating pixel addresses(col. 9,
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`lines 1-23), as is well-knownin theart.
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`15.
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`Asper Claim 18, MacInnis doesnotteach a bridge operable to transmit vertex data to
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`each of the 1“, 2"’, 3and 4"" graphicspipelines. But, Kelleher teachesa bridge (38, Fig. 3)
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`operative to transmit vertex data to each of the 1* (20A), 2" (20B), 3" (20C) and 4" (20N)
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`graphics pipelines (col. 3, lines 22-23; col. 4, lines 9-14; col. 8, lines 56-65; col. 3, lines 46-50).
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`It would have been obvious to one of ordinary skill in the art at the time of invention by
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`applicant to modify MacInnisto include a bridge operable to transmit vertex data to each of the
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`first, second, third and fourth graphics pipelines because Kelleher suggests being able to convert
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`the vertex data to pixel data in parallel, which increases the efficiency of the graphics system
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`(col, 2, lines 31-35; col. 8, lines 56-65; col. 9, lines 1-23).
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`16.
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`Asper Claim 24, MacInnis teaches a graphics processing circuit, comprising: front end
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`circuitry (90, Fig. 4) operative to generate pixel data in responseto primitive data for a primitive
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`to be rendered(col. 8, lines 49-59); back end circuitry (98), coupled to the front end circuitry
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`(90) (col. 9, lines 15-34), operative to process the pixel data in responseto position coordinates
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`(col. 9, lines 35-54). The front end circuitry (90) and the back endcircuitry (98) are in the
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`graphics display pipeline (80) (col. 7, lines 55-63), and the graphics display pipeline (80) is
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`equivalent to display engine (58, Fig. 2), which is on graphics chip (10)(col. 4, lines 65-67; col.
`
`Ex. 10, p. 10
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`Ex. 10, p. 10
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 11 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 11 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 10
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`5, lines 36-39). A memory controller (54) is also on graphics chip (10) (col. 4, lines 65-67; col.
`
`5, lines 36-39). Therefore, the front end circuitry (90), the back end circuitry (98), and the
`
`memory controller (54) are on the chip (10). The memorycontroller (54) is coupled to the
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`display engine (58) and is operative to transmit and receive the processed pixel data (col. 6, lines
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`10-13, 59-67; col. 7, lines 1-2). Since the display engine (58) is equivalent to the graphics
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`display pipeline (80) which contains the back endcircuitry (98) (col. 6, lines 59-67; col. 7, lines
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`55-63), the memory controller (54) is coupled to the back end circuitry (98) and is operative to
`
`transmit and receive the processed pixel data.
`
`However, MacInnis does not teach first back end circuitry operative to process a first
`
`portion of the pixel data; set of tiles of a repeating tile pattern are to be processed bythefirst
`
`back end circuitry, the repeating tile pattern including a horizontally and vertically repeating
`
`pattern of square regions; second back endcircuitry operative to process a secondportion of the
`
`pixel data;set of tiles of the repeating tile pattern are to be processed by the second back end
`
`circuitry. However, Perego teaches graphics processing circuit (300, Fig. 3; col. 3, lines 61-63),
`
`having front end circuitry (308) operative to generate pixel data in responseto primitive data for
`
`primitive to be rendered (col. 5, lines. 19-23); 1“ back endcircuitry (1“ rendering engine 312),
`
`coupledto front end circuitry 308, operative to process 1*portion ofpixel data (labeled “REO”in
`
`Fig. 5) in response to position coordinates; set of tiles of repeating tile pattern are to be processed
`
`by 1*back end circuitry, repeating tile pattern including horizontally and vertically repeating
`
`pattern of square regions, as shownin Fig. 5; 2™ back end circuitry (second rendering engine
`
`312), coupled to front end circuitry 308, operative to process an portion of pixel data (labeled
`
`“REI” in Fig. 5) in response to position coordinates; set of tiles of repeating tile pattern are to be
`
`Ex. 10, p. 11
`
`Ex. 10, p. 11
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 12 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 12 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 11
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`processed by 2"! back end circuitry (col. 3, line 63-col. 4, line 2; col. 5, lines 19-44); and
`
`memory controller (310), coupled to 1" and 2™ back end circuitry (312) operative to transmit and
`
`receive processed pixel data (col. 3, lines 65-67; col. 4, lines 1-53; col. 5, lines 32-44). Perego
`
`describes “Improvements in integrated circuit design and manufacturing technologies allow
`
`higher levels of integration, thereby allowing an increasing number of subsystemsto be
`
`integrated into a single device. This increased integration reduces the total number of
`
`components in a system, such as a computer system. As subsystems with high memory
`
`performance requirements (such as graphics subsystems) are combined with the traditional main
`
`memory controller, the resulting architecture may provide a single high-performance main
`
`memory interface” (col. 1, lines 34-43). Perego showsin Fig. 8 that in one embodiment, a
`
`memory module 800 contains two different rendering engines 802 and 810 (Fig. 8; col. 6, lines
`
`61-62), and therefore at least two graphics pipelines (802, 810) are on a same memory module
`
`800. From Fig. 8 and from the description in Perego, one of ordinary skill in the art would
`
`understand that a memory module is equivalent to a chip. Therefore, Perego teaches that two
`
`graphics pipelines are on the same chip, and so the first back end circuitry and second back end
`
`circuitry are on the same chip. Since MacInnisteachesthat the front end circuitry, the back end
`
`circuitry and the memory controller are on the same chip, this teaching from Perego can be
`
`implemented into the device of MacInnis so that the front end circuitry sends pixel data to both
`
`the first back end circuitry and the second back endcircuitry, and the front end circuitry, the first
`
`back end circuitry, the second back end circuitry, and the memory controller are on the same
`
`chip. This would be obviousfor the reasons given in the rejection for Claim 1.
`
`Ex. 10, p. 12
`
`Ex. 10, p. 12
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 13 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 13 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 12
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`However, MacInnis and Perego do not explicitly teach first scan converter and second
`
`scan converter. However, Kelleher teaches first scan converter, coupled between front end
`
`circuitry (14, Fig. 3) and first back end circuitry (update stage, Fig. 7 in 20A, Fig. 3), operative to
`
`determine whichsetoftiles of repeating tile pattern are to be processed byfirst back end
`
`circuitry (col. 3, lines 22-23; col. 8, line 33-col. 9, line 23), and operative to provide position
`
`coordinates to first back end circuitry in responseto pixel data (col. 4, lines 60-62; col. 8, lines
`
`52-65; col. 6, lines 36-38); second scan converter, coupled between front end circuitry and
`
`second back end circuitry (update stage, Fig. 7 in 20B, Fig. 3), operative to determine whichset
`
`of tiles of repeating tile pattern are to be processed by second back endcircuitry, and operative to
`
`provide position coordinates to second back end circuitry in response to pixel data (col. 3, lines
`
`22-23; col. 8, line 33-col. 9, line 23; col. 4, lines 60-62; col. 8, lines 52-65; col. 6, lines 36-38).
`
`Therefore, by implementthis teaching into the device of Perego, front end circuitry, first back
`
`end circuitry, and first scan converter of Perego-Kelleher combination make up one graphics
`
`pipeline, and front end circuitry, second back endcircuitry, and second scan converter of Perego-
`
`Kelleher combination make up another graphics pipeline. Since Perego teaches graphics
`
`pipelines are on the same chip, the teaching from Kelleher can be applied to Perego so that the
`
`first scan converter and the second scan converter are also on the same chip. This would be
`
`obviousfor reasons given in the rejection for Claim 5.
`
`17.
`
`Claims6 and 17 are rejected under 35 U.S.C. 103(a) as being unpatentable over MacInnis
`
`(US006570579B 1) in view of Perego (US006864896B2), further in view of Furtner
`
`(US006778177B1).
`
`Ex. 10, p. 13
`
`Ex. 10, p. 13
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 14 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 14 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
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`Page 13
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`18.
`
`Asper Claim 6, MacInnis and Perego are relied upon for the teachings as discussed
`
`aboverelative to Claim 1.
`
`However, MacInnis and Perego do not expressly teach that each tile of the set of tiles
`
`further comprises a 16x16 pixel array. However, Furtner teaches that eachtile of the set oftiles
`
`further comprises a 16x16 pixel array (col. 11, lines 45-48, 64-65).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify MacInnis and Peregoso eachtile ofset of tiles further has 16x16 pixel array
`
`because Furtner suggests depending on numberof parallel image-rendering pipelines and
`
`depending on memory organization, optimum tile size and shape can be selected (col. 11, lines
`
`45-48, 64-65), and so it would be obvious to modify tile size to be 16x16 pixels if that would be
`
`optimum tile size for particular numberofparallel image-rendering pipelines and particular
`
`memory organization.
`
`19,
`
`Asper Claim 17, MacInnis doesnot teach 3" and 4" graphics pipelines are on separate
`
`chips. However, Furtner teaches this limitation (col. 6, lines 47-51).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify MacInnis so pipelines are on separate chips because Furtner teaches this
`
`makes system more configurable by being able to easily add more graphics pipelines to increase
`
`performance(col. 6, lines 29-30, 42-51).
`
`20.
`
`Claims 11, 13, 15, and 16 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`MacInnis (US006570579B 1) in view of Perego (US006864896B2), further in view of Kelleher
`
`(US005794016A), further in view of Hamburg (US005905506A).
`
`MacInnis and Perego are relied upon for teachings relative to Claim 10.
`
`Ex. 10, p. 14
`
`Ex. 10, p. 14
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 15 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 15 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
`
`Page 14
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`However, MacInnis and Perego do not explicitly teach scan converter. However,
`
`Kelleher teachesfirst of the at least two graphics pipelines (20A,Fig. 3; col. 3, lines 22-23; col.
`
`4, lines 9-14) further includes scan converter (84, Fig. 7), coupled to front end circuitry (80, 82)
`
`and back endcircuitry (col. 8, line 52-col. 9, line 23). Scan converter determines which groups of
`
`blocks 52 within graphics memory 22 are allocated to and controlled by graphics pipelines (col.
`
`8, lines 52-65; col. 6, lines 26-28). Graphics memoryis partitioned into plurality of pixel blocks
`
`that are tiled in x-and y-direction of graphics memory (col. 4, lines 60-62). So, scan converteris
`
`inherently operative to provide memory addressesor position coordinates of pixels within first
`
`set of tiles to be processed by back end circuitry. This would be obviousfor the reasons given in
`
`the rejection for Claim 5.
`
`But, MacInnis, Perego, and Kelleher do not expressly teach using tile identification data
`
`to indicate whichtiles are to be processed. But, Hamburg teachespixel identification line for
`
`receiving tile identification data indicating whichtiles are to be processed (col. 5, lines 35-52).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify MacInnis, Perego, and Kelleher to include usingtile identification data to
`
`indicate whichtiles are to be processed because Hamburg suggests advantage ofusingtile
`
`identification data to easily track storage locations oftile pixel data and being able to easily
`
`retrieve data for particular imagetile (col. 1, lines 46-54).
`
`21.
`
`Claim 19 is rejected under 35 U.S.C. 103(a) as being unpatentable over MacInnis
`
`(US006570579B 1) in view of Perego (US006864896B2), further in view of Furtner
`
`(US006778177B 1), further in view of Kent (US 20030164830A1).
`
`Ex. 10, p. 15
`
`Ex. 10, p. 15
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 16 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 16 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
`
`Page 15
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`MacInnis, Perego, and Furtner are relied upon for the teachings as discussed above
`
`relative to Claim 17. MacInnis teaches data includes polygon (col. 58, lines 50-54). Furtner
`
`teaches third and fourth graphics pipelines are on separate chips (col. 6, lines 47-51), as
`
`discussed for Claim 17.
`
`But, MacInnis, Perego, and Furtner do not teach creating bounding box around polygon
`
`and each corner of bounding box is checked against supertile that belongs to each separate chip
`
`and if bounding box does not overlap any of supertiles associated with separate chip, then
`
`processing circuit rejects whole polygon and processes next one. But, Kent teaches graphics
`
`pipeline [0006] calculates bounding box ofprimitive andtesting this against VisRect. If
`
`bounding box of primitive is contained in other P10’s supertile the primitive is discarded at this
`
`stage [0129]. Primitive can be polygon [0088]. Method usedis to calculate distance from each
`
`subpixel sample point in point’s bounding box to point’s center and comparethis to point’s
`
`radius. Subpixel sample points with distance greater than radius do not contribute to pixel’s
`
`coverage. Cost of this is kept low by only allowing small radius points hence distance calculation
`
`is a small multiply and by taking a cycle per subpixel sample per pixel within bounding box
`
`[0144]. Since method calculates distance from each subpixel sample point in point’s bounding
`
`box, this must include all corners of bounding box. So, Kent teaches data includes polygon and
`
`graphics pipeline creates bounding box around polygon and wherein each corner of bounding
`
`box is checked against supertile that belongs to graphics pipeline and if bounding box does not
`
`overlap any of supertiles, then processing circuit rejects whole polygon and processes next one.
`
`Ex. 10, p. 16
`
`Ex. 10, p. 16
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 17 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 17 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 2628
`
`Page 16
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`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify MacInnis, Perego, and Furtner to include bounding box as because Kent
`
`suggests processing supertiles one at a time in order to hide page break costs [0129, 0051].
`
`22.
`
`Claims 20-22 are rejected under 35 U.S.C. 103(a) as being unpatentable over Perego
`
`(US006864896B2).
`
`23.
`
`Asper Claim 20, Perego teaches graphics processing method, comprising generating
`
`pixel data (col. 5, lines 19-25), which is inherently generated in response to received vertex data.
`
`Perego teaches a shared front end (308, Fig. 3) that passes the pixel data to both of the two
`
`graphics pipelines (first rendering engine 312 and second rendering engine 312) (col. 3, line 63-
`
`col. 4, line 2; col. 5, lines 19-44), similarly as what is described in the instant specification, and
`
`so Perego teaches passing the same pixel data to both of the two graphics pipelines. Perego
`
`shows in Fig. 8 that in one embodiment, a memory module 800 contains two different rendering
`
`engines 802 and 810 (Fig. 8; col. 6, lines 61-62), and therefore at least two graphics pipelines
`
`(802, 810) are on a same memory module 800. From Fig. 8 and from the description in Perego,
`
`one of ordinary skill in the art would understand that a memory module is equivalent to a chip.
`
`Therefore, Perego teaches that two graphics pipelines are on the same chip. Perego teaches
`
`determining pixels within set of tiles of repeating tile pattern corresponding to screen locations to
`
`be processed by corresponding oneofthe at least two graphics pipelines (312, Fig. 3) in response
`
`to pixel data, repeating tile pattern including horizontally and vertically repeating pattern of
`
`square regions, as shownin Fig. 5; performing pixel operations on pixels within determinedset
`
`of tiles by corresponding oneofat least two graphics pipelines (col. 5, lines 19-44); and
`
`transmitting processed pixels to memory controller 310, at least 2 graphics pipelines share
`
`Ex. 10, p. 17
`
`Ex. 10, p. 17
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 18 of 26
`Case 6:22-cv-00466-ADA-DTG Document 50-10 Filed 12/19/22 Page 18 of 26
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`Application/Control Number: 10/459,797
`Art Unit: 262