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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 1 of 26
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`
`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`
`
`Advanced Silicon Technologies LLC,
`
`
`Plaintiff,
`
`v.
`
`NXP Semiconductors N.V.,
`NXP B.V., and
`NXP USA, Inc.,
`
`
`Defendants.
`
`
`
`Case No. 6:22-cv-00466-ADA-DTG
`
`
`
`
`Jury Trial Demanded
`
`AST's Responsive Claim Construction Brief
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`

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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 2 of 26
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`Table of Contents
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`Table of Authorities ........................................................................................................................ ii 
`1. 
`Introduction ......................................................................................................................... 1 
`2. 
`The Asserted Patents ........................................................................................................... 1 
`2.1.  U.S. Patent No. 7,804,435....................................................................................... 1 
`2.2.  U.S. Patent No. 8,933,945....................................................................................... 2 
`Claim Construction Analysis .............................................................................................. 5 
`"A method for reducing power consumption for a video
`3.1. 
`decoder comprising" ('435 Patent, Claim 26) ........................................................ 5 
`3.1.1.  The Preamble Has No Essential Steps and the Claim
`Lives Without It .......................................................................................... 5 
`3.1.2.  The Preamble Merely Recites the Benefit of the
`Claimed Method.......................................................................................... 6 
`3.1.3.  NXP's Proposal Would Create Confusion about Claim Scope ................... 7 
`"Graphics Pipeline" ('945 Patent, Claims 1, 4, 12, and 21) .................................... 7 
`3.2.1.  NXP's Construction Improperly Reads Out Software Elements................. 8 
`3.2.2.  NXP's Addition of "Processes Graphics Data" Only Risks
`Confusion .................................................................................................... 9 
`"Graphics Pipelines Operative to Process Data in a Dedicated Tile"
`('945 Patent, Claims 1 and 21) .............................................................................. 10 
`3.3.1.  NXP's Proposed Construction Goes Against the Specification ................ 10 
`3.3.2.  AST's Arguments in a 2016 POPR Accord with the Plain Meaning ........ 11 
`"A Memory Controller . . . Operative to Transfer Pixel Data Between Each
`of a First Pipeline and a Second Pipeline and a Memory Shared Among
`the at Least Two Graphics Pipelines" ('945 Patent, Claims 1 and 21).................. 12 
`3.4.1.  The Claim Language Follows A Well Understood Formulation .............. 12 
`3.4.2.  The Specification Confirms the Plain Meaning of the
`Claim Language ........................................................................................ 14 
`3.4.3.  The File History is at Best Ambiguous and Thus Cannot
`Override the Plain Meaning in the Claims and Specification ................... 15 
`3.4.4.  NXP Offers Conflicting Claim Construction Positions ............................ 17 
`"NxM Number of Pixels" ('945 Patent, Claim 21) ............................................... 17 
`3.5.1.  No Disclaimer of Square Shapes Occurred .............................................. 18 
`3.5.2.  Even without Acquiescence, the Examiner's Views Bar Disclaimer ........ 20 
`3.5.3.  Prior Legal Briefs Cannot Support Prosecution History Disclaimer ........ 20 
`Conclusion ........................................................................................................................ 20
`
`3. 
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`4. 
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`3.2. 
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`3.3. 
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`3.4. 
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`3.5. 
`
`—i—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 3 of 26
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`Table of Authorities
`
`Cases 
`Am. Piledriving Equip., Inc. v. Geoquip, Inc.,
`637 F.3d 1324 (Fed. Cir. 2011) ................................................................................................. 19
`Aspex Eyewear, Inc. v. Marchon Eyewear, Inc.,
`672 F.3d 1335 (Fed. Cir. 2012) ................................................................................................... 5
`Bates v. Coe,
`98 U.S. 31 (1878) ...................................................................................................................... 15
`Bristol-Myers Squibb Co. v. Immunex Corp.,
`86 F. Supp. 2d 447 (D.N.J. 2000), aff'd
`Bristol-Myers Squibb Co. v. Ben Venue Labs., Inc.,
`246 F.3d 1368 (Fed. Cir. 2001) ................................................................................................... 6
`Catalina Mktg. Int'l v. Coolsavings.com, Inc.,
`289 F.3d 801 (Fed. Cir. 2002) ................................................................................................. 5, 6
`Cochlear Bone Anchored Sols. AB v. Oticon Med.,
`958 F.3d 1348 (Fed. Cir. 2020) ................................................................................................... 5
`Droplets, Inc. v. YAHOO! Inc.,
`No. 12-cv-03733-JST,
`2021 U.S. Dist. LEXIS 259660 (N.D. Cal. July 2, 2021) ......................................................... 20
`Ecolab, Inc. v. FMC Corp.,
`569 F.3d 1335 (Fed. Cir. 2009) ........................................................................................... 18, 19
`Galderma Labs., L.P. v. Ameanl Pharms. LLC,
`806 F. App'x 1007 (Fed. Cir. 2020) .................................................................................... 19, 20
`Genuine Enabling Tech. LLC v. Nintendo Co.,
`29 F.4th 1365 (Fed. Cir. 2022) ............................................................................................ 18, 20
`ICU Med., Inc. v. Alaris Med. Sys.,
`558 F.3d 1368 (Fed. Cir. 2009) ................................................................................................. 14
`Immunex Corp. v. Sanofi-Aventis U.S. LLC,
`977 F.3d 1212 (Fed. Cir. 2020) ................................................................................................. 12
`Infinity Computer Prods. v. Oki Data Ams., Inc.,
`987 F.3d 1053 (Fed. Cir. 2021) ................................................................................................. 17
`Karsten Mfg. Corp. v. Cleveland Golf Co.,
`242 F.3d 1376 (Fed. Cir. 2001) ................................................................................................. 15
`Omega Eng'g, Inc. v. Raytek Corp.,
`334 F.3d 1314 (Fed. Cir. 2003) ................................................................................................. 20
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) ........................................................................................... 14, 15
`
`—ii—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 4 of 26
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`Seachange Int'l, Inc. v. C-COR Inc.,
`413 F.3d 1361 (Fed. Cir. 2005) ................................................................................................. 19
`Smith v. Snow,
`294 U.S. 1 (1935) ...................................................................................................................... 15
`Springs Window Fashions LP v. Novo Indus., L.P.,
`323 F.3d 989 (Fed. Cir. 2003) ................................................................................................... 19
`Summit 6, LLC v. Samsung Elecs. Co.,
`802 F.3d 1283 (Fed. Cir. 2015) ................................................................................................... 5
`Symantec Corp. v. Computer Assocs. Int'l, Inc.,
`522 F.3d 1279 (Fed. Cir. 2008) ................................................................................................... 5
`Teleflex, Inc. v. Ficosa N. Am. Corp.,
`299 F.3d 1313 (Fed. Cir. 2002) ................................................................................................. 14
`Zoho Corp. v. Sentius Int'l, LLC,
`No. 4:19-cv-0001-YGR,
`2020 U.S. Dist. LEXIS 103314 (N.D. Cal. June 12, 2020) ...................................................... 19
`
`
`
`
`
`
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`
`
`—iii—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 5 of 26
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`1.
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`Introduction
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`The asserted patents reflect two of AMD's seminal advancements in graphics and video
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`processing technology in the early-to-mid 2000s. The asserted claims employ uncomplicated
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`language to teach skilled artisans how to implement the disclosed inventions in view of the patents'
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`robust specifications. NXP's opening brief injects ambiguity and complexity into the disputed
`
`terms by reading in additional limitations, misstating the intrinsic evidence, and making mountains
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`out of molehills from preliminary attorney argument in non-instituted IPR proceedings governed
`
`by the now obsolete "broadest reasonable interpretation" standard. The Court should decline NXP's
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`invitation to confuse the jury and instead afford these terms their plain and ordinary meaning.
`
`2.
`
`The Asserted Patents
`
`2.1. U.S. Patent No. 7,804,435
`
`The '435 patent disclosed new technology for reducing power consumption in video
`
`
`
`
`decoders. Prior art battery-powered devices with low-power modes could only access the mode
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`manually through a user switching the device into low-power mode or automatically based on a
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`triggering event, like battery capacity dropping below a certain threshold. ’435 Patent at 1:33-45.
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`But the inventors recognized that the reactive nature of these techniques allowed for significant
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`and wasteful power consumption before the activation of low-power mode. Id. at 1:46-50.
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`
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`The '435 patent teaches systems and methods for conserving power before significant
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`battery discharge occurs, without user intervention. Id. at 2:39-41. The patent teaches varying
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`power consumption "in portions of the video decoder in response to encoding characteristics from
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`an input data stream to minimize power consumption while achieving required performance." Id.
`
`at 2:41-44. A POSITA would have recognized the power consumed by a portion of the video
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`decoder may increase to attain required performance, but the patent’s methods would reduce
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`overall power use by reducing power selectively based on the nature of the input data.
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 6 of 26
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`2.2. U.S. Patent No. 8,933,945
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`The '945 patent disclosed new technology for parallel processing of an image in a graphics
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`processor. The inventors saw inefficiencies in the prior art grounded in differences between how
`
`computer processors and display screens treated graphics data. In computer graphics, a single
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`image in a sequence of pictures is known as a frame—e.g., one second of video may contain 24 or
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`30 frames—and each frame may relate to "primitives," or shapes—often triangles—that make up
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`the frame. '945 Patent at 1:56-60. Display screens, on the other hand, use pixels to display the
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`frame. CRT monitors, for instance, include a plurality of scan lines comprised of a series of pixels.
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`Id. at 1:34-36. "When appearance attributes (e.g., color, brightness, texture) are applied to the
`
`pixels, and object or scene is presented on the display device." Id. at 1:36-38. But prior art displays
`
`could not use the primitives relied on by graphics processors. They instead "receive[d] the vertex
`
`data and generate[d] pixel data including the appearance attributes." Id. at 1:38-41.
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`
`
`The '945 patent discloses a graphics processing circuit that can convert vertex data for a
`
`primitive to pixel data. Figure 2 of the patent depicts an exemplary graphics processing circuit 34:
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`—2—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 7 of 26
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`Here, the graphics processing circuit 34 receives graphics data 31. Id. at 3:57-59. The graphics
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`data 31 may be vertex data of a primitive (e.g., a triangle). Id. The graphics processing circuit 34
`
`then uses two or more graphics pipelines to process graphics data. For example, Figure 2 shows a
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`first graphics pipeline 101 and second graphics pipeline 102 that operate independently of each
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`other. Id. at 4:7-13. These pipelines may include common front end circuitry 35, separate scan
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`converters 37 and 40, and separate back end circuitry 39 and 42. Id. at 4:7-9, 14-15.
`
`
`
`The '945 patent further discloses that each of the first graphics pipeline 101 and the second
`
`graphics pipeline 102 may be responsible for processing a certain tile or set of tiles. Id. at 4:51-52.
`
`Figure 4 illustrates this concept, showing a repeating tile pattern where the tiles may be "the
`
`responsibility of and processed by a corresponding one of the graphics pipelines." Id. at 6:15-20.
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`
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`For example, a first graphics pipeline may be responsible for processing the "A_" tiles, while a
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`second graphics pipeline may be responsible for processing the "B_" tiles.
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`
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`In this embodiment, the front end circuitry receives the primitive data 31—e.g., vertex
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`data—and generates pixel data 36 "to be further processed by the back end circuitry 39 and 42
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`—3—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 8 of 26
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`respectively." Id. at 4:35-39. The same pixel data 36 may be transmitted to the scan converters 37
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`and 40 of the first and second pipelines. Id. at 4:16-22, 42-44. The scan converters 37 and 40 then
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`identify the pixels of the primitive that are to be processed by the corresponding pipeline. Id. at
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`4:45-52. "The particular tile(s) that the back end circuity 39 is responsible for is determined based
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`on the tile identification data present on the pixel identification line 38 of the scan converter 37."
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`Id. at 52-55. In Figure 3, for example, the scan converter 37 of the first graphics pipeline would
`
`identify the pixels associated with areas 81 and 82 of the primitive 80 because those pixels are
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`within the "A_" tiles for which the first graphics pipeline is responsible. Id. at 4:45-65. And the
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`scan converter 40 of the second pipeline would identify the pixels associated with areas 83 and 84
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`because those are within the "B_" tiles for which the second pipeline is responsible. Id. at 5:8-27.
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`
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`The back end circuitry 39 and 42 then performs pixel appearance attribute operations on
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`the pixels identified by the scan converters 37 and 40, such as "pixel appearance operations (e.g.,
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`color, texture blending, z-buffering)" on the pixels located in the areas 81 and 82 located on tiles
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`—4—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 9 of 26
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`72 and 75. Id. at 4:66-5:4. The processed pixel data 43 and 44 travels to graphics memory 48 via
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`memory controller 46 for storage until the frame is displayed on the monitor. Id. at 5:4-7, 33-36.
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`3.
`
`Claim Construction Analysis
`
`3.1.
`
`"A method for reducing power consumption for a video decoder comprising"
`('435 Patent, Claim 26)
`
`NXP gives no reason to depart from the presumption that a preamble does not limit claim
`
`
`
`scope. The preamble here describes the benefit of the claimed method, which is not limiting.
`
`Term
`
`Claim(s)
`
`Plaintiff's Proposal Defendants' Proposal
`
`"A method for reducing
`power consumption for a
`video decoder comprising"
`
`
`'435 patent,
`Claim 26
`
`Non-limiting
`
`Limiting
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`3.1.1. The Preamble Has No Essential Steps and the Claim Lives Without It
`
`"[A]s a general rule preamble language is not treated as limiting." E.g., Cochlear Bone
`
`
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`Anchored Sols. AB v. Oticon Med., 958 F.3d 1348, 1354 (Fed. Cir. 2020) (quoting Aspex Eyewear,
`
`Inc. v. Marchon Eyewear, Inc., 672 F.3d 1335, 1347 (Fed. Cir. 2012)); see also Summit 6, LLC v.
`
`Samsung Elecs. Co., 802 F.3d 1283, 1292 (Fed. Cir. 2015). Deviation from this general rule may
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`only occur if the preamble "recites essential structure or steps, or if it is necessary to give life,
`
`meaning, and vitality to a claim." E.g., Catalina Mktg. Int'l v. Coolsavings.com, Inc., 289 F.3d
`
`801, 808 (Fed. Cir. 2002). For example, a preamble may prove limiting if the patentee relied on it
`
`during prosecution to distinguish prior art or to supply needed antecedent basis for the body of the
`
`claim. See Symantec Corp. v. Computer Assocs. Int'l, Inc., 522 F.3d 1279, 1288 (Fed. Cir. 2008).
`
`This preamble meets none of these exceptional criteria. The preamble of claim 26 does not
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`recite essential steps of the claimed method and is not otherwise necessary to give meaning to the
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`claim. Claim 26 recites a complete method without reference to the preamble. The three steps
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`recited in claim 26 correspond to the three steps illustrated in Figure 9 of the '435 patent. Those
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`—5—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 10 of 26
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`steps describe a complete method. See Ex. 1. The applicants did not rely on the preamble to
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`distinguish prior art during prosecution, nor did they cite the preamble to supply antecedent basis.
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`
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`3.1.2. The Preamble Merely Recites the Benefit of the Claimed Method
`
`Claim 26 "defines a structurally complete invention in the claim body and uses the
`
`preamble only to state a purpose or intended use for the invention." Catalina, 289 F.3d at 808. The
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`preamble frames "reducing power for a video decoder" as a non-limiting "shorthand encapsulation
`
`of the advantages of the invention." E.g., Bristol-Myers Squibb Co. v. Immunex Corp., 86 F. Supp.
`
`2d 447, 451 (D.N.J. 2000), aff'd Bristol-Myers Squibb Co. v. Ben Venue Labs., Inc., 246 F.3d 1368,
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`1375–76 (Fed. Cir. 2001). "[T]o achieve the beneficial results promised in the preamble, a
`
`practitioner need only follow the method steps recited in the body of the claim." Id.
`
`The inventors of the '435 patent viewed prior art systems with low-power modes as
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`"reactive rather than proactive," suggesting that "significant battery may be consumed prior to
`
`triggering" the low-power mode. ’435 Patent at 1:45-48. The '435 patent describes systems and
`
`methods where "[p]ower is proactively and automatically conserved prior to significant
`
`discharge," which "minimize[s] power consumption while achieving required performance." Id. at
`
`2:43-45. A POSITA would understand that the method of claim 26 reduces overall power
`
`consumption compared to prior art devices, even though the claimed methods and systems
`
`dynamically raise and lower consumption to achieve performance targets.
`
`For example, the '435 patent describes increasing power by increasing the clock frequency
`
`and supply voltage for the decoder "if there are multiple input streams being received" and if clock
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`frequency and supply voltage "is not already at a desired level." Id. at 14:8-12. A POSITA would
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`understand this allows the decoder to operate at a lower power state until the increase is needed,
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`rather than operating at a higher state until a triggering event activates a low-power mode. Ex. 2
`
`("Hart Decl."), ¶ 15. The described power increase strategy reduces power consumption overall,
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`—6—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 11 of 26
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`even if the claimed method sometimes increases power, confirming the preamble speaks to the
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`benefit of the method and not its implementation.
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`
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`3.1.3. NXP's Proposal Would Create Confusion about Claim Scope
`
`NXP proposes that the preamble be considered a limitation of the claim. If it were a
`
`limitation, however, a conflict would arise between "a method for reducing power consumption"
`
`in the preamble and "if more than one input stream is received. . . increasing the power
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`consumption" in the claim. Construing the overall power reduction benefit to limit a claim that
`
`discloses dynamically decreasing and increasing power levels would only confuse a jury. The plain
`
`language—a "method for reducing power consumption" that involves "controlling" and not just
`
`reducing—is sufficiently clear. '435 Patent at 2:57-63.
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`If the claim requires "reducing power consumption," as NXP proposes, must "varying"
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`then only mean "reducing"? Must power consumption be reduced based on the input stream
`
`encoding description data more than it is increased by the receipt of more than one input stream?
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`Does the power consumption of the video decoder have to decrease, even if the power consumption
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`of the operational portion of the device increases? And what length of time or triggering action
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`must be considered to determine whether the power consumption is reduced? While the claim ties
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`"increasing" and "varying" to specific conditions, the preamble's "reducing" is not so tethered.
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`Interpreting the preamble as limiting will only ensure that further claim construction issues
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`will arise. The Court should instead construe the preamble as not limiting and give the claim its
`
`plain meaning, avoiding these pitfalls.
`
`3.2.
`
`"Graphics Pipeline" ('945 Patent, Claims 1, 4, 12, and 21)
`
`The Court need not construe "graphics pipeline," which has a plain and ordinary meaning
`
`
`
`
`to a POSITA. NXP's proposal contains extraneous limitations: "hardware," that "hardware" may
`
`only be "one or more circuits," and that hardware can only process "graphics data." NXP aims to
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`—7—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 12 of 26
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`tether the invention of the '945 patent to the distant, analog past when the claimed invention
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`represented a key leap forward towards digital, parallel graphics processing.
`
`Term
`
`Claims
`
`Plaintiff's Proposal
`
`Defendants' Proposal
`
`"graphics
`pipeline"
`
`'945 patent,
`Claims 1, 4, 12, 21
`
`Plain and ordinary
`meaning
`
`"hardware, which may be one or more
`circuits, that processes graphics data"
`
`
`
`3.2.1. NXP's Construction Improperly Reads Out Software Elements
`
`A graphics pipeline will include some hardware. But to construe "graphics pipeline" as
`
`only "hardware" that may only consist of "one or more circuits" impermissibly narrows the claim
`
`scope and contradicts the intrinsic evidence. NXP falsely asserts that the "circuit" in the claim only
`
`includes hardware. But the '945 patent teaches, and a POSITA would have understood, that circuits
`
`can include a processor implementing software instructions. NXP's extrinsic evidence confirms
`
`this unremarkable notion, defining "pipeline" to include processors. See ECF No. 49-3 at 5.
`
`Looking no further than the claims themselves confirms that a "graphics pipeline" can
`
`include non-hardware elements. For example, claims 1 and 21 list a "memory controller" as an
`
`element of the graphics processing circuit. A POSITA would understand that a memory controller
`
`could, and often does, implement software instructions. Hart Decl., ¶ 19. The specification goes
`
`further, stating the graphics processing circuit 34 (which includes the graphics pipelines 101 and
`
`102) may be integrated with a host processor, which in turn may be a "graphics application running
`
`on the system processor." '945 Patent at 3:61-67 (emphasis added). A POSITA would understand
`
`"application" there to mean software. Hart Decl., ¶ 22. The specification thus explains that graphics
`
`pipelines may be implemented as software running on hardware. And the specification describes
`
`the graphics pipeline performing operations—e.g., matrix operations and drawing bounding
`
`boxes—that a POSITA would expect is performed by software. Id., ¶ 20.
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`—8—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 13 of 26
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`The file history also confirms both applicant and examiner understood that a graphics
`
`pipeline" can include software. The examiner cited rendering engines 312 in U.S. Patent No.
`
`6,864,896 ("Perego") as disclosing "graphics pipelines." Ex. 3 at 6–7. Perego describes rendering
`
`engines 312 as software able to process "instructions." E.g., Ex. 4 at Abstract; 4:36-40; claims 3,
`
`12. The examiner also cited U.S. Patent No. 6,184,906 ("Wang") as disclosing a memory controller
`
`28. Ex. 5 at 12. Wang discloses that the memory controller 28 includes processors executing
`
`software. E.g., Ex. 6 at 3:59-63. Neither examiner nor applicant distinguished Wang on this basis,
`
`nor would they as it was well understood at the time of the invention that a graphics pipeline could
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`and often did include software. E.g., Ex. 2, ¶¶ 17, 21, 22.
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`3.2.2. NXP's Addition of "Processes Graphics Data" Only Risks Confusion
`
`NXP’s construction of "graphics pipeline" also requires the hardware to only process
`
`
`
`
`"graphics data." This needless language could only cause confusion in view of the full claim set.
`
`
`
`The '945 patent describes the function of graphics pipelines. Claim 1 recites graphics
`
`pipelines "operative to process data in a corresponding set of tiles of a repeating tile pattern
`
`corresponding to screen locations." Claim 21 is similar. The claim thus textually describes what
`
`the inventive graphics pipelines must process—no further explanation is needed. If NXP wants
`
`"graphics data" to mean "data in a corresponding set of tiles of a repeating tile pattern
`
`corresponding to screen locations," this language adds nothing as it is already present in the text
`
`of the claim. If NXP wants "graphics data" to require that graphics pipelines process something
`
`else, the language is improper, again because the claims recite what must be processed.
`
`
`
`NXP's construction of "graphics pipeline" adds nothing helpful to the plain and ordinary
`
`meaning of the term, but risks injecting improper limitations into the claim and confusing a jury.
`
`The Court should afford this term its plain and ordinary meaning as understood by a POSITA.
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`—9—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 14 of 26
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`3.3.
`
`"Graphics Pipelines Operative to Process Data in a Dedicated Tile"
`('945 Patent, Claims 1 and 21)
`
`A POSITA would understand the plain and ordinary meaning of this term without a
`
`construction. To the extent a construction is required, NXP's proposal goes too far.
`
`Term
`
`Claims
`
`Plaintiff's
`Proposal
`
`Defendants' Proposal
`
`"graphics pipeline
`operative to process
`data in a dedicated tile"
`
`'945 patent,
`Claims 1, 21
`
`Plain and ordinary
`meaning
`
`"graphics pipeline operative such that
`data for a specific tile is processed by
`one and only one pipeline"
`
`
`
`3.3.1. NXP's Proposed Construction Goes Against the Specification
`
`NXP's construction seeks to limit the claim scope to situations when all data for a specific
`
`tile is processed by "one and only one" pipeline. In both life and claim construction, extremist
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`language like this should raise alarm bells. The specification, of course, is less single-minded. The
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`inventors explained that each pipeline may use data related to other tiles to generate pixels for their
`
`assigned tile.
`
`Figure 3, for example, shows that a primitive may overlap several tiles 72-75. The '945
`
`patent teaches that front end circuitry of each of the pipelines—which may be common front end
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`circuitry—converts vertex data 31 into pixel data 36. The pixel data 36 may then be provided to
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`scan converters 37, 40, which then associate pixels of the primitive with the tiles assigned to each
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`pipeline. The back end circuitry 39, 42 performs "pixel attribute operations (e.g., color, texture
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`blending, z-buffering)" on the pixel data 60, 61 for the respective identified pixels. Thus, the '945
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`patent describes that vertex data 31 and pixel data 36 for a primitive that is not within a single tile
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`may be used to identify the pixels for which pixel attribute operations are performed.
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`The parts of the specification NXP cites—"the first graphics pipeline 101 operative to
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`process graphics data in a first set of tiles" and the "second graphics pipeline 102 operative to
`
`—10—
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`

`

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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 15 of 26
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`process graphics data in a second set of tiles"—must be read in the context of the specification's
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`allowance for pipelines' use of another tile's data for specific purposes. NXP's proposal further
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`departs from the patent by using "data" instead of "graphics data," as in the claims.
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`NXP also ignores the claim's reference to the "respective one of the at least two graphics
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`pipelines," which means only one of the multiple pipelines must be operative to process data in a
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`dedicated tile. For example, NXP's construction would render Claim 10 meaningless because it
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`specifies that a second of the at least two graphics pipelines processes data "only in a second set
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`of tiles in the repeating tile pattern." Here too the plain meaning should govern.
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`
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`3.3.2. AST's Arguments in a 2016 POPR Accord with the Plain Meaning
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`NXP cites discussion in a POPR AST filed in 2016 in an IPR proceeding that never reached
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`institution. But the POPR—unlike NXP's proposed construction—properly focused on the pixels
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`over the pipelines and allows some data to be used by different pipelines. See ECF No. 49-2 at 37
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`("exclusively allocated . . . to processing the pixels for a particular tile") (emphasis added).
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`The POPR discussion crates no clear disclaimer of claim scope. AST's arguments focused
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`on two references: Narayanaswami and Perego. Narayanaswami disclosed processors that "process
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`all pixels, whether they are in the tile or not." Id. at 39; see also id. at 41 ("[E]ach Narayanaswami
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`processor scan converts and processes all of the subobject's pixels, not just those in a specific tile").
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`AST noted Narayanaswami's disclosure that "these method steps are 'executed concurrently and
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`in parallel by all processors.'" Id. at 42. There is no basis for prosecution history estoppel here.
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`AST's discussion of Perego provides even less basis for finding disclaimer. In the IPR,
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`Petitioner argued that Perego disclosed rendering engines—which it called pipelines—assigned to
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`different tiles. Id. at 42. AST argued this does not satisfy the claim language. Rendering engines
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`assigned to different tiles could be implemented just as in Narayanaswami, which "discloses a
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`system in which the rendering or certain tiles is assigned to a particular processor, but each
`
`—11—
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`

`

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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 16 of 26
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`processor processes pixel data that is not within the tiles assigned to that processor." Id. at 43.
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`These statements only show that a broad reference to pipelines assigned to different tiles does not
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`satisfy the claim language. It does not represent the broad disclaimer sought by NXP.
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`The Court should apply heavy skepticism to NXP's heavy-handed and unwarranted "one
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`and only one" construction and afford the term its plain and ordinary meaning.
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`3.4.
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`"A Memory Controller . . . Operative to Transfer Pixel Data Between Each
`of a First Pipeline and a Second Pipeline and a Memory Shared Among the
`at Least Two Graphics Pipelines" ('945 Patent, Claims 1 and 21)
`
`This term needs no construction. NXP seeks to change the plain and ordinary meaning by
`
`
`
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`adding an element to the claim. The Court should decline NXP's offer.
`
`Term
`
`Claims
`
`Plaintiff's
`Proposal
`
`Defendants' Proposal
`
`"a memory controller . . .
`operative to transfer pixel data
`between each of a first pipeline
`'945 patent,
`and a second pipeline [the two
`Claims 1-4,
`graphics pipelines] and a
`17-20
`memory shared among the at
`least two graphics pipelines"
`
`Plain and
`ordinary
`meaning
`
`"a memory controller . . . operative to
`transfer pixel data to, from, and
`between (1) the first graphics pipeline
`and the second graphics pipeline, and
`also (2) the two graphics pipelines
`and a memory shared among the two
`graphics pipelines"
`
`
`
`3.4.1. The Claim Language Follows A Well Understood Formulation
`
`The term employs the common and well understood formulation of "between each of X or
`
`Y and Z," which means "between both X and Z and Y and Z." NXP's construction injects a third
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`requirement—between X and Y—that neither the plain language nor the specification supports.
`
`See Immunex Corp. v. Sanofi-Aventis U.S. LLC, 977 F.3d 1212, 1218 (Fed. Cir. 2020) (rejecting
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`additional restriction not required by claims or specification). The claim language does not require
`
`any transfer of pixel data between pipelines. It only requires transfer between each pipeline and
`
`the shared memory. NXP's proposed construction violates this well understood precept.
`
`—12—
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`Case 6:22-cv-00466-ADA-DTG Document 50 Filed 12/19/22 Page 17 of 26
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`Each of claim 1 and 21 recite a m