Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 1 of 18
`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 1 of 18
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`EXHIBIT 6
`EXHIBIT 6
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 2 of 18
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`UNITED STATES DEPARTMENT OF COMMERCE
`United Stoics P11tcnt 11nd Trudcnrnrk Office
`Address: COMMISSIONER FOR PATENTS
`P.O. Box 1450
`Alcxundriu, Virginia 223 I 3~ 1450
`www .uspLo.gov
`
`APPLICATION NO.
`
`FILING DATE
`
`FIRST NAMED INVENTOR
`
`ATTORNEY DOCKET NO.
`
`CONFIRMATION NO.
`
`10/459,797
`
`06/12/2003
`
`Mark M. Leather
`
`00100.02.0053
`
`4148
`
`02/09/2007
`7590
`29 I 53
`ADV AN CED MICRO DEVICES, INC.
`C/0 VEDDER PRICE KAUFMAN & KAMMHOLZ, P.C.
`222 N.LASALLE STREET
`CHICAGO, IL 6060 I
`
`EXAMINER
`
`HSU.JONI
`
`ART UNIT
`
`PAPER NUMBER
`
`2628.
`
`SHORTENED STATUTORY PERIOD OF RESPONSE
`
`3 MONTHS
`
`MAIL DATE
`
`02/09/2007
`
`DELIVERY MODE
`
`PAPER
`
`Please find below and/or attached an Office communication concerning this application or proceeding.
`
`If NO period for reply is specified above, the maximum statutory period will apply and will expire 6 MONTHS
`from the mailing date of this communication.
`
`PTOL-90A (Rev. 10/06)
`
`AST0000751
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 3 of 18
`Application No.
`Applicant(s)
`
`Office Action Summary
`
`10/459,797
`
`Examiner
`
`LEATHER ET AL.
`
`Art Unit
`
`2628
`Joni Hsu
`-- The MAILING DA TE of this communication appears on the cover sheet with the correspondence address --
`Period for Reply
`A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE~ MONTH(S) OR THIRTY (30) DAYS,
`WHICHEVER IS LONGER, FROM THE MAILING DATE OF THIS COMMUNICATION.
`• Extensions of time may be available under the provisions of 37 CFR 1.136(a). In no event, however, may a reply be timely filed
`after SIX (6) MONTHS from the mailing date of this communication.
`If NO period for reply is specified above, the maximum statutory period will apply and will expire SIX (6) MONTHS from the mailing date of this communication.
`-
`- Failure to reply within the set or extended period for reply will, by statute, cause the application to become ABANDONED (35 U.S.C. § 133).
`Any reply received by the Office later than three months after the mailing date of this communication, even if timely filed, may reduce any
`earned patent term adjustment. See 37 CFR 1. 704(b).
`Status
`
`1)[8J Responsive to communication(s) filed on 13 July 2006.
`2a)0 This action is FINAL.
`2b)~ This action is non-final.
`3)0 Since this application is in condition for allowance except for formal matters, prosecution as to the merits is
`closed in accordance with the practice under Ex parte Quayle, 1935 C.D. 11, 453 O.G. 213.
`
`Disposition of Claims
`
`4)[8J Claim(s) 1-26 is/are pending in the application.
`4a) Of the above claim(s) __ is/are withdrawn from consideration.
`5)0 Claim(s) __ is/are allowed.
`6)[8J Claim(s) 1-26 is/are rejected.
`7)0 Claim(s) __ is/are objected to.
`8)0 Claim(s) __ are subject to restriction and/or election requirement.
`
`Application Papers
`
`9)0 The specification is objected to by the Examiner.
`1 O) □ The drawing(s) filed on __ is/are: a)□ accepted or b)D objected to by the Examiner.
`Applicant may not request that any objection to the drawing(s) be held in abeyance. See 37 CFR 1.85(a).
`Replacement drawing sheet(s) including the correction is required if the drawing(s) is objected to. See 37 CFR 1.121(d).
`11) □ The oath or declaration is objected to by the Examiner. Note the attached Office Action or form PTO-152.
`
`Priority under 35 U.S.C. § 119
`
`12) □ Acknowledgment is made of a claim for foreign priority under 35 U.S.C. § 119(a)-(d) or (f).
`a) □ All b)D Some * c)D None of:
`1.0 Certified copies of the priority documents have been received.
`2.0 Certified copies of the priority documents have been received in Application No. __ .
`3.0 Copies of the certified copies of the priority documents have been received in this National Stage
`application from the International Bureau (PCT Rule 17.2(a)).
`* See the attached detailed Office action for a list of the certified copies not received.
`
`Attachment(s)
`1) ~ Notice of References Cited (PT0-892)
`2) D Notice of Draftsperson's Patent Drawing Review (PT0-948)
`3) D Information Disclosure Statement(s) (PTO/SB/08)
`Paper No(s)/Mail Date __ .
`
`4) D Interview Summary (PT0-413)
`Paper No(s)/Mail Date. __ .
`5) D Notice of Informal Patent Application
`6) D Other: __ .
`
`U.S. Patent and Trademark Office
`PTOL-326 (Rev. 08-06)
`
`Office Action Summary
`
`Part of Paper No./Mail Date 71306
`
`AST0000752
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 4 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page2
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`DETAILED ACTION
`
`Response to Amendment
`
`1.
`
`Applicant's arguments with respect to claims 1-18 and 20-26 have been considered but
`
`are moot in view of the new ground(s) of rejection.
`
`2.
`
`Applicant's arguments, see pages 1-3, filed July 13, 2006, with respect to the rejection(s)
`
`of claim(s) 1-7 and 20-26 under 35 U.S.C. 102(e) and Claims 8-18 under 35 U.S.C. 103(a) have
`
`been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
`
`However, upon further consideration, a new ground(s) of rejection is made in view of Kelleher
`
`(US005794016A).
`
`3.
`
`Applicant argues that Furtner (US006778 l 77B 1) describes a non-repeating tile pattern
`
`approach and alternatively a per pixel processing approach, neither of which anticipate the
`
`claimed subject matter (page 1). The cited FIG. 21A shows a non-repeating tile based approach,
`
`and is the only tile based approach described by the cited portion of Furtner. Furtner describes
`
`that the per pixel processing approach is repeating. However, Furtner does not teach a repeating
`
`tile based approach. The Examiner attempted to cite the reference for possibilities that are not
`
`disclosed in the reference (pages 2-3).
`
`In reply, the Examiner agrees. However, new grounds of rejection are made in view of
`
`Kelleher.
`
`AST0000753
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 5 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 3
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`Claim Objections
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`4.
`
`Claim 25 is objected to because it is exactly the same as Claim 1, and therefore is a
`
`repeated claim. Appropriate correction is required.
`
`Claim Rejections-35 USC§ 101
`
`5.
`
`35 U.S.C. 101 reads as follows:
`
`Whoever invents or discovers any new and useful process, machine, manufacture, or
`composition of matter, or any new and useful improvement thereof, may obtain a patent
`therefor, subject to the conditions and requirements of this title.
`
`6.
`
`Claims 20-23 are rejected under 35 U.S.C. 101 because the claimed invention is directed
`
`to non-statutory subject matter.
`
`Claim 20 recites a graphics processing method, however it appears to be directed to an
`
`abstract idea rather than a practical application of the abstract idea. The claimed invention as a
`
`whole must accomplish a practical application. That is, it must produce a "useful, concrete and
`
`tangible result (State Street, 149 F.3d at 1373, 47 USPQ2d at 1601-02). The tangible
`
`requirement requires that the claim must set forth a practical application of the 101 judicial
`
`exception to produce a real-world result (Benson, 409 U.S. at 71-72, 175 USPQ at 676-77). See
`
`MPEP 2106 II A Since there is no tangible result recited in these claims, these claims are
`
`directed to non-statutory subject matter.
`
`Claims 21-23 are non-statutory for the same reasons discussed above.
`
`AST0000754
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 6 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page4
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`Claim Rejections - 35 USC§ 102
`
`7.
`
`The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the
`
`basis for the rejections under thjs section made in this Office action:
`
`A person shall be entitled to a patent unless -
`
`(b) the invention was patented or described in a printed publication in this or a foreign
`country or in public use or on sale in this country, more than one year prior to the date of
`application for patent in the United States.
`
`8.
`
`Claims 1-5, 7, 9, 10, 12-16, 18, and 20-26 are rejected under 35 U.S.C. 102(b) as being
`
`anticipated by Kelleher (US005794016A).
`
`9.
`
`With regard to Claim 1, Kelleher discloses a graphics processing circuit (I0C, Figure 3)
`
`comprising at least two graphics pipelines (20A, 20B; graphics system 1 0C with N rendering
`
`processors 20A-20N, Col. 3, lines 22-23; rendering processor 20 provides a video pipeline, Col.
`
`4, lines 9-14) operative to process data in a corresponding set of tiles (group of pixel blocks 52,
`
`Figure 4) of a repeating tile pattern corresponding to screen locations, a respective one of the at
`
`least two graphics pipelines operative to process data in a dedicated tile, wherein the repeating
`
`tile pattern includes a horizontally and vertically repeating pattern of square regions, as shown in
`
`Figure 4 (graphics memory 22 that has been partitioned into a plurality of pixel blocks 52 that
`
`are tiled in the x- and y-direction of the graphics memory 22, the graphics memory 22 renders a
`
`l 280xl 0 24 screen display, pixel blocks 5 2 are organized into noncontiguous groups of blocks
`
`52, groups of blocks 52 are then assigned to the rendering processors 20, each rendering
`
`processor 20 writes only those pixels that are located in the blocks 52 of the assigned groups,
`
`Col. 4, line 60-Col. 5, line 19).
`
`AST0000755
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 7 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 5
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`10. With regard to Claim 2, Kelleher discloses that the square regions (blocks 52) comprise a
`
`two dimensional partitioning of memory (22, Figure 4) ((graphics memory 22 that has been
`
`partitioned into a plurality of pixel blocks 52 that are tiled in the x- andy-direction of the
`
`graphics memory 22, Col. 4, lines 60-62).
`
`11. With regard to Claim 3, Kelleher discloses that the memory (22, Figure 4) is a frame
`
`buffer (graphics memory 22, also known as a frame buffer, Col. 3, lines 38-41).
`
`12. With regard to Claim 4, Kelleher discloses that each of the at least two graphics pipelines
`
`(20A, 20B, Figure 3; Col. 3, lines 22-23; Col. 4, lines 9-14) further includes front end circuitry
`
`(80, 82, Figure 7) operative to receive vertex data and generate pixel data corresponding to a
`
`primitive to be rendered, and back end circuitry (84, Figure 7), coupled to the front end circuitry,
`
`operative to receive and process a portion of the pixel data (each of the rendering processors 20
`
`independently scan-converts the geometric objects, the rendering processor 20 first reads the
`
`command packets, the rendering processors 20 then processes the command packets in a
`
`pipeline process comprising a dispatch stage 80, a setup stage 82, and an updated stage 84, in a
`
`dispatch stage 80, the dispatch circuit 64 reads the command packets from the command queue
`
`62 and dispatches the vertex data in the command to the next stage in the pipeline, the setup
`
`stage 82, the setup stage 82 includes the geometric setup circuit 66 and the attribute setup circuit
`
`70 which accept the triangle vertex data and setup the triangles for scan-conversion by the
`
`AST0000756
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 8 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 6
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`update stage 84, the update stage 84 includes the interpolator circuit 72, which interpolates final
`
`attribute values for the pixels in each triangle, Col. 8, line 52-Col. 9, line 23).
`
`13. With regard to Claim 5, Kelleher discloses that each of the at least two graphics pipelines
`
`(20A, 20B, Figure 3; Col. 3, lines 22-23; Col. 4, lines 9-14) further includes a scan converter (84,
`
`Figure 7), coupled to the back end circuitry, operative to determine the portion of the pixel data
`
`to be processed by the back end circuitry (scan-converts the geometric objects into the memory
`
`blocks 52 indicated by their block enable.field 61, Col. 8, lines 52-61; scan-conversion by the
`
`update stage 84, Col. 9, lines 1-23; block enable field 61 determines which groups of blocks 52
`
`within the graphics memory 22 are allocated to and controlled by the rendering processor 20,
`
`Col. 6, lines 26-28).
`
`14. With regard to Claim 7, Kelleher discloses that the at least two graphics pipelines 20A,
`
`(20B, Figure 3; Col. 3, lines 22-23; Col. 4, lines 9-14) separately receive the pixel data from the
`
`front end circuitry (Col. 8, lines 52-65).
`
`15. With regard to Claim 9, Kelleher discloses a memory controller (68, Figures 7 and 1 I)
`
`coupled to the at least two graphics pipelines (20A, 20B, Figure 3; Col. 3, lines 22-23; Col. 4,
`
`lines 9-14), operative to transfer pixel data between each of a first pipeline and a second pipeline
`
`and a memory (22) (address generation circuit 68 accepts the initial geometry values from the
`
`geometric setup circuit 66, and generates physical memory addresses, Col. 9, lines 18-23; Col.
`
`10, lines 40-47).
`
`AST0000757
`
`

`

`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 9 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 7
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`16. With regard to Claim 10, Kelleher discloses that a first of the at least two graphics
`
`pipelines (20A, Figure 3; Col. 3, lines 22-23; Col. 4, lines 9-14) processes the pixel data only in a
`
`first set of tiles (group 0 of pixel blocks 52) in the repeating tile pattern (each rendering
`
`processor 20 writes to only those pixels that are located in the blocks 52 of the assigned groups,
`
`blocks in group "O" may be assigned to rendering processor 0, Col. 4, line 65-Col. 5, line 19).
`
`17. With regard to Claim 12, Kelleher discloses that a second of the at least two graphics
`
`pipelines (20B, Figure 3; Col. 3, lines 22-23; Col. 4, lines 9-14) processes the pixel data only in a
`
`second set of tiles (group 1 of pixel blocks 52) in the repeating tile pattern (each rendering
`
`processor 20 writes to only those pixels that are located in the blocks 52 of the assigned groups,
`
`blocks in group "l" may be assigned to rendering processor 1, Col. 4, line 65-Col. 5, line 19).
`
`18. With regard to Claim 13, Claim 13 is similar in scope to Claim 11, and therefore is
`
`rejected under the same rationale.
`
`19. With regard to Claim 14, Claim 14 is similar to Claims 4 and 10, except that Claim 14 is
`
`for a third and fourth graphics pipeline. Kelleher discloses four graphics pipelines (20A-20N,
`
`Figure 3; Col. 3, lines 22-23; Col. 4, lines 9-14). Therefore, Claim 14 is rejected under the same
`
`rationale as Claims 4 and 10.
`
`AST0000758
`
`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 10 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 8
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`20. With regard to Claims 15 and 16, these claims are each similar in scope to Claim 11, and
`
`therefore are rejected under the same rationale.
`
`21. With regard to Claim 18, Kelleher discloses a bridge (38, Figure 3) operative to transmit
`
`vertex data to each of the first (20A), second (20B), third (20C) and fourth (20N) graphics
`
`pipelines (Col. 3, lines 22-23; Col. 4, lines 9-14; rendering processor 20first reads the command
`
`packets sent to it over the PC! bus 30, Col. 8, lines 56-65; rendering processors 20 are
`
`connected to a system PC! bus 30A through a PC! bridge 38, Col. 3, lines 46-50).
`
`22. With regard to Claim 20, Kelleher discloses a graphics processing method (Col. 2, lines
`
`27-28), comprising receiving vertex data for a primitive to be rendered; generating pixel data in
`
`response to the vertex data; determining the pixels within a set of tiles (group of pixel blocks 52)
`
`of a repeating tile pattern corresponding to screen locations to be processed by a corresponding
`
`one of at least two graphics pipelines (20A, 20B, Figure 3; Col. 3, lines 22-23; Col. 4, lines 9-14)
`
`in response to the pixel data, the repeating tile pattern including a horizontally and vertically.
`
`repeating pattern of square regions, as shown in Figure 4; and performing pixel operations on the
`
`pixels within the determined set of tiles by the corresponding one of the at least two graphics
`
`pipeHnes (Col. 4, line 60-Col. 5, line 19; Col. 8, lines 56-65).
`
`23. With regard to Claim 21, Kelleher discloses that determining the pixels within a set of
`
`tiles (group of pixel blocks 52) of the repeating tile pattern to be processed further comprises
`
`AST0000759
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 11 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 9
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`determining the set of tiles that the corresponding graphics pipeline (20, Figure 3; Col. 3, lines
`
`22-23; Col. 4, lines 9-14) is responsible for (Col. 4, line 60-Col. 5, line 19).
`
`24. With regard to Claim 22, Kelleher discloses that the scan converter determines which
`
`groups of blocks 52 within the graphics memory 22 are allocated to and controlled by the
`
`graphics pipelines 20 (Col. 8, lines 52-61 ). The graphics memory is partitioned into a plurality
`
`of pixel blocks that are tiled in the x-and y-direction of the graphics memory (Col. 4, lines 60-
`
`62). Kelleher discloses that determining the pixels within a set of tiles (group of pixel blocks 52)
`
`of the repeating tile pattern to be processed (Col. 5, lines 6-19) inherently further comprises
`
`. providing position coordinates of the pixels within the determined set of tiles to be processed to
`
`the corresponding one of the at least two graphics pipelines.
`
`25. With regard to Claim 23, Kelleher discloses transmitting the processed pixels to memory
`
`(22, Figure 4) (rendering processor 20 scan-converts the object into the graphics memory 22, the
`
`graphics memory stores pixel data, Col. 3, lines 36-41).
`
`26. With regard to Claim 24, Kelleher discloses a graphics processing circuit, comprising
`
`front end circuitry (80, 82, Figure 7) operative to generate pixel data in response to primitive data
`
`for a primitive to be rendered; first back end circuitry (84), coupled to the front end circuitry,
`
`operative to process a first portion of the pixel data in response to position coordinates; a first
`
`scan converter, coupled between the front end circuitry and the first back end circuitry, operative
`
`to determine which set of tiles of a repeating tile pattern are to be processed by the first back end
`
`AST0000760
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 12 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 10
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`circuitry (CoL 3, lines 22-23; Col. 8, line 59-Col. 9, line 23), the repeating tile pattern including a
`
`horizontally and vertically repeating pattern of square regions, as shown in Figure 4 (Col. 4, line
`
`60-Col. 5, line 19), and operative to provide the position coordinates to the first back end
`
`circuitry in response to the pixel data (Col. 4, lines 60-62; Col. 8, lines 52-65; Col. 6, lines 36-
`
`3 8); second back end circuitry, coupled to the front end circuitry, operative to process a second
`
`portion of the pixel data in response to position coordinates; a second scan converter, coupled
`
`between the front end circuitry and the second back end circuitry, operative to determine which
`
`set of tiles of the repeating tile pattern are to be processed by the second back end circuitry, and
`
`operative to provide the position coordinates to the second back end circuitry in response to the
`
`pixel data (Col. 3, lines 22-23; Col. 8, line 59-Col. 9, line 23; Col. 4, lines 60-62; Col. 8, lines
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`52-65; Col. 6, lines 36-38); and a memory controller (68, Figures 7 and 11), coupled to the first
`
`and second back end circuitry operative to transmit and receive the processed pixel data (Col. 9,
`
`lines 18-23; Col. 10, lines 40-4 7).
`
`27. With regard to Claim 25, Claim 25 is the same as Claim 1, and therefore is rejected under
`
`the same rationale.
`
`28. With regard to Claim 26, Kelleher discloses a horizontally and vertically repeating
`
`pattern of regions (Col. 4, line 65-Col. 5, line 19) include NxM number of pixels ( each pixel
`
`block 52 is 128xl 28 pixels in size, Col. 6, lines 2-4).
`
`AST0000761
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 13 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 11
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`29.
`
`Thus, it reasonably appears that Kelleher describes or discloses every element of Claims
`
`1-5, 7, 9, 10, 12-16, 18, and 20-26 and therefore anticipates the claims subject.
`
`Claim Rejections - 35 USC§ I 03
`
`30.
`
`The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all
`
`obviousness rejections set forth in this Office action:
`
`(a) A patent may not be obtained though the invention is not identically disclosed or
`described as set forth in section 102 of this title, if the differences between the subject
`matter sought to be patented and the prior art are such that the subject matter as a whole
`would have been obvious at the time the invention was made to a person having ordinary
`skill in the art to which said subject matter pertains. Patentability shall not be negatived
`by the manner in which the invention was made. ·
`
`31.
`
`The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459
`
`(1966), that are applied for establishing a background for determining obviousness under 35
`
`U.S.C. 103(a) are summarized as follows:
`
`1.
`2.
`3.
`4.
`
`Determining the scope and contents of the prior art.
`Ascertaining the differences between the.prior art and the claims at issue.
`Resolving the level of ordinary skill in the pertinent art.
`Considering objective evidence present in the application indicating obviousness
`or nonobviousness.
`
`32.
`
`Claims 6, 8, and 17 are rejected under 35 U.S.C. 103(a) as being unpatentable over
`
`Kelleher (US005794016A) in view of Furtner (US006778177B 1 ).
`
`33. With regard to Claim 6, Kelleher is relied upon for the teachings as discussed above
`
`relative to Claim 1.
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`AST0000762
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 14 of 18
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`Application/Control Number: 10/459,797
`Art Unit: 2628
`
`Page 12
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`However, Kelleher does not explicitly teach that each tile of the set of tiles further
`
`comprises a 16x16 pixel array. However, Furtner describes that each tile of the set of tiles
`
`further comprises a 16xl6 pixel array (Col. 11, lines 45-48, 64-65).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify the device of Kelleher so that each tile of the set of tiles further comprises a
`
`16x16 pixel array as suggested by Furtner because Furtner suggests that depending on the
`
`number of parallel image-rendering pipelines and depending on the memory organization, the
`
`optimum tile size and shape can be selected (Col. 11, lines 45-48, 64-65), and th_erefore it would
`
`be obvious to modify the tile size to be 16x16 pixels if that would be the optimum tile size for a
`
`particular number of parallel image-rendering pipelines and particular memory organization.
`
`34. With regard to Claim 8, Kelleher does not teach that the at least two graphics pipelines
`
`are on multiple chips. However, Furtner describes that the at least two graphics pipelines are on
`
`multiple chips (Col. 6, lines 4 7-51 ).
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify the device of Kelleher so that the at least two graphics pipelines are on
`
`multiple chips as suggested by Furtner because Furtner suggests that this makes the system more
`
`configurable by being able to easily add more graphics pipelines to increase the performance
`
`(Col. 6, lines 29-30, 42-51 ).
`
`3 5. With regard to Claim 17, Claim 17 is similar in scope to Claim 8, and therefore is
`
`rejected under the same rationale.
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`AST0000763
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 15 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
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`Page 13
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`36.
`
`Claim 11 is rejected under 35 U.S.C. 103(a) as being unpatentable over Kelleher
`
`(US005794016A) in view of Hamburg (US005905506A).
`
`Kelleher is relied upon for the teachings as discussed above relative to Claim 10.
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`Kelleher discloses that the first of the at least two graphics pipelines (20A, Figure 3; Col. 3, lines
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`22-23; Col. 4, lines 9-14) further includes a scan converter (84, Figure 7), coupled to the front
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`end circuitry (80, 82) and the back end circuitry (Col. 8, line 52-Col. 9, line 23). The scan
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`converter determines which groups of blocks 52 within the graphics memory 22 are allocated to
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`and controlled by the graphics pipelines (Col. 8, lines 52-65; Col. 6, lines 26-28). The graphics
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`memory is partitioned into a plurality of pixel blocks that are tiled in the x-and y-direction of the
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`graphics memory (Col. 4, lines 60-62). Therefore, the scan converter is inherently operative to
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`provide memory addresses or position coordinates of the pixels within the first set of tiles to be
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`processed by the back end circuitry.
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`However, Kelleher does not explicitly teach using tile identification data to indicate
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`which tiles are to be processed. However, Hamburg discloses a pixel identification line for
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`receiving tile identification data indicating which tiles are to be processed (during pixel
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`modification, the system must write a pixel within at least one tile within image B, the system
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`determines a tile ID at which to write the pixel value, Col. 5, lines 35-52).
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`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify the device of Kelleher to include using tile identification data to indicate
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`which tiles are to be processed as suggested by Hamburg because Hamburg suggests the
`
`AST0000764
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 16 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
`
`Page 14
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`advantage of using tile identification data to easily track the storage locations of the tile pixel
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`data and being able to easily retrieve data for a particular image tile (Col. 1, lines 46-54).
`
`37.
`
`Claim 19 is rejected under 35 U.S.C. 103(a) as being unpatentable over Kelleher
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`(US005794016A) and Furtner (US006778177B1) in view ofKent (US 20030164830Al).
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`Kelleher and Furtner are relied upon for the teachings as discussed above relative to
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`Claim 17. Kelleher discloses that the data includes a polygon. Each pixel block 52 is 128xl28
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`pixels in size. This block size has been determined to effectively divide the parallelism of the
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`graphics pipelines 20. Since polygons tend to be particularly small, and 128x128 blocks 52 are
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`relatively large, polygons will not commonly cross block boundaries (Col. 5, line 65-Col. 6, line
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`12). Furtner describes that the at least two graphics pipelines are on multiple chips (Col. 6, lines
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`47-51 ), as discussed in the rejection for Claim 8.
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`However, Kelleher and Further do not teach creating a bounding box around the polygon
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`and wherein each corner of the bounding box is checked against a super tile that belongs to each
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`separate chip and wherein if the bounding box does not overlap any of the super tiles associated
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`with a separate chip, then the processing circuit rejects the whole polygon and processes a next
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`one. However, Kent discloses that the graphics pipeline [0006] calculates the bounding box of
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`the primitive and testing this against the VisRect. If the bounding box of the primitive is
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`contained in the other Pl O's super tile the primitive is discarded at this stage [0129]. A primitive
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`can be a polygon (independent primitives (triangles or quads), [0088]). The method used is to
`
`calculate the distance from each subpixel sample point in the point's bounding box to the point's
`
`center and compare this to the point's radius. Subpixel sample points with a distance greater
`
`AST0000765
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 17 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
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`Page 15
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`than the radius do not contribute to a pixel's coverage. The cost of this is kept low by only
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`allowing small radius points hence the distance calculation is a small multiply and by taking a
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`cycle per subpixel sample per pixel within the bounding box [0144]. Since the method calculates
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`the distance from each subpixel sample point in the point's bounding box, this must include all
`
`the corners of the bounding box. Therefore, Kent discloses that the data includes a polygon and
`
`that the graphics pipeline creates a bounding box around the polygon and wherein each corner of
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`the bounding box is checked against a super tile that belongs to the graphics pipeline and
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`wherein if the bounding box does not overlap any of the super tiles, then the processing circuit
`
`rejects the whole polygon and processes a next one.
`
`It would have been obvious to one of ordinary skill in the art at the time of invention by
`
`applicant to modify the devices of Kelleher and Furtner to include creating a bounding box
`
`around the polygon and wherein each corner of the bounding box is checked against a super tile
`
`that belongs to each separate chip and wherein if the bounding box does not overlap any of the
`
`super tiles associated with a separate chip, then the processing circuit rejects the whole polygon
`
`and processes a next one as suggested by Kent because Kent suggests the advantage of
`
`processing the super tiles one at a time in order to hide the page break costs [0129, 005 l].
`
`Conclusion
`
`Any inquiry concerning this communication or earlier communications from the
`
`examiner should be directed to Joni Hsu whose telephone number is 571-272-7785. The
`
`examiner can normally be reached on M-F 8am-5pm.
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`AST0000766
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`

`

`•
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`Case 6:22-cv-00466-ADA-DTG Document 49-6 Filed 11/28/22 Page 18 of 18
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`Application/Control Number: 10/459, 797
`Art Unit: 2628
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`Page 16
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`If attempts to reach the examiner by telephone are unsuccessful, the examiner's
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`supervisor, Ulka Chauhan can be reached on 571-272-7782. The fax phone number for the
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`organization where this application or proceeding is assigned is 571-273-8300.
`
`Information regarding the status of an application may be obtained from the Patent
`
`Application Information Retrieval (PAIR) system. Status information for published applications
`
`may be obtained from either Private PAIR or Public PAIR. Status information for unpublished
`
`applications is available through Private PAIR only. For more information about the PAIR
`
`system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR
`
`system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would
`
`like assistance from a USPTO Customer Service Representative or access to the automated
`
`information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
`
`JH
`
`ULKA CHAUHAN
`SUPERVISORY PATENT EXAMINER
`
`AST0000767
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`