Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 1 of 14
`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 1 of 14
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`EXHIBIT 5
`EXHIBIT 5
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 2 of 14
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`IN THE UNITED STATES PATENT AND TRADEMARK OFFICE
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`PATENT APPLICATION
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`Applicants: Mark M. Leather et al.
`Serial No.: 10/459,797
`Filing Date: June 12, 2003
`Confirmation No.: 4148
`
`Examiner: Joni Hsu
`Art Group: 2676
`Docket No.: 00100.02.0053
`
`Title: DIVIDING WORK AMONG MULTIPLE GRAPHICS PIPELINES USING
`A SUPER-TILING TECHNIQUE
`
`Mail Stop Amendment
`Commissioner for Patents
`P.O. Box 1450
`Alexandria, VA 22313-1450
`
`Certificate of First Class Mailing
`I hereby certify that this paper is being deposited with the
`United States Postal Service as first-class mail in an envelope
`addressed to Mail Stop Amendment, Commissioner for Patents,
`P.O. Box 1450, Alexa,rJjio/)1~ 2}/13-1450.
`f-14:-0~ ~
`Date
`Christine A. Wright
`
`AMENDMENT AND RESPONSE
`
`Dear Sir:
`
`In response to the Office Action mailed December 14, 2004, Applicants submit the
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`following Amendment and Response.
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`Amendments to the Specification begin on page 2 of this paper.
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`Amendments to the Claims are reflected in the listing of claims which begins on page 3 of this
`paper.
`
`Remarks begin on page 10 of this paper.
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`03/18/2005 ZJUHAR1 00000004 500441
`01 FC:1201
`200,00 DA
`02 FC:1202
`100.00 DA
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`10459797
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`CHICAG0/#1345789.1
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 3 of 14
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`Amendments to the Specification:
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`Please replace paragraph [0046] with the following amended paragraph:
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`[0046]
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`The bounding boxes' four comers are mapped to the tile pattern, simply by
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`discarding the lower bits of X & Y. The four comers map to the same or different tiles. If they
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`all map to the same tile, then only the pipeline that is associated with that tile receives the
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`polygon. If it maps to only tiles that are associated with only one pipeline, then again only that
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`pipeline receives the polygon. If it maps to tiles that are associated with multiple pipelines, then
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`the entire polygon is sent to all pipelines. In [[our]]~ implementation, we broadeast the
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`polygon is broadcast to all pipelines, masking the pipelines that should not receive it.
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`Consequently, polygons can be sent to only one pipe or up to all the pipes, depending on the
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`coverage of the tiles by the polygon.
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 4 of 14
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`Amendments to the Claims:
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`Re-write the claims as set forth below. This listing of claims will replace all prior versions and
`listings, of claims in the application:
`
`Listing of Claims:
`
`1. (original) A graphics processing circuit, comprising:
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`at least two graphics pipelines operative to process data in a corresponding set of tiles of
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`a repeating tile pattern, a respective one of the at least two graphics pipelines operative to
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`process data in a dedicated tile,
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`wherein the repeating tile pattern includes a horizontally and vertically repeating pattern
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`of square regions.
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`2. (original) The graphics processing circuit of claim 1, wherein the square regions
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`comprise a two dimensional partitioning of memory.
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`3. (original) The graphics processing circuit of claim 2, wherein the memory is a frame
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`buffer.
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`4. (original) The graphics processing circuit of claim 1, wherein each of the at least two
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`graphics pipelines further includes front end circuitry operative to receive vertex data and
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`generate pixel data corresponding to a primitive to be rendered, and back end circuitry, coupled
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`to the front end circuitry, operative to receive and process a portion of the pixel data.
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`5. (original) The graphics processing circuit of claim 4, wherein each of the at least two
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`graphics pipelines further includes a scan converter, coupled to the back end circuitry, operative
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`to determine the portion of the pixel data to be processed by the back end circuitry.
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`6. (original) The graphics processing circuit of claim 1, wherein each tile of the set of
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`tiles further comprises a 16xl6 pixel array.
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`7. (original) The graphics processing circuit of claim 4, wherein the at least two graphics
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`pipelines separately receive the pixel data from the front end circuitry.
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`8. (original) The graphics processing circuit of claim 4, wherein the at least two graphics
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`pipelines are on multiple chips.
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`9. (currently amended) The graphics processing circuit of claim 1, further including a
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`memory controller coupled to the at least two graphics pipelieepipelines, operative to transfer
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`pixel data between each of [[the]]£! first pipeline and [[the]]£! second pipeline and a memory.
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`10. (original) The graphics processing circuit of claim 4, wherein a first of the at least
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`two graphics pipelines processes the pixel data only in a first set of tiles in the repeating tile
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`pattern.
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`11. (original) The graphics processing circuit of claim 10, wherein the first of the at
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`least two graphics pipelines further includes a scan converter, coupled to the front end circuitry
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`and the back end circuitry, operative to provide position coordinates of the pixels within the first
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`CHICAG0/#1345789. I
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 6 of 14
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`set of tiles to be processed by the back end circuitry, the scan converter including a pixel
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`identification line for receiving tile identification data indicating which of the set of tiles is to be
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`processed by the back end circuitry.
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`12. (currently amended) The graphics processing circuit of claim 1, wherein a second of
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`the at least two graphics pipelines processes the [[pixel]] data only in a second set of tiles in the
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`repeating tile pattern.
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`13. (currently amended) The graphics processing circuit of claim 12, wherein the second
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`of the at least two graphics pipelines further includes a scan converter, coupled to [[the]] front
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`end circuitry and [[the]] back end circuitry, operative to provide position coordinates of the
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`pixels within the second set of tiles to be processed by the back end circuitry, the scan converter
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`including a pixel identification line for receiving tile identification data indicating which of the
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`set of tiles is to be processed by the back end circuitry.
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`14. (original) The graphics processing circuit of claim 1 including a third graphics
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`pipeline and a fourth graphics pipeline, wherein the third graphics pipeline includes front end
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`circuitry operative to receive vertex data and generate pixel data corresponding to a primitive to
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`be rendered, and back end circuitry, coupled to the front end circuitry, operative to receive and
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`process the pixel data in a third set of tiles in the repeating tile pattern, and wherein the fourth
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`graphics pipeline includes front end circuitry operative to receive vertex data and generate pixel
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`data corresponding to a primitive to be rendered, and back end circuitry, coupled to the front end
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`circuitry, operative to receive and process the pixel data in a fourth set of tiles in the repeating
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`tile pattern.
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`15. (original) The graphics processing circuit of claim 14, wherein the third graphics
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`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
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`circuitry, operative to provide position coordinates of the pixels within the third set of tiles to be
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`processed by the back end circuitry, the scan converter including a pixel identification line for
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`receiving tile identification data indicating which of the sets of tiles is to be processed by the
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`back end circuitry.
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`16. (original) The graphics processing circuit of claim 14, wherein the fourth graphics
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`pipeline further includes a scan converter, coupled to the front end circuitry and the back end
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`circuitry, operative to provide position coordinates of the pixels within the fourth set of tiles to
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`be processed by the back end circuitry, the scan converter including a pixel identification line for
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`receiving tile identification data indicating which of the sets of tiles is to be processed by the
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`back end circuitry.
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`17. (original) The graphics processing circuit of claim 14, wherein the third and fourth
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`graphics pipelines are on separate chips.
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`18. (original) The graphics processing circuit of claim 14, further including a bridge
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`operative to transmit vertex data to each of the first, second, third and fourth graphics pipelines.
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`19. (original) The graphics processing circuit of claim 17 wherein the data includes a
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`polygon and wherein each separate chip creates a bounding box around the polygon and wherein
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`each corner of the bounding box is checked against a super tile that belongs to each separate chip
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`and wherein if the bounding box does not overlap any of the super tiles associated with a
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`separate chip, then the processing circuit rejects the whole polygon and processes a next one.
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`20. (original) A graphics processing method, comprising:
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`receiving vertex data for a primitive to be rendered;
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`generating pixel data in response to the vertex data;
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`determining the pixels within a set of tiles of a repeating tile pattern
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`to be processed by a corresponding one of at least two graphics pipelines in response to the pixel
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`data, the repeating tile pattern including a horizontally and vertically repeating pattern of square
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`regions; and
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`performing pixel operations on the pixels within the determined set of tiles by the
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`corresponding one of the at least two graphics pipelines.
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`21. (original) The graphics processing method of claim 20, wherein determining the
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`pixels within a set of tiles of the repeating tile pattern to be processed further comprises
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`determining the set of tiles that the corresponding graphics pipeline is responsible for.
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`22. (original) The graphics processing method of claim 20, wherein determining the
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`pixels within a set of tiles of the repeating tile pattern to be processed further comprises
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`providing position coordinates of the pixels within the determined set of tiles to be processed to
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`the corresponding one of the at least two graphics pipelines.
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`23. (original) The graphics processing method of claim 20, further comprising
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`transmitting the processed pixels to memory.
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`24. (currently amended) A graphics processing circuit, comprising:
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`front end circuitry operative to generate pixel data in response to primitive data for a
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`primitive to be rendered;
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`first back end circuitry, coupled to the front end circuitry, operative to process a first
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`portion of the pixel data in response to position coordinates;
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`a first scan converter, coupled between the front end circuitry and the first back end
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`circuitry, operative to determine which set of tiles of a repeating tile pattern are to be processed
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`by the first back end circuitry, the repeating tile pattern including a horizontally and vertically
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`repeating pattern of square regions, and operative to provide the position coordinates to the first
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`back end circuitry in response to the pixel data;
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`second back end circuitry, coupled to the front end circuitry, operative to process a
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`second portion of the pixel data in response to position coordinates;
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`a second scan converter, coupled between the front end circuitry and the second back end
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`circuitry, operative to determine which set of tiles [[or]]of the repeating tile pattern are to be
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`processed by the second back end circuitry, and operative to provide the position coordinates to
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`the second back end circuitry in response to the pixel data; and
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`a memory controller, coupled to the first and second back end circuitry. operative to
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`receive transmit and receive the processed pixel data.
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`25. (new) A graphics processing circuit, comprising:
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`at least two graphics pipelines operative to process data in a corresponding set of tiles a
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`repeating tile pattern, a respective one of the at least two graphics pipelines operative to process
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 10 of 14
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`data in a dedicated tile, wherein the repeating tile pattern includes a horizontally and vertically
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`repeating pattern of regions.
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`26. (new) The graphics processing circuit of claim 25 wherein the horizontally and
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`vertically repeating pattern of regions include NxM number of pixels.
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 11 of 14
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`Applicants respectfully traverse and request reconsideration.
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`REMARKS
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`Claims 9 and 24 are objected to due to typographical errors. These errors have been
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`corrected.
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`Claims 9, 12 and 13 stand rejected under 35 U.S.C. §112, 2nd paragraph, as being
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`indefinite due to antecedent discrepancies caused by typographical errors. Applicants have
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`corrected typographical errors and as such, this rejection is respectfully requested to be
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`withdrawn.
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`Claims 1-8, 10-18, 20-23 stand rejected under 35 U.S.C. §103(a) as being unpatentable
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`over Migdal in view of Heirich further in view of Duffy. Applicants respectfully submit that the
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`Migdal reference actually teaches away from a multi-graphics pipeline structure and as such,
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`cannot render the claimed invention obvious. For example, the Migdal reference is directed to a
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`computer system having a distributed texture memory architecture to overcome problems
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`associated with parallel pipelined architectures. As specifically stated for example in column 2,
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`lines 26-27, Migdal states that there are several disadvantages with using a parallel pipelined
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`approach especially in the case when several pipelines perform parallel processing together in
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`order to generate a single frames worth of data. (See specifically, column 2, lines 31-33). Since
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`Applicants claim a multigraphics pipeline structure that processes data in sets of tiles in a frame,
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`Migdal teaches away from the claimed circuit. Moreover, the office action also admits that
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`Migdal does not teach that there are multiple graphics pipelines and wherein each graphics
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`pipeline processes data in a dedicated tile. As noted, Migdal actually teaches away from
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`Applicants' claimed invention. (See for example, columns 2 and 3 of Migdal). Since the Migdal
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`reference teaches away from Applicants' claimed invention, the claims are in condition for
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 12 of 14
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`allowance and that the combination of the cited references with Migdal does not render the
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`claims obvious.
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`In addition, the Duffy reference has been alleged to be properly combinable with Migdal
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`and Heirich and is allegedly cited as describing a repeating tile pattern where the repeating tile
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`patterns include a horizontally and vertically repeating pattern of square regions (office action
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`citing column 3, lines 67 through column 4, line 4; column 4, lines 31-32; column 5, lines 17-
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`20). However, Applicants respectfully submit that the cited portions of Duffy actually teach a
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`completely different pattern than the repeating tile patterns that are processed by two graphics
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`pipelines wherein the repeating tile pattern includes horizontally and vertically repeating patterns
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`of regions as claimed. For example, the "repeating patterns" cited in the portions referenced in
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`the office action of Duffy, are actually pixel "fill" patterns used for dithering. (See for example,
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`column 3, lines 52-66). As such, the "repeating patterns" of tiles described in Duffy are actually
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`patterned wallpaper or filled patterns that are when displayed allow a person's eye to blend
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`neighboring pixels of differing visual patterns.
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`In contrast, the "tiles" and "repeating tile pattern" of the claimed invention deal with
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`processing tiles that are used by graphics pipelines to process primitive data such as polygons to
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`generate pixels that are ultimately displayed. Accordingly, although some of the wording is
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`similar, the Duffy reference actually refers to a dithering halftone visual pattern of pixels
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`whereas Applicants' claim is directed to tile processing using graphics pipelines. As such, upon
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`further
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`investigation of Duffy,
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`it appears
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`that
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`the Duffy reference may have been
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`misapprehended and actually teaches a different system from that described by Applicants and
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`accordingly, the claims are in condition for allowance.
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`The dependent claims add additional novel and non-obvious subject matter and are also
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`allowable for at least depending upon allowable base claims.
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 13 of 14
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`As to claim 20, Applicants respectfully reassert the relevant remarks made above with
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`respect to claim 1 and as such, this claim is also allowable.
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`Claim 9 stands rejected under 35 U.S.C. §103(a) as being unpatentable over Migdal in
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`view of Heirich further in view of Duffy and in view of Wang. Applicants respectfully reassert
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`the relevant remarks made above with respect to the Migdal and Duffy reference and as such,
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`this claim is also believed to be in condition for allowance.
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`Claim 19 stands rejected under 35 U.S.C. §103(a) as being unpatentable over Migdal in
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`view of Heirich further in view of Duffy and in view of Kent. Applicants respectfully reassert
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`the relevant remarks made above with respect to the Migdal and Duffy reference and as such,
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`this claim is also in condition for allowance. In addition, this claim adds additional novel and
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`non-obvious subject matter and is also therefore allowable.
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`Claim 24 stands rejected under 35 U.S.C. §103(a) as being unpatentable over Migdal in
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`view of Duffy further in view of Morgan and in view of Wang. Applicants respectfully reassert
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`the relevant remarks made above with respect to the Migdal and Duffy reference and as such,
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`this claim is also believed to be in condition for allowance.
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`New claims 25 and 26 are also allowable for similar reasons stated above as the
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`references in combination do not teach or suggest the graphic pipelines and non-square tile
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`processing in horizontally and vertically repeating patterns as claimed.
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`Case 6:22-cv-00466-ADA-DTG Document 49-5 Filed 11/28/22 Page 14 of 14
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`Applicants respectfully submit that the claims are in condition for allowance and
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`respectfully request that a timely Notice of Allowance be issued in this case. The Examiner is
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`invited to contact the below-listed attorney if the Examiner believes that a telephone conference
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`will advance the prosecution of this application.
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`Respectfully submitted,
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`B y : ~& ( , - ~
`Christor J. Reckamp
`Registration No. 34,414
`
`Date:
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`Vedder, Price, Kaufman & Kammholz, P.C.
`222 N. LaSalle Street
`Chicago, Illinois 60601
`PHONE: (312) 609-7599
`FAX:
`(312) 609-5005
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