Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 1 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 1 of 55
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`EXHIBIT 1
`EXHIBIT 1
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 2 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 2 of 55
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`UNITED STATES PATENT AND TRADEMARKOFFICE
`
`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`UNIFIED PATENTS INC.,
`Petitioner,
`
`V.
`
`ADVANCEDSILICON TECHNOLOGIES LLC
`Patent Owner
`
`Case [PR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`PATENT OWNER’S PRELIMINARY RESPONSE
`PURSUANTTO 37 C.E.R.§ 42.107(a)
`
`NXP-AST00156732
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 3 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 3 of 55
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF CONTENTS
`
`PAGE
`
`Introduction & Summary of Argument...0.....0000ccccceccccecesceeeeeeeceesseeeesteeeeeaes 1
`
`The ’945 Patent Discloses Improved Graphics Pipelines.......0.0.0... eee 3
`
`Unified’s Petition... ccc icc ccccccecceccsccescecesecseceseensseesesessecssecasessecssesnesenseeaes 7
`
`IL.
`
`IIL.
`
`A.—The Challenged Claims.....0..00ccccccccccccccccccscceccnseecesseeeensseeeesseeeeenseeeess 8
`
`B.—The Asserted References .......0..ccccccccccceseceesecesneeeereeesesessseesseeenseeeaae 10
`
`L.
`
`2.
`
`3.
`
`NarayanaSwam 0.00.0... cece cece cece ce ceeeeceeseteceeeceeceteeecneseecene: 10
`
`POLOQO... cccccccccceec cece cecceseeceseseecesasecesssaeecessesecessesessssessssseesesaese 13
`
`SOUT occ ccccccccsecceseceesseessececeeecsaeeesseeceseccesseensesesseesseeseeeesseees 15
`
`IV.
`
`The Correct Claim Construction of Material Disputed Terms..........0000.000... 17
`
`A.—The Controlling Claim Construction Standard ...0...000 cece 17
`
`B.—The Only Material Claim Construction Issue Facing the Board
`Is The Correct Construction of “memory controller”....0....000cc ce. 19
`
`L.
`
`2.
`
`The correct construction of “memory controller” ........0..0.... 19
`
`Unified provides no construction for “memory
`controller” and no support for its application of “memory
`controller” to Setber 0... cecececesceceseseeceesseeeseesseeesteeenseees 20
`
`a. Unified neither alleges nor proves that its implicit
`construction is the ordinary meaning of the claimed
`“memory controller” ooo... ec ccccececcscesseceeseteesecesseeessseees 21
`
`b. Unified neither alleges nor provesthat its implicit
`construction is some purported special definition of the
`claimed “memory controller’ ..0....00000ccece 22
`
`C.
`
`The Remaining Claim Construction Dispute Is Not Material
`and Should Not Be Decided By the Board...000...000000ec cc eeceeeseeeeeeee 25
`
`All Challenged Claims: Seiler Cannot Cure The Admitted
`Deficiencies Of Perego And Narayanaswam..........0..0000cccccccccececeseceeeereeees 25
`
`A.—Seiler Does Not Disclose The Claimed Memory Controller.............. 26
`
`B.—Unified Has Failed To Identify Evidence Sufficient To MeetIts
`Burden Of Proving That It Would Have Been Obvious To
`Combine Seiler With Either Perego Or Narayanaswamil..........0...0.... 28
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`NXP-AST00156733
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 4 of 55
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`1.
`
`2.
`
`Ground I: Unified Has Not Shown That It Would Have
`Been Obvious To Combine Seiler With Perego .......00..00000000. 29
`
`Ground I: Unified Has Not Shown That It Would Have
`Been Obvious To Combine Seiler With Narayanaswami........ 31
`
`a. Unified identifies no explanation for how a person of
`ordinary skill would have combined Seiler and
`NarayanaSwa.00.....cccceccccccececcesesceceseseseseeceserseeeseseeceease 33
`
`b. Unified fails to establish a reasonable likelihood of proving
`whya person of ordinary skill would have combined
`Narayanaswamiand Seiler... ccc cccccceseceesseeeeteees 35
`
`VI. All Challenged Claims: Unified Has Failed To Meet Its Burden Of
`Identifying A Pipeline “operative to process data in a dedicated tile”.......... 37
`
`lL.
`
`2.
`
`Unified Has Not Shown That Narayanswami Discloses A
`Pipeline “operative to process data in a dedicated tile”............ 38
`
`Unified Has Not Shown That Perego Discloses A
`Pipeline “operative to process data in a dedicatedtile”............ 42
`
`Vil. Dependent Claims 2 and 3: Unified Has Failed To Meet Its Burden Of
`Identifying “a two dimensional partitioning of memory”..........0.00.00ee ee 44
`
`VUTL. Conclusion oo. cecccccccceccccceseeeseceseeeseseeeseeceecsesseceseecesecessecesseeessseeeseeesseenaees 46
`
`ill
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`NXP-AST00156734
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 5 of 55
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`
`ACTY, Inc. v. Walt Disney Co.,
`346 F.3d 1082 (Fed. Cir. 2003) oo... ccccccccccceeceescceesceecaceeseseeessenseeesseeseesesens 22
`
`Aventis Pharma S.A. v. Hospira, Inc.,
`675 F.3d 1324 (Fed. Cir, 2012) ooo ccescecesecensesesnecetseeeneenssseenseeeees 19, 23
`
`Becton, Dickinson and Co. v. One StockDug Holdings, LLC,
`IPR2013-00235, Paper 30 (PTAB Sept. 25, 2014)... eee ccceeeeeteeee 18, 23
`
`Ericcson, Inc. v. Intellectual Ventures I LLC,
`IPR2014-00921, Paper 8 (PTAB Dec. 16, 2014) ooo eect eeceeeeeees 18, 23
`
`Hill-RomServices, Inc. v. Stryker Corporation,
`755 F.3d 1367 (Fed. Cir. 2014) ooo ccc cccecccecceeseeesseessseeneseensseens 18, 19, 23
`
`Hockerson-Halberstadt, Inc. v. Converse Inc.,
`183 F.3d 1369 (Fed. Cir, 1999) ooo ccc cece c cece cesseceseessesesseeessesenseseseseeees 22
`
`Intellectual Ventures Memt, LLC, v. Xilinx, Inc.,
`IPR2012-00019, Paper 33 (PTAB February 10, 2014)oc eeeteeees 18
`
`Phillips v. AWH Corp.,
`A415 F.3d 1303 (Fed. Cir. 2005) (en banc) oo... cece cceceececeeeseeeesesesseseseseenes 18
`
`Universal Remote Control, Inc. v. Universal Electronics, Inc.,
`IPR2013-00127, Paper 32 (PTAB June 30, 2014) oo. cee esteetereeeee 18
`
`Vivid Techs., Inc. v. Am. Sci. & Eng’g, Inc.,
`200 F.3d 795 (Fed. Cir, 1999) ooo. cccccccccccccccccccscecsseeeeseeeseceseeessesesseseseeesseeess 19
`
`Wellman, Inc. v. Eastman Chem. Co.,
`642 F.3d 1355 (Fed. Cir, 2011) occ ccccccescceeescnssecessecensesesseeesseeeseeenaeee 19
`
`Wowza Media Sys., LLC v. Adobe SystemsInc.,
`[PR2013-00054, No. 12 (PTAB Apr. 8, 2013)... cece cececteeeeteteneeenseeenes 18
`
`1V
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`NXP-AST00156735
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 6 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 6 of 55
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`Other Authorities
`
`77 Fed. Reg. 48,756, 48,766 (Aug. 14, 2012) ooo cece cece ceessesenseeeneeeeseees 17
`
`37 CLF.R. S1OO(D) ooo cece cccccccseeceseecesseceseeecssecassecseeceseesesseeseeeessessneeeeeseaeees 17
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`NXP-AST00156736
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 7 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 7 of 55
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`IPR2016-01060
`U.S. Patent No. 8,933,945 B2
`
`TABLE OF EXHIBITS
`
`
`
`Declaration of John C. Hart, Ph.D. In Support Of Patent Owner
`Advanced Silicon Technologies LLC’s Preliminary Response
`
`
`
`
`2001
`
`vi
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`NXP-AST00156737
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 8 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`1,
`
`Introduction & Summaryof Arguments
`
`Unified’s Petition fails to establish the required likelihoodthat it will prove
`
`that the challenged claims of Advanced Silicon’s U.S. Patent No. 8,933,945 are
`
`unpatentable for at least the following reasons.
`
`e Seiler cannot cure Perego’s and Narayanaswami’s admitted deficiencies
`
`Unified concedesthat its primary references (Perego in GroundI and
`
`Narayanaswamiin Ground I) fail to disclose a numberoflimitations found in
`
`every challenged claim, including the claimed “memory controller.” Unified
`
`argues that combining these references with the Seiler reference would cure these
`
`admitted deficiencies, but Unified’s argument must fail because:
`
`1. Underthe correct construction of “memory controller’—andthe only
`
`proposed construction before the Board—there is no evidencethat Seiler
`
`discloses the “memory controller” admittedly missing from Perego and
`
`Narayanaswami; and
`
`2. Asa threshold matter, Unified has failed to identify any evidence
`
`showing that it is likely to meet its burden of proving that it would have
`
`been obvious to combine Seiler with either Perego or Narayanaswami.
`
`Eachof these failures provides an independent basis for denying Unified’s
`
`Petition in its entirety.
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`NXP-AST00156738
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 9 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`e graphics pipeline “operative to process data in a dedicated tile”
`
`Each challenged claim requires a graphics pipeline “‘operative to process
`
`data in a dedicated tile.” Unified’s Ground I asserts that Perego discloses this
`
`limitation, while GroundII asserts that it 1s disclosed by Narayanaswami. But
`
`Unified’s assertions are wholly unsupported: Unified has identified no claim
`
`construction for this term, and it has failed to identify any evidence that either
`
`Narayanaswamior Perego discloses any such pipeline. Instead, Unified merely
`
`argues that the purported pipelines are “assigned”to or “own”particulartiles,
`
`without actually addressing whether they are “operative to process data in a
`
`dedicated tile” as required by each challenged claim.
`
`This failure is yet another independent reason for denying the Petition in its
`
`entirety.
`
`e “a two dimensionalpartitioning of memory”
`
`Finally, challenged dependent claims 2 and 3 each require “a two
`
`dimensional partitioning of memory.” Unified’s GroundI asserts that this
`
`limitation is taught by Perego, but improperly relies on Perego’s dividing of a
`
`graphical rendering surface, not of amemory. This failure of proof provides
`
`another reason the Petition should be denied with respect to challenged claims 2
`
`and 3.
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`NXP-AST00156739
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 10 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`Il.
`
`The ’945 Patent Discloses Improved Graphics Pipelines
`
`The ‘945 Patentis entitled “Dividing Work Among Multiple Graphics
`
`Pipelines Using a Super-Tiling Technique”and describes a “graphics processing
`
`circuit” consisting of multiple graphics pipelines on the same chip.
`
`When multiple graphics pipelines operate in parallel, an important goal for
`
`efficient graphics processing is “load balancing,” which meansall of the graphics
`
`pipelines remain busy and nonelay idle, such that the graphics processing unit can
`
`produce an image as quickly as possible. (See Hart Decl.' § 16.)
`
`The ‘945 Patentillustrates such parallel graphics pipelines in Figure 2,
`
`which has been reproduced below, and annotated using a red rectangle to identify
`
`one of the plurality graphics pipelines:
`
`' AdvancedSilicon is providing the Declaration of John C. Hart, Ph.D. In Support
`
`Of Patent Owner Advanced Silicon Technologies LLC’s Preliminary Response as
`
`Exhibit 2001.
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`NXP-AST00156740
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 11 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 11 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`AQ
`
`|
`SCAN
`CONVE
`RTER|
`
`Md
`
`KEND
`CIRCUITRY
`
`CIRCUITRY
`BO
`
`FIG. 5
`
`As depicted above, a graphics pipeline may contain front-end circuitry. Such
`
`front-end circuitry “generates the pixel data 36 by performing, for example,
`
`clipping, lighting, spatial transformations, matrix operations and rasterizing
`
`operations on the primitive data.” (945 Patent’ at 4:39-42.) For example, the
`
`front end circuitry would convert the vertices of a triangle from their 3-D XYZ
`
`positions on the sphere to their corresponding 2-D XY positions on the display
`
`screen, as Shown below. The “‘rasterizing operations” include computing vertex
`
`values useful for the next scan converter stage. (See Hart Decl. ¥ 18.)
`
`* Unified previously provided the ’945 Patent as Exhibit 1001.
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`NXP-AST00156741
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`
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`The graphics pipeline may also include a scan converter. “The scan
`
`converter 37 of the first graphics pipeline 101 receives the pixel data 36 and
`
`sequentially provides the position (e.g. x, y) coordinates 60 in screen space of the
`
`pixels to be processed by the back end circuitry 39[.]” (945 Patent at 4:45-48.)
`
`For example, as shown below, a scan converter accepts a triangle described by
`
`three vertices and produces a collection of pixels designedto fill the triangle. (See
`
`Hart Decl. 4 19.)
`
`The graphics pipeline may also include back-end circuitry. “Back end
`
`circuitry 39 may include, for example, pixel shaders, blending circuits, z-buffers or
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`NXP-AST00156742
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`any other circuitry for performing pixel appearance attribute operations(e.g. color,
`
`texture blending, z-buffering) on those pixels located, for example,in tiles...”
`
`(945 Patent at 4:66-5:3.) As illustrated below, the back end circuitry determines
`
`(See Hart Decl. { 20.)
`
`the colors of the pixels produced by the scan converter.
`
`
`
`In order to provide better load balancing of the available graphics pipelines,
`
`the ‘945 Patent divides the screen up intotiles (below left), such that each tile can
`
`be assigned to one graphics pipeline for graphics processing. For example, as
`
`illustrated in below right, tiles shaded in red are assigned to one graphics pipeline
`
`while tiles shaded in blue are assigned to the other. (See Hart Decl. 21.)
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`
`
`Asillustrated below, the graphics pipelines are in communication with a
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`NXP-AST00156743
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`Case IPR2016-01060
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`memory controller, which is operative to transfer pixel data between each of the
`
`pipelines and a shared memory. For example, as depicted below, memory
`
`controller 46 accepts pixels 43 and 44 generated by back end circuitry A 39 and B
`
`42 and writes pixels from both sources into the same graphics memory. This
`
`memory controller 46 may also manage the transfer of pixel data 49 and 50 from
`
`the shared graphics memory to the display 51 and back to the pipelines. (Hart
`
`Decl. ¥ 22.)
`
`GRAPHICS
`PROCESSING E!
`CIRCUIT
`i
`
`BACK END
`
`
`
`
`
`CIRCUITRY A
`
`
`
`49
`
`
`
`i590
`
`ve
`Ft
`
`mu|
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`GRAPHICS
`MEMORY
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`| DisPLay Liss
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`FHS. 2
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`Ill. Unified’s Petition
`
`Unified’s Petition asserts the following Grounds:
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`NXP-AST00156744
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`
`
`
`1-3, 9, 10, and 21
`§ 103(a)
`Seiler and Perego
`I
`
`
`
`
`
`
`
`
`Il
`
`Narayanaswamiand Seiler
`
`§ 103(a)
`
`1,9, 10, and 21
`
`These Groundsoverlap substantially, with each Ground challenging claims
`
`1,9, 10, and 21. Despite this redundancy, United has not even asserted, much less
`
`established, the required meaningful distinction between its overlapping Grounds.
`
`Therefore, as a threshold matter, a redundancy rejection is appropriate. See, e.g.,
`
`ScentAir Techs., Inc. v. Prolitec, Inc., 1PR2013-00180, Paper 18 at 3 (PTAB Aug.
`
`26, 2013) (“To avoid a determination that a requested ground of review is
`
`redundant of another requested ground,a petitioner must articulate a meaningful
`
`distinction.”); LaRose Industries, LLC, et al. v. Cipriola Corp., (PR2013-00120,
`
`Paper 20 at 4 (PTABJul. 22, 2013).
`
`A.
`
`The Challenged Claims
`
`Unified challenges independent claim 1, its dependent claims 2-3, 9, 10, and
`
`independent claim 21. Asillustrated by exemplary claim | reproducedin full
`
`below, each challenged claim describes a graphics processing circuit having at
`
`least two graphics pipelines, at least one of which can “process data in a dedicated
`
`tile.” The claims additionally require a “memory controller” that is operative “to
`
`transfer pixel data between each of”the first pipeline, the second pipeline, and a
`
`NXP-AST00156745
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`Case IPR2016-01060
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`memory shared by the two. The claims further require that the pipelines and the
`
`memory controller be on the “same chip.”
`
`L.
`
`at
`
`A graphics processing circuit, comprising:
`
`least
`
`two graphics pipelines on the same chip
`
`operative to process data in a corresponding set of tiles of a
`
`repeating tile pattern corresponding to screen locations, a
`
`respective one of
`
`the at
`
`least
`
`two graphics pipelines
`
`operative to process data in a dedicatedtile; and
`
`a memory controller on the chip in communication
`
`with the at least two graphics pipelines, operative to transfer
`
`pixel data between each of a first pipeline and a second
`
`pipeline and a memory shared amongthe at least two graphics
`
`pipelines;
`
`wherein the repeating tile pattern includes a horizontally
`
`and vertically repeating pattern of square regions.
`
`(945 Patent at claim | (emphasis added); see also claims 2-3, 9, 10, 21.)
`
`Also relevant to this Preliminary Response are the additional limitations of
`
`dependent claim 2. Challenged claim 2 depends from claim | and adds the
`
`requirement of a partitioning of memory:
`
`2.
`
`The graphics processing circuit of claim 1, wherein
`
`the square regions comprise a two dimensionalpartitioning of
`
`memory.
`
`(945 Patent at claim 2.)
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`NXP-AST00156746
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`

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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 17 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`B.
`
`The Asserted References
`
`1,
`
`Narayanaswami
`
`Narayanaswami’ is directed to a graphics processing circuit and in
`
`particular, a method and apparatus for managing a graphical workload across
`
`multiple processors. (See Hart Decl. §[ 30-32.) Narayanaswamiis designed to
`
`provide a “computer graphics systems” capable of rendering multiple objects into a
`
`frame buffer with the purpose of displaying those objects as quickly as possible.
`
`(Narayanaswami at 1:15-17.) (See Hart Decl. 99 31 and 33.) Narayanaswami was
`
`purportedly designed to respond to a rendering process that had become “more
`
`complex and computationally intensive as users demand more detailed results
`
`using more objects rendered more quickly, including providing realtime motion,
`
`while using more computationally intensive processing techniques suchascolor,
`
`texture, lighting, transparency and other rendering techniques.” (/d. at 1:17-24.)
`
`(See Hart Decl. { 32.)
`
`Narayanaswamidescribes graphics adapter processors 220, depicted in Fig.
`
`| below. (See Hart Decl. 9 34.) Unified asserts that each of these processors is one
`
`of the claimed “graphics pipelines.”(Pet. at 61.)
`
`* Unified previously provided the Narayanaswamireference as Exhibit 1004.
`
`10
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`NXP-AST00156747
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`
`
`
`
`
` $
`
`
`
`
`ou
` ADAPTER
`
`
`
`- ‘
`nw) PROCESSOR
`|
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`
`ee
`
`
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`=FRAMEBUFFER
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`
`on
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`| Gaaracs =e
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`| OUTPUT DEVICES)
`
`GRAPHICS
`aoAPTEg
`
`FIG. 1
`
`
`
`Narayanaswamidescribes (and illustrates in Fig. 6 below) the preferred
`
`method steps to be performed by each processor: “FIG. 6 is a flowchart illustrating
`
`a preferred method for each processor to handle the graphics workload while
`
`determining ownership of pixels or regions. (See Hart Decl. § 35.) This process
`
`may be executed concurrently and in parallel by all processors.” (Narayanaswami
`
`at 6:66 — 7:3.) (See Hart Decl. § 35.)
`
`il
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`NXP-AST00156748
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 19 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 19 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`{ omar J
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`As depicted in Figure 6 and the accompanying description, each
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`Narayanaswami processorprocessesall pixels, whether they are in a particular
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`region or not. (Narayanaswami at 7:21-28.) (See Hart Decl. 9 36.) Toillustrate,
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`step 610 of Narayanaswami requires each processor to scan convert the subobject.
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`(See id.) Narayanaswami describes the processor as completing this step before
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`determining which pixels are “owned by the processor,” resulting in the processor
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`scan converting and processingall of the pixels, not just those in a particular
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`region:
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`12
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`NXP-AST00156749
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 20 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 20 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`In step 615, the subobject is then scan converted into
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`pixels, In step 620, each pixel is checkedto see if it is owned by
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`the processor by comparing the identifier of the processor with
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`the identifier stored in the pixel ownership buffer or the region
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`ownership list for that pixel.
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`If yes in step 620, indicating that the processor owns the
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`pixel, then the processer processesthe pixel.
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`(Id. at 7:21-28.) (See Hart Decl. { 36.)
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`2.
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`Perego
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`Perego’ discloses a system architecture that “provid{es] scalability option to
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`higherlevels of aggregate memory bandwidth.” (Perego at 2:53-57.) (See Hart
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`Decl. § 27.) As illustrated In Figure 3 below, in Perego, “a system has been
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`described that provides multiple discrete memory modules coupled to a common
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`memory controller. Each memory module includes a computing [or ‘rendering’ |
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`engine and a shared memory.” (Perego, col. 7:35-42.
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`) (See Hart Decl. § 26.)
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`Unified asserts that each engine is one of the claimed “graphics pipelines.”(E.g.,
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`Pet. at 37).
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`“ Unified previously provided the Perego reference as Exhibit 1003.
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`13
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 21 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 21 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`
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`Perego’s scalable architecture is the key feature of Perego’s invention. (See
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`Hart Decl. § 27.) Asa result, Perego does not use a memory shared among
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`different pipelines operating in parallel. (See id. { 28.) Rather, as illustrated in
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`Figure 3 above, each rendering engine 312 has a dedicated memory thatit shares
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`with the CPU/Memory Controller 302 but not with any other rendering engines
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`312. (E.g., Perego at 4:53-57.) (See Hart Decl. | 26.) Perego’s use of dedicated
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`memory for each rendering engine is the essence of Perego’s purported innovation:
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`by having a dedicated memory for each rendering engine/module, Peregois able to
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`achieve its goal of providing a scalable modular system in which individual
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 22 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 22 of 55
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`Case IPR2016-01060
`U.S. Patent No. 8,933,945 B2
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`engines/modules can be added or removed as needed. (See Perego at 2:61-65.)
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`(See Hart Decl. § 27.)
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`In addition to teaching away from the claimed shared memory, Perego also
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`fails to disclose a pipeline that is “operative to process data in a dedicated tile” as
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`required by each of the challenged °945 Patent claims. (See Hart Decl. 4] 28-29.)
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`Although Perego states generally that certain tiles may be assignedto a particular
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`rendering engine, Perego does not describe how this assignment and any
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`corresponding processing is done.
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`(See Perego at 5:19-27.) (See Hart Decl. 4 29.)
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`Perego does not describe a system in which a rendering engine only processes the
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`pixels in the particular tile or tiles assigned to that engine.
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`(Seeid.)
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`Noris such a system inherentin light of the assignment described in Perego
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`because such assignment can be achieved without the rendering engines only
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`processing the pixels in a particular tile. (See Hart Decl. § 30.) For example, as
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`described below, the Narayanaswamireference describes a system in which the
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`rendering of certain tiles is assigned to a particular processor, but each processor
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`processes pixel data that is not within the tiles assigned to that processor. (See id.)
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`3.
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`Seiler
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`Unified’s Grounds I and II attempt to rely on the Seiler reference to provide
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`the claim limitations that United concedes are not disclosed by Perego or
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`Narayanaswami, including the claimed “memory controller,” the claimed “memory
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 23 of 55
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`Case IPR2016-01060
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`shared amongtheat least two graphic pipelines,” and the pipelines and memory
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`controller being “on a same chip.” (Pet. at 17-18 and 68-69.)
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`Seiler’ discloses a specialized system used for volumerendering, e.g. for
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`medical data imaging of CT and MRIscan data stored as a 3-D voxelarray. (See
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`e.g., Seiler {J 3 and 10-12.) While competitive graphics processors like
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`Narayanaswami would have used specialized circuity including a scan converter
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`and a texture unit (for example, Narayanaswamiat 1:22 and 38-39), Seiler used an
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`alternative to scan conversion knownas ray casting. (Seiler 76.) (See Hart Decl. {
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`23.) Ray casting determines for each pixel, which triangle(s) affect it, and is
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`viewedas the inverse approach of scan conversion. (See Hart Decl. { 23.)
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`Seiler describes a “memory interface 210 [that] implementsall accesses to
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`the rendering memory 160, arbitrates the requests of the bus logic 220 and the
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`controller 400, and distributes array data across the modules and the rendering
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`memory 160 for high bandwidth access and operation.” (Seiler { 16.) Seiler does
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`not describe memory interface 210 as transferring processed pixel data (or any
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`data) from one pipelme to another. (See Hart Decl. { 25.)
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`For example, Seiler’s Figure 2 (reproduced below) shows that memory
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`interface 210 acts as an interface for data transfers between rendering memory 160,
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`° Unified previously providedthe Seiler reference as Exhibit 1002.
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 24 of 55
`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 24 of 55
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`Case IPR2016-01060
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`on the other hand, and either the bus logic 220 or controller 400, on the other.
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`Figure 2 and the Seiler reference does not describe or depict memory interface 210
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`as transferring data from one pipeline to another. (See Hart Decl. {] 25.)
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`Pa!Burs
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`210
`220
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`FIG, 2
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`IV.
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`The Correct Claim Construction of Material Disputed Terms
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`A.
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`The Controlling Claim Construction Standard
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`The broadest reasonable interpretation standard applies in an inter partes
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`review of a patent that, like the ‘945 Patent, will not expire prior to the Final
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`Written Decision. 37 C.F.R. §100(b); Office Patent Trial Practice Guide, 77 Fed.
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`Reg. 48,756, 48,766 (Aug. 14, 2012). Applying the broadest reasonable
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`interpretation, claim terms are given their ordinary and customary meaning, as
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 25 of 55
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`would be understood by a person of ordinary skill in the art at the time of the
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`invention, in light of the language of the claims, the specification, and the
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`prosecution history of the record. #.2., Wowza Media Sys., LLC v. Adobe Systems
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`Inc., IPR2013-00054, No. 12 at 5 (PTAB Apr. 8, 2013); Intellectual Ventures
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`Memt, LLC, v. Xilinx, Inc., 1PR2012-00019, Paper 33 at 9 (PTAB February 10,
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`2014); see also Phillips v. AWH Corp., 415 F.3d 1303, 1313-1317 (Fed. Cir. 2005)
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`(en banc); Hill-Rom Services, Inc. v. Stryker Corporation, 755 F.3d 1367, 1371
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`(Fed. Cir. 2014).
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`Underthis test, “[t]here is a “heavy presumption’ that a claim termcarriesits
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`ordinary and customary meaning.” See Intellectual Ventures, IPR2012-00019,
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`Paper 33 at 9; Wowza, IPR2013-00054, No. 12 at 6; Universal Remote Control,
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`Inc. v. Universal Electronics, Inc., IPR2013-00127, Paper 32 at 6 (PTAB June 30,
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`2014). This heavy presumption is overcome in specific and limited circumstances:
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`a claim term may be construed contrary to its ordinary meaning only wherethereis
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`clear and unambiguous evidencethat the patentee, as lexicographer, provided a
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`special definition for the claim term, or the patentee otherwise disavowedthefull
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`scope of the claim term either in the specification or during prosecution. Lriccson,
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`Inc. v. Intellectual Ventures I LLC, 1PR2014-00921, Paper 8, at 8 (PTAB Dec.16,
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`2014); Becton, Dickinson and Co. v. One StockDug Holdings, LLC, 1PR2013-
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 26 of 55
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`Case IPR2016-01060
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`00235, Paper 30 at 6 (PTAB Sept. 25, 2014); see also Aventis Pharma S.A.v.
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`Hospira, Inc., 675 F.3d 1324, 1330 (Fed. Cir. 2012); Hill-Rom, 755 F.3d at 1371.
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`B.
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`The Only Material Claim Construction Issue Facing the Board Is
`The Correct Construction of “memory controller”
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`The Board should only construe terms to the extent such construction is
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`necessary to resolve a controversy material to the Petition. See, e.g., Wellman, Inc.
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`v. Eastman Chem. Co., 642 F.3d 1355, 1361 (Fed. Cir. 2011); Vivid Techs., Inc. v.
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`Am. Sci. & Eng’g, Inc., 200 F.3d 795, 803 (Fed. Cir. 1999). Based on the Petition
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`and this Response, the only material claim construction issues currently facing the
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`Board concerns the terms “memory controller.”
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`1,
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`The correct construction of “memory controller”
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`The claimed “memory controller” is a limitation of every challenged claim.
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`For example, each challenged claim requires:
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`a memory controller ... operative to transfer pixel data between each
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`of a first pipeline and a second pipeline and a memory shared among
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`the at least two graphics pipelines.
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`(945 Patent at independent claim 1, independent claim 21.)
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`Consistent with the plain and ordinary meaning of the foregoing explicit
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`claim language, the claimed “memory controller” should be construed to mean a
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`“logic circuit operative to transmit and receive processed pixel data to and from the
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`Case 6:22-cv-00466-ADA-DTG Document 49-1 Filed 11/28/22 Page 27 of 55
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`Case IPR2016-01060
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`first pipeline, the second pipeline, and the first and second pipelines’ shared
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`memory.”
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`2.
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`Unified provides no construction for “memory controller”
`and no support for its application of “memory controller”
`to Seiler
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`The clatmed “memory controller” is a key limitation; indeed, Unified relies
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`on Seiler primarily because it admits that the “memory controller’ is missing from
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`each ofits primary references, Perego and Narayanaswami. (Pet. at 17 and 58.)
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`Despite this focus on “memory controller,” Unified’s Petition fails to provide any
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`claim construction for the term. Instead, Unified just generally asserts that the
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`term should be givenits “broadest reasonable interpretation” without identifying
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`what Unified contendsthat “broadest reasonable interpretation”actually is. (Pet. at
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`19.) This failing alone meansthat Unified has not met its burden of proof and
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`Unified’s Petition should be denied. See Jiawei Tech. (HK) Lid. v. Richmond,
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`IPR2014-00938, Paper 20 at 17 (PTAB Dec. 16, 2015) (it “is Petitioner’s burden to
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`explain how the challenged claims are to be construed and how they read on the
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`priorar