Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 1 of 25
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 1 of 25
`
`EXHIBIT 11
`EXHIBIT 11
`
`

`

`(12) United States Patent
`Sadowski et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 7,804,435 B2
`Sep. 28, 2010
`
`USOO7804435B2
`
`(54) VIDEO DECODER WITH REDUCED POWER
`CONSUMPTION AND METHOD THEREOF
`(75) Inventors: Greg Sadowski, Cambridge, MA (US);
`it's sing:M (US); Paul
`s
`
`(73) Assignee: ATI Technologies ULC, Markham,
`Ontario (CA)
`
`(*) Notice:
`
`-
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 11/469,335
`(22) Filed:
`Aug. 31, 2006
`
`(65)
`
`Prior Publication Data
`US 2008/OO55119A1
`Mar. 6, 2008
`(51) Int. Cl.
`(2006.01)
`H03M I/2
`(52) U.S. Cl. ........ grrrrr. 341A155
`(58) Field of Classification Search ................. 341/155,
`341/157, 158; 3.75/222, 219, 316, 345
`See application file for complete search history.
`References Cited
`U.S. PATENT DOCUMENTS
`
`(56)
`
`1/1998 Redford et al.
`5,711,672 A
`2f1998 Mittal et al.
`5,719,800 A
`5,734,779 A * 3/1998 Okino ......................... 386/38
`6,332,168 B1
`12/2001 House et al.
`6,477,654 B1
`1 1/2002 Dean et al.
`6,795,930 B1
`9/2004 Laurenti et al.
`6,957,422 B2 10/2005 Hunt
`6,978,085 B1* 12/2005 Maeda et al. ............... 386, 112
`7,174,392 B2
`2, 2007 Tervo
`
`aWe ca.
`
`7,227,847 B2
`6/2007 Gluck
`7,372,999 B2 *
`5/2008 Oneda et al. ................ 382,232
`7401,240 B2
`7/2008 Heller et al.
`S.85.7 A. 1929 it. Fa
`2004/00399.54 A1
`2/2004 White et al.
`2004/O136596 A1* 7/2004 Oneda et al. ................ 382,232
`2004/0158748 A1* 8, 2004 Ishibashi et al. ............ T13,300
`2004/O158752 A1
`8, 2004 Borza et al.
`2004/026831.6 A1 12/2004 Fisher et al.
`2005/0081107 A1
`4/2005 DeWitt, Jr. et al.
`2005/02O0627 A1
`9/2005 Desylva
`2005/0232136 A1* 10/2005 Kwak ......................... 370,208
`2005/0273636 A1 12/2005 Grobman
`2006/0044468 A1* 3/2006 Chowdhury et al. ........ 348/465
`2006, O123262 A1
`6/2006 Bullman
`(Continued)
`OTHER PUBLICATIONS
`International Search Report and Written Opinion; International
`Application No. PCT/US2007/077346; dated Aug. 14, 2008.
`Primary Examiner Brian Young
`(74) Attorney, Agent, or Firm Vedder Price P.C.
`(57)
`ABSTRACT
`
`A video decoder (10) with reduced power consumption
`includes a power management controller (45) that is operative
`to select one of a plurality of different power consumption
`states for a video decoder (10), and, in response to the deter
`mination, vary power consumption of at least one operational
`portion of the video decoder(10). In addition, in one example,
`a method (200) for reducing power consumption for a video
`decoder (10) includes determining input stream encoding
`description data (34) to select one of a plurality of different
`power consumption states for a video decoder (10) and, in
`response to the determination, varying power consumption of
`at least one operational portion of the video decoder (10).
`
`26 Claims, 12 Drawing Sheets
`
`
`
`BATTERY-WRE
`EWICE
`
`10
`
`25
`CODE: APPLICATION
`PROFILEATA
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 2 of 25
`
`MAMAGEMENT
`CONTROLLER
`
`ALCATION
`
`APLCATION
`RFILEATA
`
`S CODE AND
`APPLICATION
`PROFILEATA
`FROM
`WRELESS
`NETWORK
`
`2
`
`CODE; APPLICATION CODE: APPLICATION
`proFILEATA
`ROFIEDATA
`Y
`
`CONTROLLER
`
`18
`
`54
`
`56
`
`XCWR
`
`114
`
`30
`
`
`
`3 5
`
`ENGINE
`
`MCLK
`
`94
`
`MEMORY
`CONTROL
`MORY
`MEMORY
`CONTROLLER
`
`PLLBLOCK
`
`SYSTEM
`
`OSCLATOR 40
`
`4s
`
`CRYSTAL
`
`MCLKPROG
`OWERSUPLY PROs
`
`GUWITHOWER
`MANAGEMENT
`
`72
`
`68
`
`SENERAL PURPOSEld
`
`OWER SUPPLY
`
`s
`
`106
`
`OWERSUPLYSEt
`
`WLTAGE
`GENERATOR
`
`POWERSUPPLY
`WOLTASE
`
`

`

`US 7,804,435 B2
`Page 2
`
`U.S. PATENT DOCUMENTS
`2006, O136764 A1
`6/2006 Munguia
`2007/0064159 A1
`3f2007 Kim et al. ................... 348,730
`
`2008/00598.23 A1
`
`3/2008 Balatsos et al.
`
`* cited by examiner
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 3 of 25
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 1 of 12
`
`US 7,804,435 B2
`
`
`
`BATTERY-POWERED
`DEVICE
`
`25
`CODE: APPLICATION
`
`CODE: APPLICATION CODE: APPLICATION S CODE AND
`PROFILE DATA
`PROFILE DATA
`APPLICATION
`
`APPLICATION
`PROFILE DATA
`
`CONTROLLER
`
`WIRELESS
`NETWORK
`
`POWER
`MANAGEMENT
`CONTROLLER
`
`DLE
`REGISTER
`
`3D
`ENGINE
`
`MEMORY
`
`MEMORY
`
`OSCILLATOR A
`
`SCLKPROG
`
`98
`SYSTEMCLOCKREG
`
`64
`
`SYSTEM CLOCKREG
`
`CRYSTAL
`
`MCLKPROG
`POWER SUPPLY PROG
`
`GPUWITHPOWER
`MANAGEMENT
`
`GENERAL PURPOSEO
`
`POWER SUPPLY
`WOLTAGE INPUT
`
`POWER SUPPLYSET
`
`WOLTAGE
`GENERATOR
`
`POWER SUPPLY
`WOLTAGE
`
`FIG. 1
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 4 of 25
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 2 of 12
`
`US 7,804,435 B2
`
`
`
`EXECUTE CODE INCLUDINGAPPLICATION
`PROFILE DATA IDENTIFYING USAGE OF
`PORTIONS OF PROCESSORDURING
`RUNTIME
`
`21 O
`
`IN RESPONSE TO APPLICATION PROFILE
`DATA IDENTIFYING USAGE OF PORTIONS OF
`THE PROCESSOR, CONTROL POWER
`CONSUMPTION OF IDENTIFIED PORTIONS OF
`PROCESSOR
`
`220
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 5 of 25
`
`FIG. 2
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 3 of 12
`
`US 7,804,435 B2
`
`START
`
`PROFILE APPLICATION USAGE OF
`PORTIONS OF PROCESSOR USED
`DURING EXECUTION OF APPLICATION
`CODE BASED ON IDLE BITS
`
`STORE APPLICATION PROFILE DATA
`IDENTIFYING USAGE OF PORTIONS OF
`PROCESSOR WITH APPLICATION
`CODE
`
`APPLICATION STILL RUNNING?
`
`NO
`
`END
`
`
`
`
`
`
`
`YES
`
`310
`
`320
`
`330
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 6 of 25
`
`FIG. 3
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 4 of 12
`
`US 7,804,435 B2
`
`
`
`ACCESS APPLICATION PROFILE
`DATAN APPLICATION
`
`410
`
`DETERMINE PROCESSOR PORTION
`USAGE BY APPLICATION BASED ON
`APPLICATION PROFILE DATA
`
`42O
`
`CONTROL POWER CONSUMPTION
`OF PROCESSOR PORTIONS BASED
`ON PROCESSOR PORTION USAGE
`
`430
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 7 of 25
`
`FIG. 4
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 5 of 12
`
`US 7,804,435 B2
`
`RECORD IDLE REGISTER VALUES AND
`CLOCK/VOLTAGE REGISTER VALUES
`DURING APPLICATION RUNTIME
`
`51O
`
`TRANSFERDLE REGISTER VALUES AND
`CLOCK/VOLTAGE REGISTER VALUES AS
`APPLICATION PROFILE DATA TO OFFLINE
`STORAGE
`
`520
`
`APPLICATION PROFILE DATA
`ASSOCATED WITH APPLICATION?
`
`
`
`STORE APPLICATION PROFILE DATA WITH
`APPLICATION
`
`FIG. 5
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 8 of 25
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 6 of 12
`
`US 7,804,435 B2
`
`600
`
`610
`
`IDENTIFY CALLS TO PROCESSOR
`NAPPLICATION DURING RUNTIME
`
`MAP CALLS TO PROCESSOR TO
`SPECIFIC PORTIONS OF THE
`PROCESSOR
`
`62O
`
`
`
`STORE CALLS TO PROCESSORPORTIONS AS
`APPLICATION PROFILE DATA TO OFFLINE STORAGE 630
`
`
`
`
`
`
`
`APPLICATION PROFILE DATA
`ASSOCIATED WITH APPLICATION?
`
`
`
`640
`
`NO
`
`STORE APPLICATION PROFILE DATA IN
`APPLICATION
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 9 of 25
`
`FIG. 6
`
`END
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 7 of 12
`
`US 7,804,435 B2
`
`
`
`BATTERY-POWERED
`DEVICE
`
`APPLICATION USAGE PROFILER
`CO-PROCESSOR
`
`APPLICATION
`
`CONTROLLER
`
`\ IDENTIFYING
`DATA FROM
`WIRELESS
`NETWORK
`
`-
`POWER
`80 N MANAGEMENT
`CONTROLLER
`
`- - -
`
`2D
`ENGINE
`
`3
`ENGINE
`
`MEMORY
`MEMORY CONTROL
`CONTROLLER
`MEMORY
`
`OLE BITS
`
`70
`
`PBLOCK
`
`DLE
`REGISTER
`
`SYSTEM
`PL
`
`OSCILLATOR
`
`96
`
`SCLKPROG
`
`MCLKFREQ
`SCLKFREQ 104
`98
`64
`SYSTEMCLOCKREG
`SYSTEM CLOCKREG
`
`CRYSTAL
`
`MCLKPROG
`
`POWER SUPPLY PROG
`GPUWITHPOWER
`MANAGEMENT
`
`68
`
`GENERAL PURPOSE/O
`
`72
`
`66
`
`POWER SUPPLY
`WOLTAGE INPUT
`
`POWER SUPPLY SET
`WOLTAGE
`POWESSPY
`GENERATOR
`
`FIG. 7
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 10 of 25
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 8 of 12
`
`US 7,804,435 B2
`
`VOLTAGE CONTROL
`
`CLOCK
`CONTROL
`
`
`
`
`
`
`
`
`
`870
`CLOCKGENERATOR
`
`POWER SUPPLY
`
`829
`
`850
`
`862
`
`858
`
`
`
`MCLK
`
`UWD
`WOLTAGE
`866
`
`DRAM
`WOLTAGE
`
`878
`
`LEVEL
`INFORMATION
`
`89
`RECEIVE INPUT
`STREAM FROM
`WIRELESS
`NETWORK
`
`MANAGEMENT
`CONTROLLER
`
`VIDEO
`PROCESSING
`UNIT (VPU)
`
`INTERFACE
`
`WMBUS2
`
`MEMORY
`CONTROLLE
`R
`
`
`
`
`
`
`
`
`
`al
`
`REVERSE ENTROPY
`PROCESSOR
`
`DECODED
`STREAM
`
`MACROBLOCK
`PROCESSOR
`
`DECODER
`
`FIG. 8
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 11 of 25
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 9 of 12
`
`US 7,804,435 B2
`
`START
`
`910
`DETERMINE IF MORE THAN ONE INPUT STREAMAND
`INCREASE POWER CONSUMPTION OF AT LEAST ONE -
`PORTION OF THE VIDEODECODER IN RESPONSE TO THE
`DETERMINATION
`
`
`
`DETERMINE INPUT STREAMENCODING DESCRIPTION DATA
`TO SELECT ONE OF A PLURALITY OF DIRFERENT POWER
`CONSUMPTION STATES FOR THE WIDEO DECODER
`
`920
`
`VARY POWER CONSUMPTION OF AT LEAST ONE
`OPERATIONAL PORTION OF THE VIDEO DECODING IN
`RESPONSE TO THE DETERMINATION
`
`930
`
`FIG. 9
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 12 of 25
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 10 of 12
`
`US 7,804,435 B2
`
`
`
`START
`
`ANALYZE HEADER INFORMATION TO OBTAIN PROFILE AND
`LEVEL INFORMATION ON A PER BLOCK, SLICE, FRAME, OR
`STREAM BASIS
`
`1010
`
`USE POWER MANAGEMENT CONTROL TABLE TO OBTAIN
`CLOCK SETTINGS AND POWER SUPPLY SETTINGS FOR
`VARIOUS DECODER CIRCUITS
`
`CONTROL CLOCK GENERATOR AND POWER SUPPLY TO
`PROVIDE LEVELS FROM TABLE
`
`1030
`
`FIG 10
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 13 of 25
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 11 of 12
`
`US 7,804,435 B2
`
`WOLTAGE CONTROL
`
`1150
`CLOCK
`CONTROL
`WCLK
`
`CLOCK GENERATOR
`
`POWER
`MANAGEMENT
`CONTROLLER
`(HOST
`DRIVER)
`HOST
`PROCESSOR
`POWER
`CONTROL
`AND STATUS
`
`1130
`1140
`
`LEVEL
`INFORMATION
`
`
`
`845
`
`RECEIVE INPUT
`STREAM FROM
`WIRELESS
`NETWORK
`894
`
`815
`
`Y INPUT
`
`STREAM
`
`
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 14 of 25
`
`
`
`DRAM
`WOLTAGE
`
`
`
`858
`
`854
`
`MCLK
`
`UWD
`WOLTAGE
`66
`N
`
`
`
`
`
`
`
`882
`
`880
`
`WMBUS2
`
`MEMORY
`INTERFACE
`
`MEMORY
`CONTROL
`
`WIDEO
`PROCESSOR
`UNIT (VPU)
`ENCODING
`DESCRIPTION 834
`
`844
`
`DECODED
`REVERSE ENTROPY | STREAM
`PROCESSOR
`
`MACROBLOCK
`PROCESSOR
`
`843
`DECODER
`
`FIG. 11
`
`811
`
`
`
`
`
`
`
`
`
`

`

`U.S. Patent
`
`Sep. 28, 2010
`
`Sheet 12 of 12
`
`US 7,804,435 B2
`
`HOSSESSTER 1204
`
`810
`
`
`
`SHARED
`REGISTER
`
`OUEUEO
`D. S.
`
`s OUEUE 1
`
`1200
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 15 of 25
`
`MEMORY
`READ/WRITE
`
`r
`
`1208
`
`MEMORY
`WRITE PORT
`
`\1210
`
`MEMORY
`READ PORT
`
`\1212
`
`BITSTREAM
`READ PORT
`
`\120s
`FIG. 12
`
`

`

`US 7,804,435 B2
`
`1.
`VIDEO DECODER WITH REDUCED POWER
`CONSUMPTION AND METHOD THEREOF
`
`RELATED CO-PENDINGAPPLICATION
`
`This is a related application of copending application Ser.
`No. 1 1/469,326, entitled BATTERY-POWERED DEVICE
`WITH REDUCED POWER CONSUMPTION AND
`METHOD THEREOF filed on Aug. 31, 2006, having as
`inventors Aris Balatsos et al., and owned by instant assignee
`and incorporated by reference in its entirety.
`
`10
`
`FIELD OF THE INVENTION
`
`The invention relates generally to video decoders and,
`more particularly, to a video decoder with reduce power con
`Sumption and method thereof.
`
`15
`
`BACKGROUND OF THE INVENTION
`
`2
`FIG. 3 is one example of a method of determining identi
`fying data for use in controlling power consumption depicting
`one embodiment of the invention;
`FIG. 4 is one example of a method of controlling power
`consumption depicting one embodiment of the invention;
`FIG. 5 is one example of a method of determining identi
`fying data for use in controlling power consumption depicting
`one embodiment of the invention;
`FIG. 6 is one example of a method of determining identi
`fying data for use in controlling power consumption depicting
`one embodiment of the invention;
`FIG. 7 is one example of a battery-powered device depict
`ing one embodiment of the invention;
`FIG. 8 is one example of a video decoding system depict
`ing one embodiment of the invention;
`FIG. 9 is one example of a method of controlling power
`consumption depicting one embodiment of the invention;
`FIG. 10 is one example of a method of controlling power
`consumption depicting one embodiment of the invention;
`FIG. 11 is one example of a video decoding system depict
`ing one embodiment of the invention; and
`FIG. 12 is a block diagram illustrating one example of a
`decoder that can be controlled as described herein.
`
`25
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`Despite improvements in rechargeable battery technology,
`battery capability continues to limit performance of mobile
`electronic devices. In particular, limited energy capacity
`results in relatively short device run-times, of, for example,
`only a few hours, between recharging or Switching batteries.
`In addition, functional integration, Such as in the example of
`integrating camera functions onto a cellular telephone hand
`set, results in popular multiple function devices yet may
`increase energy consumption. Video encoding/decoding
`operations such as MPEG, H.264, VC-1 based encoding and/
`or decoding or other video coding circuits can consume lim
`ited battery power.
`Power conservation techniques may be used to compensate
`for battery limitations in battery-powered devices. For
`example, low power modes may be used to conserve powerby
`selectively shutting down certain components or functional
`blocks within components. Alternatively, power may be
`saved by reducing power Supply Voltages or clocking fre
`quencies. Typical low power modes are entered either by
`direct operator interaction, Such as by placing the device to
`low power mode, or by a triggering event. A triggering event
`may occur when, for example, the battery capacity drops
`below a certain threshold. Alternatively, a low power mode
`may be triggered when certain functional blocks in the device
`have not been used or accessed for some period of time. These
`triggering events may be useful for conserving battery power;
`however, each is reactive rather than proactive. That is, Sig
`nificant battery may be consumed prior to triggering. As a
`result, the triggering techniques may not be sufficient to pro
`vide Sufficient energy conservation in all cases. Since video
`decoders in battery-powered devices can consume significant
`energy, improved video decoders with reduce power con
`sumption and methods thereof would be desirable.
`
`Briefly, an apparatus employs a power management con
`troller, in response to a determination of encoding description
`data and varies power consumption of at least one operational
`portion of a video decoder. The apparatus may also include
`the decoder. In addition, in one example, a method for reduc
`ing power consumption for a video decoder includes deter
`mining input stream encoding description data to select one
`of a plurality of different power consumption states for a
`Video decoder and, in response to the determination, varying
`power consumption of at least one operational portion of the
`video decoder.
`In one example, a video decoder is disclosed with reduced
`power consumption. Power is proactively and automatically
`conserved prior to significant battery discharge and without
`operator intervention. Power consumption is varied in por
`tions of the video decoder in response to encoding character
`istics from an input data stream to minimize power consump
`tion while achieving required performance. Other advantages
`will be recognized by one of ordinary skill in the art.
`In another embodiment, a device includes a processor that
`is operative to process a data stream such as executable code,
`encoded video or other Suitable data stream, and has a plural
`ity of processor portions. The device further includes a power
`management controller coupled to the processorportions that
`controls power consumption of the processor portions based
`on information associated with or in the data stream. The
`information may include application profile data included
`with executable code that directly indicates usage/nonusage
`of portions of the processor or the data stream may have use
`data inherent in the stream, that indirectly identifies usage of
`the processorportions. In addition, in one example, a method
`for reducing power consumption for a battery powered device
`includes executing code that includes application profile data
`identifying usage of portions of a first processor during runt
`ime of an application; and, in response to the application
`profile data, controlling power consumption of the identified
`first processor portions during runtime. In addition, in one
`example, a battery-powered device includes memory that
`stores the code and a first processor coupled to the memory
`and operative to execute the code. The power management
`controller may be part of the processor or external thereto.
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`Case 6:22-cv-00466-ADA-DTG Document 46-12 Filed 09/12/22 Page 16 of 25
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention and the corresponding advantages
`and features provided thereby will be best understood and
`appreciated upon review of the following detailed description
`of the invention, taken in conjunction with the following
`drawings, where like numerals represent like elements, in
`which:
`FIG. 1 is one example of a battery-powered device depict
`ing one embodiment of the invention;
`FIG. 2 is one example of a method of controlling power
`consumption depicting one embodiment of the invention;
`
`

`

`US 7,804,435 B2
`
`10
`
`15
`
`25
`
`30
`
`35
`
`40
`
`45
`
`3
`The application profiling data may be generated by an appli
`cation developer and embedded as header information in the
`code or may be generated by the device the first time the
`application is run on the device, or at any other suitable time.
`In Such a case, it may be necessary to create header informa
`tion specific to a particular device or class of devices reflec
`tive of the differing capabilities and/or processors (orportions
`thereof). In this case, it may be desirable applications with
`embedded header information that is specific to a particular
`device (or class of devices). Alternatively, the header infor
`mation may include more than one header information por
`tions with each portion associated with a particular device (or
`class of devices). Inafurther alternative, the application could
`be transferred to a device without any header information but,
`instead, be transferred with associated (but separate) applica
`tion profile data. In such an embodiment, the application
`could be unchanged for a variety of devices (or classes of
`devices) while only device (or device class) specific applica
`tion profile data would vary between the variety of devices (or
`classes of devices).
`As such, a battery-powered device is disclosed with
`reduced power consumption wherein power is proactively
`and automatically conserved prior to significant battery dis
`charge and, if desired, without operator intervention. Portions
`of a processor included in the device are automatically iden
`tified for power consumption based on application runtime
`profiling. Power is conserved in the identified portions using
`any desired power saving method. The power consumption
`technique is useful for a wide variety of battery-powered
`devices. Other advantages will be recognized by one of ordi
`nary skill in the art.
`FIG. 1 is one example of a battery-powered device 10
`depicting one example of one embodiment of the invention.
`The battery-powered device 10 may be a handheld device or
`a non-handheld device. For purposes of illustration only, and
`not limitation, FIG. 1 illustrates an example where a data
`stream is considered executable code with header informa
`tion that includes application profile data. A later example
`will be set forth below where the data stream is an encoded
`video data stream. However it will be recognized that any
`suitable data stream and device may be employed. It should
`be recognized that while in many instances the “header infor
`mation' may be placed at or near the beginning of a data
`stream it could, in many instances, be placed elsewhere in the
`data stream.
`The battery-powered device 10 may have wireless capabil
`ity and/or non-wireless capability. The battery-powered
`device 10 may, for example, be a wireless telephone, a per
`Sonal computer, a digital assistant (such as a personal digital
`assistant—PDA), a digital entertainment/playback device, a
`radio communication device, a tracking device, a personal
`training device, a global positioning device, a camera, a video
`recorder, a video game controller, a television receiver, a
`digital video player, a printing device, a digital display, a
`combination thereof or any suitable device.
`The battery-powered device 10 includes a processor 15 and
`a memory 20 including application code 25 in any Suitable
`format. As used herein code or application can also include
`data if desired. The battery-powered device 10 may further
`include a wireless network interface including a wireless
`transceiver 30 operatively coupled to a controller 35. The
`battery-powered device 10 may further include additional
`memory 40, a crystal oscillator 45, and a voltage generator 50
`operatively to the processor 15.
`For purposes of illustration only, the processor 15 is shown
`as a graphics processing core (GPU) or multimedia process
`ing core. However, processors of other types, architectures,
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`and capabilities may be used as will be recognized by one
`skilled in the art. For example, a digital signal processor
`(DSP), microcontroller, central processing unit, baseband
`processor, co-processor, or any suitable processing circuit(s)
`may be used. In addition the processor 15 may be discrete
`logic, or any suitable combination of hardware, Software or
`firmware or any suitable structure. The processor 15 may be
`made up of several portions, or functional blocks. The por
`tions provide or control functions contributing to the function
`of the overall processor 15. The operating portions may
`include, but are not limited to, a 2D engine 52, a 3D engine 54,
`a memory controller 56, a phase-lock loop (PLL) circuit
`including system PLL 60 and memory PLL 62, clock fre
`quency registers including system clock register 64 and main
`clock register 66, a general purpose input/output registers 68,
`an idle bit register 70, and a power supply voltage input 72.
`The processor 15 further includes a power management con
`troller 80. The processor 15 may further include arithmetic
`units, on-chip memory, address decoders and encoders, video
`decoders and encoders, co-processors, and other portions as
`are known in the art.
`The operational instructions, such as executable code 25,
`or software, executed by the processor 15 are stored in
`memory 20 which may include any Suitable digital storage
`medium including, but not limited to, RAM, ROM, flash
`memory, hard disk drive, distributed memory Such as servers
`with memory on a network, CD-ROM or any suitable storage
`medium. It will be recognized that Such memory may be
`integrated with the controller or take any Suitable configura
`tion.
`The memory 20 stores application code 25 that is executed
`by the processor 15. The application code 25 may further
`include application profile data 84. Such as in headers of the
`code, identifying usage of portions, during code runtime,
`within the plurality of portions included in the processor 15.
`The application profile data 84 may provide usage informa
`tion including which portions of the processor 15 are active or
`are idle during execution of the code, how frequently various
`portions are active/idle or accessed/not accessed, and para
`metric settings associated with various portions of the pro
`cessor Such as clocking frequency and power Supply Voltage
`settings for the relevant portions of the processor. The appli
`cation profile data 84 is further defined and described below.
`The code 25 with application profile data 84 may be passed
`from the memory 20 to the processor 15 through the system
`bus 88, or any suitable link, for execution by the processor 15.
`For example, the application profile data 84 may be included
`with the code 25 as a header section. Alternatively, the appli
`cation profile data 84 may be associated with the code using
`pointers or may be associated with the code by any means
`recognized by one skilled in the art.
`The processor 15 may include a power management con
`troller 80. The power management controller 80 evaluates
`header information of a data stream and varies parametric
`settings of portions of the processor 15 to reduce power
`consumption of the processor 15 based on the header infor
`mation. In this example, the data stream includes executable
`code and header information that includes application profile
`data identifying which portions of the processor are exercised
`during runtime of the executable code. In an alternative or
`combined embodiment, the device processor 15 may include
`a video decoder, and the data stream includes encoded video.
`In such an example, described further below, the header infor
`mation in the encoded video is used by the power manage
`ment controller to determine which parametric settings of the
`video decoder are to be controlled. The encoded video stream
`need not include additional data, instead data inherent data in
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`example, reducing clocking frequency, reducing the operat
`ing power Supply Voltage, or increasing the transistor back
`bias Voltage are known to reduce power consumption during
`runtime. However, these parametric changes, such as reduc
`ing clock frequency, may also reduce the operating speed of
`the processor or portions thereof. Therefore, to reduce power
`consumption while minimizing the effect on performance, it
`is useful to only affect the operating parameters of portions of
`the processor that are not in use or that are minimally used.
`The power management controller 80 may therefore be
`adapted to use the application profile data 84, where the
`usage, in the running of application 25, of various portions of
`the processor is provided along with the application code 25,
`to selectively adjust the parametric settings of identified por
`tions of the processor 15. For example, if a particular portion
`of the processor, such as the 2D engine 52, is not active or not
`used in the execution of application 25, as indicated by the
`application profile data 84, then the power management con
`troller 80 may simply turn OFF the 2D engine 52 during
`runtime of the application code 25, prior to the runtime of
`application code 25 or during the initialization of application
`25. Alternatively, the power management controller 80 may
`reduce the clocking frequency of SCLK 98 to reduce the
`power consumption of the 2D engine 52. Alternatively, the
`power management controller 80 may reduce the value of the
`power supply voltage 72 for the 2D engine 52 to reduce the
`power consumption of the 2D engine 52. Of course, reducing
`the clock frequency of SCLK98 to Zero or reducing the power
`supply voltage 72 to Zero may effectively reduce power con
`sumption to near Zero. If the 2D engine 52 is not used in the
`application code 25, then this approach may be optimal for
`reducing power consumption. Alternatively, if a portion, Such
`as the memory controller 56 is used in the application, but
`only sporadically, then the power management controller 80
`may be adapted to only reduce the clock frequency of MCLK
`94 or the power supply voltage 72, or both, to the memory
`controller 56. The power consumption of the memory con
`troller 56 is thereby reduced. The speed of operation of the
`memory controller 56 that Supplies memory control signals
`110 for accessing the additional memory 40 may be reduced
`while maintaining Sufficient functionality to Support the
`operation of the processor 15. Similarly, the transistor back
`bias may be varied under the control of the power manage
`ment controller 80 to increase or to reduce the power con
`sumption of a portion of the processor 15.
`The application profile data 84 may be supplied to the
`memory 20 in various ways. For example, the application
`code 25 and application profile data 84 may be written into
`memory 20 during the manufacture of the battery-powered
`device 10. Alternatively, the application code 25 and applica
`tion profile data 84 may be written into memory 20 at a later
`time. For example, the application code 25 and application
`profile data 84 may be supplied through a wireless data link
`using the transceiver 30 and the controller35. The application
`and application profile data 112 may be downloaded from a
`wireless network through the transceiver 30. In this example,
`the application and application profile data 114 is then trans
`mitted through the controller 35, and the application and
`application profile data 114 is stored in memory 20. Alterna
`tively, the application profile data 84 may be supplied inde
`pendent of the application code 25.
`The idle register 70 may generate idle bits 118 that may be
`read from the processor 15 to monitor the activity of the
`various portions of the processor 15. For example, the idle
`register 70 may generate bit patterns that indicate which
`portions of the processor 15 are active or inactive during
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`encoded streams (e.g., H.264, VC-1, MPEG or other encoded
`schemes typically include identifiers in the encoded data
`identifying the codec employed to encode the data stream) is
`used to determine how to control the video encoder to save
`power. Additional control data may be included in the stream
`if desired, but this can add additional data that may be unde
`sirable in Some instances.
`Referring again to FIG.1. The power management control
`ler 80 is operative to control power consumption of processor
`portions based on the application profile data 84 and may be
`in any Suitable form including but limited to executing soft
`ware, dedicated circuitry or any suitable structure. The power
`management controller 80 may be operatively coupled to the
`system clock register 64, the main clock register 66 and the
`general purpose I/O 68. The crystal oscillator 45 generates an
`oscillator signal 90 that oscillates at a specific frequency
`based on the crystal 45. The oscillator signal 90 may be used
`by the PLL block 58 to generate a plurality of clock signals
`each of a specified frequency. For example, the system PLL
`60 may generate a system clock (SCLK) 84 that may be used
`to synchronize operations in the 2D engine 52 and the 3D
`engine 54. Meanwhile, the memory PLL 62 may generate a
`memory clock (MCLK) 94 that is used to synchronize opera
`tions of the memory controller 56. The system PLL 60 may be
`adapted to generate the SCLK92 with various frequencies. To
`select a specific frequency to change power consumption of
`the device based on the profile information 84, the power
`management controller 80 writes a system clock program
`value (SCLKPROG)96 into the system clock register 64. The
`system clock register 64 generates a system clock frequency
`(SCLKFREQ)98 that is used as the frequency selection input
`to the system PLL 60. Similarly, the memory PLL 62 may be
`adapted to generate the MCLK 94 with various frequencies.
`To select a specific frequency, the power management con
`troller 80 may write a memory clock program value (MCLK
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`PROG) 102 into the memory clock register 66. The memory
`clock register 66 generates a memory clock frequency
`(MCLK FREQ) 104 that is used as the frequency selection
`input to the memory PLL 62. As a result, the power manage
`ment controller 80 is operative to vary the clocking frequen
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`cies of several portions of the processor 15, such as the 2D
`engine 52, the 3D engine 54, and the memory controller 56 or
`any other desired portions of the processor.
`The power supply voltage input 72 may be operatively
`coupled to the processor 15 to provide a voltage supply for
`operating the processor 15. A plurality of such power Supply
`Voltage inputs 72 may be used to provide a plurality of sepa
`rate adjustable voltage supplies for different portions of the
`processor 15. The power supply voltage input 72 may be
`operatively coupled to the output 73 of the voltage generator
`50. The voltage generator 50, in turn may be coupled to and
`controlled by a power supply set signal 106 from processor
`15. For example