Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 1 of 20
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`PARKERVISION, INC.,
`
`
`
`
`
`v.
`
`Plaintiff,
`
`LG ELECTRONICS, INC.,
`
`Defendant.
`
`
`
`
`
`
`
`
`
`
`Case No. 6:21-cv-00520-ADA
`
`JURY TRIAL DEMANDED
`
`JOINT CLAIM CONSTRUCTION STATEMENT
`
`

`

`1
`
`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 2 of 20
`
`modulations” is limiting.
`electromagnetic signal having complex
`Only the portion of the preamble reciting “an
`
`modem”) is limiting.
`The entire preamble (including “cable
`
`(EM) signal”
`of energy from an input electromagnetic
`“a module that stores a non-negligible amount
`
`electromagnetic signal”
`negligible amounts of energy from an input
`energy transfer system that stores non-
`Energy storage device: “a device of an
`
`
`
`from an input electromagnetic signal”
`stores non-negligible amounts of energy
`“a module of an energy transfer system that
`Energy storage module / storage module:
`
`
`
`signal”
`of energy from an input electromagnetic
`system that stores non-negligible amounts
`element: “an element of an energy transfer
`Energy storage element / storage
`
`(’835 patent, cl. 1)
`modulations, comprising”
`having complex
`electromagnetic signal
`converting an
`“A cable modem for down-
`(’673 patent, cls. 13, 17, 18)
`“energy storage device”
`26, 27)
`’736 patent, cls. 1, 11, 21,
`’528 patent, cls. 1, 9;
`(’513 patent, cl. 19;
`“energy storage element”
`(’835 patent, cl. 20)
`“storage device”
`(’444 patent, cls. 3, 4)
`“storage element”
`(’902 patent, cl. 1)
`“energy storage module”
`’725 patent, cls. 1, 6, 17-19)
`’835 patent, cls. 1, 18;
`179, 186, 190;
`115, 164, 166, 168, 175,
`(’706 patent, cls. 105, 114,
`“storage module”
`
`LGE’s Proposed Construction
`
`ParkerVision’s Proposed Construction
`
`Term
`
`2
`
`1
`No.
`Term
`
`TERMS THAT THE PARTIES NEWLY BRIEFED IN THIS LITIGATION
`
`I.
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 3 of 20
`
`2
`
`frequency of the periodic wave”
`integer multiple of the fundamental
`periodic wave that has a frequency that is an
`Harmonic: “A sinusoidal component of a
`§ I.I
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 15,
`§ II.N;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 31,
`II; 6-9, § III.B;
`Dkt. No. 32-97: Intel 108 Rep. Br. at 1-3, §
`II; 18-22, § III.B;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 2-5, §
`IV.B;
`Dkt. No. 33: Intel 108 Op. Br. at 19-24, §
`Citation(s):
`
`frequency of the input signal”
`“sampling at less than or equal to twice the
`II.B
`Dkt. No. 32-55: Intel 562 Rep. Br. at 7-8, §
`II.B;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 7, §
`Citation(s):
`
`down-converted”
`“the sample of the image that has been
`
`
`
`fundamental frequency as the first harmonic”
`of the periodic waveform and including the
`integer multiple of the fundamental frequency
`periodic wave that has afrequency that is an
`Harmonic: “A sinusoidal component of a
`
`34, § IV.N
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 33-
`16-17, § V.G;
`Dkt. No. 36-6: PV 108 Rep. Br. at 3, § III;
`20-23, § III.G;
`Dkt. No. 36-5: PV 108 Resp. Br. at 2-4, § II;
`IV.G;
`Dkt. No. 36-1: PV 108 Op. Br. at 27-28, §
`Citation(s):
`
`
`
`the input signal”
`less than or equal to twice the frequency of
`“sampling at an aliasing rate” or “sampling at
`
`IV.C
`Dkt. No. 36-13: PV 562 Rep. Br. at 12-13, §
`V.B;
`Dkt. No. 36-8: PV 562 Op. Br. at 9-10, §
`Citation(s):
`
`Plain and ordinary meaning
`
`
`
`Arguments from Prior Litigations
`
`Arguments from Prior Litigations
`
`Citation(s) to Incorporated By Reference
`
`LGE’s Proposed Construction and
`
`Citation(s) to Incorporated By Reference
`ParkerVision’s Proposed Construction and
`
`Term
`
`TERMS WITH BRIEFING IN PRIOR LITIGATIONS INCORPORATED BY REFERENCE
`
`II.
`
`28, 34; ’518 patent, cl. 1)
`(’706 patent, cls. 1, 6, 7,
`“harmonic” / “harmonics“
`
`5
`
`28, 34; ’444 patent, cl. 2)
`(’706 patent, cls. 1, 6, 7,
`sampling”
`samples” / “under-
`“under-sample” / “under-
`
`4
`
`(’706 patent, cl. 34)
`“said sample”
`(’706 patent, cls. 1, 6, 7)
`“said input sample”
`
`3
`
`No.
`Term
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 4 of 20
`
`Citation(s):
`
`Plain and ordinary meaning
`
`§ I.H
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`§ II.P;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 32,
`Citation(s):
`
`Plain and ordinary meaning
`
`
`
`
`
`§ I.J
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 15,
`32, § II.O;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 31-
`II.D;
`Dkt. No. 32-55: Intel 562 Rep. Br. at 9-12, §
`§ II.D;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 10-12,
`Citation(s):
`
`
`
`fundamental frequency of the periodic wave”
`frequency that is an integer multiple of the
`periodic wave each of which have a
`Harmonics: “Sinusoidal components of a
`
`3
`
`signal”
`that has been modulated by a baseband
`frequency having at least one characteristic
`“anelectromagnetic signal at a transmission
`14, § VII
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`37, §IV.P;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 36-
`II.B; 25-26, § IV.J
`Dkt. No. 36-13: PV 562 Rep. Br. at 4-6, §
`V.I;
`Dkt. No. 36-8: PV 562 Op. Br. at 30-33, §
`Citation(s):
`
`
`
`translator.”
`having a unified input filter and frequency
`plain-and-ordinary meaning is “a circuit
`Plain and ordinary meaning wherein the
`14, § VIII
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`36, § IV.O;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 34-
`15-17, § IV.E
`Dkt. No. 36-13: PV 562 Rep. Br. at 7-8, § III;
`V.D;
`Dkt. No. 36-8: PV 562 Op. Br. at 12-17, §
`Citation(s):
`
`
`
`the first harmonic”
`and including the fundamental frequency as
`frequency or tone, is an integer multiple of it
`compared to its fundamental or reference
`Harmonics: “A frequency or tone that, when
`
`(’513 patent, cl. 19;
`“modulated carrier signal”
`(’706 patent, cl. 127)
`“modulated signal”
`
`(’706 patent, cl. 28)
`signal”
`down-convert an input
`translator to filter and
`“integral filter/frequency
`
`7
`
`6
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 5 of 20
`
`§ I.H
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`§ II.V;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 36,
`III.I;
`Dkt. No. 32-97: Intel 108 Rep. Br. at 15, §
`§ III.I;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 40-42,
`IV.I;
`Dkt. No. 33: Intel 108 Op. Br. at 41-43, §
`Citation(s):
`
`Plain and ordinary meaning
`
`
`
`§ I.H
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`33, § II.Q;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 32-
`
`4
`
`14, § VII
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`44, § IV.V;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 43-
`8-9, § V.C;
`Dkt. No. 36-6: PV 108 Rep. Br. at 4-5, § IV;
`III.C;
`Dkt. No. 36-5: PV 108 Resp. Br. at 12-15, §
`IV.C;
`Dkt. No. 36-1: PV 108 Op. Br. at 19-21, §
`Citation(s):
`
`
`
`dictated by an independent control input”
`device for opening and closing a circuit as
`plain-and-ordinary meaning is “an electronic
`Plain and ordinary meaning wherein the
`14, § VII
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`38, § IV.Q;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 37-
`IV.K;
`Dkt. No. 36-13: PV 562 Rep. Br. at 26-27, §
`V.L;
`Dkt. No. 36-8: PV 562 Op. Br. at 35-36, §
`7-8, § V.B
`Dkt. No. 36-6: PV 108 Rep. Br. at 4-5, § IV;
`III.B;
`Dkt. No. 36-5: PV 108 Resp. Br. at 10-11, §
`IV.B;
`Dkt. No. 36-1: PV 108 Op. Br. at 17-19, §
`Citation(s):
`
`
`
`“switching device”
`(’902 patent, cl. 1)
`“switch module”
`17, 18)
`’673 patent, cls. 1, 6, 7, 13,
`21, 26, 27;
`’736 patent, cls. 1, 11, 15,
`’528 patent, cls. 1, 5, 8, 17;
`’513 patent, cl. 19;
`’835 patent, cls. 18, 19, 20;
`’444 patent, cl. 3;
`’518 patent, cl. 50;
`179, 186, 187, 190;
`165, 166, 168, 175, 176,
`109, 111, 114, 115, 164,
`(’706 patent, cls. 105, 107,
`“switch”
`
`8
`
`19)
`’673 patent, cls. 1, 2, 7, 13,
`’736 patent, cls. 1, 11, 15;
`’528 patent, cls. 1, 5, 14;
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 6 of 20
`
`17, § I.M
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 15-
`39, § II.W;
`Dkt. No. 32-18: TCL/Hisense Op. Br.at 37-
`§ III.J;
`Dkt. No. 32-97: Intel 108 Rep. Br. at 16-17,
`§ III.J;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 42-44,
`IV.J;
`Dkt. No. 33: Intel 108 Op. Br. at 43-45 , §
`Citation(s):
`
`module”
`sampled energy stored in the energy storage
`“a down-converted signal being created from
`
`§ I.H
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`34, § II.R;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 33-
`Citation(s):
`
`Plain and ordinary meaning
`
`
`
`5
`
`15-17, § XI
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`45, § IV.W;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 44-
`V.E;
`Dkt. No. 36-6: PV 108 Rep. Br. at 10-13, §
`III.E;
`Dkt. No. 36-5: PV 108 Resp. Br. at 15-19, §
`IV.E;
`Dkt. No. 36-1: PV 108 Op. Br. at 23-26, §
`Citation(s):
`
`switch module is open”
`discharged from the storage module when the
`module is closed and from sampled energy
`electromagnetic signal when the switch
`sampled energy transferred fromthe
`“a lower frequency signal formed from
`14, § VII
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`40, § IV.R;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 38-
`Dkt. No. 36-6: PV 108 Rep. Br. at 4-5, § IV;
`III.H.4;
`Dkt. No. 36-5: PV 108 Resp. Br. at 28-29, §
`IV.J;
`Dkt. No. 36-1: PV 108 Op. Br. at 31-32, §
`Citation(s):
`
`wide range of electromagnetic frequencies”
`output signal from an input signal from a
`“circuitry that generates a down converted
`
`
`
`(’902 patent, cl. 1)
`sampled energy”
`being generated from said
`“a down-converted signal
`
`10
`
`(’518 patent, cl. 50)
`down-converter (UFD)”
`“universal frequency
`(’725 patent, cl. 1)
`
`9
`
`

`

`6
`
`Citation(s):
`
`Citation(s):
`
`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 7 of 20
`
`said second down-converted signal”
`both said first down-converted signal and
`capacitor that reduces a DC offset voltage in
`[wherein said storage elements comprises] “a
`III.A
`Dkt. No. 32-97: Intel 108 Rep. Br. at 3-6, §
`II; 5-18, § III.A;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 2-5, §
`IV.A;
`Dkt. No. 33: Intel 108 Op. Br. at 9-18, §
`Citation(s):
`
`
`
`frequency of the modulated carrier signal)”
`sampling at less than or equal to twice the
`carrier signal at an aliasing rate (i.e., by
`“A system that down-converts a modulated
`§ I.F, G
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`§ II.M;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 30,
`Citation(s):
`
`capacitor (Figures 20A and 20A-1).
`comprising at least one switch and one
`Structure: an “aliasing module 2000”
`
`
`
`output[] a [] down-converted signal.”
`... according to a [] control signal and
`Function: “to down-convert the input signal
`
`Subject to § 112, ¶ 6
`
`
`
`corresponding down-converted signal
`reduces a DC offset voltage in the
`capacitor” in each of the storage elements
`Plain and ordinary meaning wherein the “a
`
`first down-converted signal
`DC offset voltage in said
`capacitor that reduces a
`elements comprises] “a
`[wherein said storage
`
`V.H
`Dkt. No. 36-6: PV 108 Rep. Br. at 17-20, §
`II.C; 23, 25-27, § III.H, H.2;
`Dkt. No. 36-5: PV 108 Resp. Br. at 4-5, §
`IV.H;
`Dkt. No. 36-1: PV 108 Op. Br. at 28-29, §
`Citation(s):
`
`
`
`Plain and ordinary meaning
`13, § VI
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`33, § IV.M;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 32-
`V.H;
`Dkt. No. 36-6: PV 108 Rep. Br. at 17-20, §
`III.H.3;
`Dkt. No. 36-5: PV 108 Resp. Br. at 27-28, §
`IV.I;
`Dkt. No. 36-1: PV 108 Op. Br. at 29-31, §
`Citation(s):
`
`(’673 patent, cl. 13)
`converting”
`“apparatus for down-
`
`
`
`’736 patent, cl. 1)
`’528 patent, cl. 1;
`(’513 patent, cl. 19;
`down-converting”
`“system for frequency
`
`13
`
`12
`
`
`
`Plain and ordinary meaning
`
`Not subject to § 112, ¶ 6
`
`
`
`’673 patent, cl. 1)
`(’444 patent, cls. 2, 3;
`conversion module”
`“frequency down-
`
`11
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 8 of 20
`
`IV.H;
`Dkt. No. 33: Intel 108 Op. Br. at 39-41 , §
`Citation(s):
`
`to a discrete-time signal”
`process of reducing a continuous-time signal
`in its closed (i.e., on) state as part of the
`“a period of time during which the switch is
`
`§ I.H
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`35, § II.T;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 34-
`Citation(s):
`
`
`
`Plain and ordinary meaning
`§ I.K
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 15,
`§ II.S;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 34,
`§ III.D;
`Dkt. No. 32-97: Intel 108 Rep. Br. at 10-11,
`§ III.D;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 27-30,
`IV.D;
`Dkt. No. 33: Intel 108 Op. Br. at 29-32, §
`
`7
`
`III.D;
`Dkt. No. 36-5: PV 108 Resp. Br. at 15, §
`IV.D;
`Dkt. No. 36-1: PV 108 Op. Br. at 21-23, §
`Citation(s):
`
`in its closed (i.e., on) state”
`“a period of time during which the switch is
`14, § VII
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`42, § IV.T;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 41-
`Dkt. No. 36-6: PV 108 Rep. Br. at 21, § V.J
`III.J;
`Dkt. No. 36-5: PV 108 Resp. Br. at 31-32, §
`IV.N;
`Dkt. No. 36-1: PV 108 Op. Br. at 37-38, §
`Citation(s):
`
`
`
`reference voltage, e.g., ground”
`between the DC voltage of a signal and a
`plain-and-ordinary meaning is “the difference
`Plain and ordinary meaning wherein the
`14-15, § IX
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`41, § IV.S;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 40-
`V.I;
`Dkt. No. 36-6: PV 108 Rep. Br. at 20-21, §
`III.I;
`Dkt. No. 36-5: PV 108 Resp. Br. at 30-31, §
`IV.M;
`Dkt. No. 36-1: PV 108 Op. Br. at 34-37, §
`
`’673 patent, cls. 13, 17, 19)
`’736 patent, cls. 1, 11;
`’528 patent, cl. 1;
`(’513 patent, cl. 19;
`“sampling aperture”
`
`15
`
`(’444 patent, cl. 4)
`“DC offset voltage”
`
`14
`
`(’444 patent, cl. 4)
`converted signal”
`and said second down-
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 9 of 20
`
`Function: “delaying said input sample”
`
`Subject to § 112, ¶ 6
`§ I.G
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`24, § II.H;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 22-
`§ II.F;
`Dkt. No. 32-55: Intel 562 Rep. Br. at 14-17,
`§ II.F;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 13-17,
`Citation(s):
`
`
`
`equivalents thereof”
`and capacitor 5310 in Figs. 53A/53A-1, and
`capacitor 2652 in Fig. 26; the switch 5308
`Structure: “the switch 2650 and the
`
`
`
`a control signal”
`under-sampling the input signal according to
`converted image of said input signal and
`to produce an input sample of a down-
`Function: “under-sampling an input signal
`
`
`
`Subject to § 112, ¶ 6
`§ I.L
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 15,
`36, § II.U;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 35-
`III.H;
`Dkt. No. 32-97: Intel 108 Rep. Br. at 14, §
`§ III.H;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 38-40,
`
`8
`
`down-converted image of said input signal”
`Function: “delaying the input sample of a
`
`sample”
`delaying said input
`“first delaying means for
`
`17
`
`13, § VI
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`26, § IV.H;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 24-
`II.C; 19-21, § IV.G;
`Dkt. No. 36-13: PV 562 Rep. Br. at 6-7, §
`V.F;
`Dkt. No. 36-8: PV 562 Op. Br. at 20-23, §
`Citation(s):
`
`thereof”
`5308 in Figs. 53A/53A-1; and equivalents
`Structure: “switch 2650 in Fig. 26; switch
`
`
`
`
`
`the input signal according to a control signal”
`image of the input signal and under-sampling
`produce an input sample of a down-converted
`Function: “under-sampling an input signal to
`
`15, § X
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`43, § IV.U;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 42-
`Dkt. No. 36-6: PV 108 Rep. Br. at 9, § V.D;
`
`(’706 patent, cl. 6)
`input signal”
`converted image of said
`an input sample of a down-
`an input signal to produce
`“means for under-sampling
`
`16
`
`

`

`9
`
`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 10 of 20
`
`§ II.H;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 19-22,
`Citation(s):
`
`
`
`27; and equivalents thereof.
`inductors and/or resistors described at 35:19-
`line having a combination of capacitors,
`described at 32:44-64; or an analog delay
`circuits 4501 and 4503 in Fig. 45 and
`described at 35:1-18; the sample and hold
`“delay module 3204” shown in Fig. 32 and
`shown in Fig 26 and described at 32:27-55,
`module 2628,” “second delay module 2630”
`Structure: structure including “first delay
`
`
`
`signal
`Function: delaying instances of an output
`
`
`
`Subject to § 112, ¶ 6
`§ I.G
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`26, § II.I;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 24-
`§ II.G;
`Dkt. No. 32-55: Intel 562 Rep. Br. at 17-20,
`§ II.G;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 17-19,
`Citation(s):
`
`shown in Fig. 26”
`Structure: “switch 2654 and capacitor 2656
`
`
`
`II.C; 24-25, § IV.I
`Dkt. No. 36-13: PV 562 Rep. Br. at 6-7, §
`V.H;
`Dkt. No. 36-8: PV 562 Op. Br. at 25-30, §
`Citation(s):
`
`
`
`resistors; and equivalents thereof
`combination of capacitors, inductors, and/or
`delay line 3404 shown in Fig. 34 having a
`circuits 4501, 4503 shown in Fig. 45; analog
`3204 shown in Fig. 32; sample and hold
`delay module 2630 in Fig. 26; delay module
`Fig. 23; first delay module 2628, second
`1914 in Fig. 19; delay modules 2316, 2318 in
`1722C, etc. in FIG. 17; delay modules 1912,
`Structure: delay modules 1722A, 1722B,
`
`
`
`signal
`Function: delaying instances of an output
`13, § VI
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`29, § IV.I;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 26-
`II.B; 21-24, § IV.H;
`Dkt. No. 36-13: PV 562 Rep. Br. at 4-6, §
`V.G;
`Dkt. No. 36-8: PV 562 Op. Br. at 23-25, §
`Citation(s):
`
`equivalents thereof”
`capacitor 5310 in Figs. 53A/53A1; and
`Structure: “capacitor 2656 in Fig. 26 or
`
`
`
`(’706 patent, cl. 6)
`an output signal”
`for delaying instances of
`“second delaying means
`
`18
`
`(’706 patent, cl. 6)
`
`

`

`10
`
`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 11 of 20
`
`§ II.K
`Dkt. No. 32-55: Intel 562 Rep. Br. at 24-26,
`§ II.K;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 25-28,
`Citation(s):
`
`
`
`thereof.
`36:63-37:5 and 42:27-32) and equivalents
`capacitors, inductors, etc.) (described at
`components(such as tunable resistors,
`optimizing module 4210 using tunable
`tunable oscillator 4204 and an aperture
`36:44-62 and 42:27-32) implemented with a
`4202 (shown in Fig. 42 and described at
`thereof; OR the control signal generator
`described at 42:33-36); and equivalents
`resistors, capacitors, or inductors (as
`the amplifier/attenuator 3704 having tunable
`67), each of the resistor attenuator 3602 and
`(shown in Fig. 37 and described at 35:60-
`operational amplifiers, transistors, or FETS
`amplifier/attenuator 3704 implemented using
`and described at 35:44-55) or the
`resistor attenuator 3602 (shown in Fig. 36
`Structure: scaling modules including the
`
`parameters
`Function: tuning one or more filter
`
`
`
`Subject to § 112, ¶ 6
`§ II.H
`Dkt. No. 32-55: Intel 562 Rep. Br. at 20-22,
`
`IV.L
`Dkt. No. 36-13: PV 562 Rep. Br. at 27-29, §
`V.M;
`Dkt. No. 36-8: PV 562 Op. Br. at 36-43, §
`Citation(s):
`
`
`
`and equivalents thereof
`37; control signal generator 4202 in Fig. 42;
`including amplifier/attenuator 3704 in Fig.
`in Figs. 35, 36; scaling module 3702
`3502 including resistor attenuator 3504, 3602
`module 2632, 2634 in Fig. 26; scaling module
`modules 2312, 2320, 2322 in Fig. 23; scaling
`modules 1916, 1918 in Fig. 19; scaling
`scaling module 1909 in Fig. 19; scaling
`control signal generator 1790 in Fig. 17; input
`1716C, 1724A, 1724B, 1724C in Fig. 17;
`Structure: scaling modules 1716A, 1716B,
`
`parameters
`Function: tuning one or more filter
`
`
`
`(’706 patent, cl. 134)
`parameters”
`tuning one or more filter
`“filter tuning means for
`
`19
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 12 of 20
`
`26:1-27:21 and 28:20-41, that includes the
`module 2624 in Fig. 26 and described at
`Structure: “the down convert and delay
`
`
`
`sample”
`said input signal, and to delay said input
`input sample of a down-converted image of
`according to a control signal to produce an
`Function: “under-sample an input signal
`
`
`
`Subject to § 112, ¶ 6.
`§ I.F, G
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`27, § II.J;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 26-
`II.A;
`Dkt. No. 32-55: Intel 562 Rep. Br. at 2-7 , §
`II.A;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 3-7, §
`Citation(s):
`
`
`
`2652 and 2656; and equivalents thereof”
`switches 2650 and 2654, and the capacitors
`26:1-27:21 and 28:20-41, that includes the
`module 2624 in Fig. 26 and described at
`Structure: “the down-convert and delay
`
`to a control signal, and delay said sample”
`converted image of an input signal according
`Function: “produce a sample of a down-
`
`Subject to § 112, ¶ 6
`
`
`
`11
`
`13, § VI
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`20, § IV.E;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 19-
`II.A-C; 8-10, § IV.A;
`Dkt. No. 36-13: PV 562 Rep. Br. at 1-7, §
`Dkt. No. 36-8: PV 562 Op. Br. at 7-9, § V.A;
`Citation(s):
`
`
`
`Plain and ordinary meaning
`
`
`
`Not subject to § 112, ¶ 6
`
`(’706 patent, cls. 1, 7)
`said input sample”
`input signal, and to delay
`converted image of said
`input sample of a down-
`input signal to produce an
`module to under-sample an
`“a down-convert and delay
`
`21
`
`13, § VI
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`§ IV.J;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 29,
`§II.B-C; 12, § IV.B;
`Dkt. No. 36-13: PV 562 Rep. Br. at 4-7,
`V.J;
`Dkt. No. 36-8: PV 562 Op. Br. at 33-34, §
`Citation(s):
`
`
`
`Plain and ordinary meaning
`
`
`
`Not subject to § 112, ¶ 6
`
`(’706 patent, cl. 34)
`delay said sample”
`an input signal, and to
`down-converted image of
`produce a sample of a
`“a frequency translator to
`
`20
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 13 of 20
`
`Fig. 45 and described at 32:44-33:19; or an
`the sample and hold circuit 4501 and 4503 in
`shown in Fig. 32 and described at 35:1-18;
`shown in Fig 26, “delay module 3204”
`module 2628,” “second delay module 2630”
`Structure: “structure including “first delay
`
`delayed and down-converted input samples”
`signal / further delay one or more of said
`Function: “delay instances of an output
`
`
`
`Subject to § 112, ¶ 6
`§ I.F
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`20, § II.E;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 18-
`II.A;
`Dkt. No. 32-55: Intel 562 Rep. Br. at 2-7 , §
`II.A;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 3-7, §
`Citation(s):
`
`2652 and 2656; and equivalents thereof”
`switches 2650 and 2654, and the capacitors
`
`
`
`12
`
`21, § IV.F;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 20-
`§II.A; 6-7, §II.C; 13-15, § IV.D;
`Dkt. No. 36-13: PV 562 Rep. Br. at 1-3,
`V.C;
`Dkt. No. 36-8: PV 562 Op. Br. at 10-11, §
`Citation(s):
`
`
`
`Plain and ordinary meaning
`
`
`
`Not subject to § 112, ¶ 6
`
`(’706 patent, cls. 1, 7)
`output signal”
`to delay instances of an
`“at least one delay module
`
`22
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 14 of 20
`
`Indefinite
`
`14, § I.E
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 13-
`22, § II.G;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 21-
`Citation(s):
`
`
`
`Indefinite
`§ I.F, G
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 14,
`21, § II.F;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 20-
`II.C;
`Dkt. No. 32-55: Intel 562 Rep. Br. at 8-9 , §
`II.C;
`Dkt. No. 32-45: Intel 562 Resp. Br. at 7-9, §
`Citation(s):
`
`
`
`thereof”
`described at 35:19-27; or equivalents
`capacitors, inductors and/or resistors
`analog delay line having a combination of
`
`13, § VI
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`
`(’706 patent, cl. 34)
`to delay an output signal”
`“at least one delay module
`
`13
`
`14, § I.E
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 13-
`30, § II.L;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 29-
`Citation(s):
`
`13, § V
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`32, § IV.L;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 31-
`Citation(s):
`
`Plain and ordinary meaning
`13, § V
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`23, § IV.G;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 21-
`IV.F;
`Dkt. No. 36-13: PV 562 Rep. Br. at 18-19, §
`V.E;
`Dkt. No. 36-8: PV 562 Op. Br. at 17-20, §
`Citation(s):
`
`Plain and ordinary meaning
`
`
`
`(’706 patent, cl. 107)
`impedance of said switch”
`purpose of reducing an
`switch is closed for a
`increase the time that said
`apertures of said pulses to
`generator establishes
`“said energy transfer signal
`
`(’706 patent, cl. 2)
`converted image”
`input signal to said down-
`energy transfer from said
`are established to improve
`having pulse widths that
`comprises a train of pulses
`“said control signal
`
`24
`
`23
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 15 of 20
`
`14
`
`§ III.K
`Dkt. No. 32-97: Intel 108 Rep. Br. at 17-20,
`§ III.K;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 44-45,
`IV.K;
`Dkt. No. 33: Intel 108 Op. Br. at 45-48, §
`Citation(s):
`
`
`
`Indefinite
`
`Dkt. No. 36-6: PV 108 Rep. Br. at 21, § V.K
`39, § III.K, K.1, K.4;
`Dkt. No. 36-5: PV 108 Resp. Br. at 32-35, 37-
`IV.O;
`Dkt. No. 36-1: PV 108 Op. Br. at 38-39, §
`Citation(s):
`
`Plain and ordinary meaning
`
`
`
`from the storage module”
`storage module discharged
`information signal to the
`transferred from the RF
`percent of the energy
`“betweenten and twenty
`(’725 patent, cl. 18)
`storage module.”
`discharged from the
`storage module when is
`information signal to the
`transferred from the RF
`five percent of the energy
`“between six and twenty-
`(’725 patent, cl. 17)
`storage module”
`discharged from the
`storage module is
`information signal to the
`transferred from the RF
`percent of the energy
`“between six and fifty
`187)
`(’706 patent, cls. 165, 176,
`said input signal”
`energy transferred from
`switch, and to increase
`an impedance of said
`switch is closed to reduce
`increase the time that said
`apertures of said pulses to
`generator establishing
`“said energy transfer signal
`
`25
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 16 of 20
`
`15
`
`14, § I.E
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 13-
`28, § II.K;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 27-
`Citation(s):
`
`13, § V
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`§ IV.K
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 30,
`Citation(s):
`
`
`
`Indefinite
`
`Plain and ordinary meaning
`
`
`
`5, § I.A, B
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 1-
`§ II.A, B;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 2-9,
`Citation(s):
`
`1-6, § I-II
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`§ IV.A-B;
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 2-8,
`Citation(s):
`
`
`
`Indefinite
`
`Plain and ordinary meaning
`
`
`
`signal when said switch is
`transferred from said input
`said increased energy
`said input signal, such that
`expense of reproducing
`signal does so at the
`transferred from said input
`increasing energy
`closed for the purpose of
`time that said switch is
`in duration to extend the
`tends away from zero time
`negligible amount that
`said pulses by a non-
`widening said apertures of
`transfer signal generator in
`“wherein said energy
`(’673 patent, cl. 5)
`the low impedance load.”
`sufficient power to drive
`capacitor provides
`discharged from said
`“said enemy[sic]
`’673 patent, cls. 5, 17)
`(’736 patent, cls. 26, 27;
`“low impedance load”
`’736 patent, cls. 1, 11)
`(’528 patent, cl. 9;
`discharged”
`cycle is not completely
`during any given discharge
`“the energy discharged
`(’725 patent, cl. 19)
`
`27
`
`26
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 17 of 20
`
`16
`
`13, § I.D
`Dkt. No. 32-42: TCL/Hisense Rep. Br. at 12-
`18, § II.D;
`Dkt. No. 32-18: TCL/Hisense Op. Br. at 16-
`Citation(s):
`
`10-13, § IV
`Dkt. No. 36-22: PV 870/945 Sur-Rep. Br. at
`19, § IV.D
`Dkt. No. 36-16: PV 870/945 Resp. Br. at 16-
`Citation(s):
`
`Indefinite
`§ III.K
`Dkt. No. 32-97: Intel 108 Rep. Br. at 20-21,
`§ III.K;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 44-45,
`IV.K;
`Dkt. No. 33: Intel 108 Op. Br. at 45, 48-49, §
`Citation(s):
`
`Indefinite
`III.K
`Dkt. No. 32-97: Intel 108 Rep. Br. at 21, §
`§ III.K;
`Dkt. No. 32-90: Intel 108 Resp. Br. at 44-45,
`IV.K;
`Dkt. No. 33: Intel 108 Op. Br. at 45, 49-50, §
`Citation(s):
`
`
`
`Indefinite
`
`Plain and ordinary meaning
`
`Dkt. No. 36-6: PV 108 Rep. Br. at 21, § V.K
`III.K.2
`Dkt. No. 36-5: PV 108 Resp. Br. at 35, §
`IV.O;
`Dkt. No. 36-1: PV 108 Op. Br. at 38-39, §
`Citation(s):
`
`Plain and ordinary meaning
`
`Dkt. No. 36-6: PV 108 Rep. Br. at 21, § V.K
`III.K.3
`Dkt. No. 36-5: PV 108 Resp. Br. at 36-37, §
`IV.O;
`Dkt. No. 36-1: PV 108 Op. Br. at 38-39, §
`Citation(s):
`
`Plain and ordinary meaning
`
`
`
`
`
`(’673 patent, cl. 2)
`apertures”
`apertures or outside of the
`capacitor during the
`approximated at the
`not reproduced or
`modulated carrier signal is
`“voltageof the input
`
`30
`
`(’528 patent, cl. 17)
`module”
`“separate integration
`
`29
`
`(’902 patent, cl. 5)
`size”
`“substantially the same
`(’706 patent, cl. 111)
`said input signal”
`voltage reproduction of
`prevents substantial
`energy transfer signal
`closed in response to said
`
`28
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 18 of 20
`
`Dated: April 20, 2022
`
`
`
`/s/ Raymond W. Mort, III
`Raymond W. Mort, III
`Texas State Bar No. 00791308
`THE MORT LAW FIRM, PLLC
`100 Congress Avenue, Suite 2000
`Austin, Texas 78701
`Tel/Fax: 512-865-7950
`raymort@austinlaw.com
`
`Ronald M. Daignault*
`Chandran B. Iyer
`Jason S. Charkow*
`Stephanie R. Mandir
`Daignault Iyer LLP
`rdaignault@daignaultiyer.com
`cbiyer@daignaultiyer.com
`jcharkow@daignaultiyer.com
`smandir@daignaultiyer.com
`8618 Westwood Center Drive
`Suite 150
`Vienna, VA 22182
`
`*Not admitted to practice in Virginia
`
`Attorneys for Plaintiff ParkerVision, Inc.
`
`
`
`Respectfully submitted,
`
`/s/ Melissa R. Smith
`Melissa R. Smith
`GILLAM & SMITH, LLP
`TX State Bar No. 24001351
`303 S. Washington Avenue
`Marshall, Texas 75670
`Telephone: (903) 934-8450
`Facsimile: (903) 934-9257
`melissa@gillamsmithlaw.com
`
`Steven Pepe
`Matthew Shapiro
`James Stevens
`Michael Morales
`ROPES & GRAY LLP
`1211 Avenue of the Americas
`New York, NY 10036-8704
`Tel: 212.596.9000
`Fax: 212.596.9090
`Steven.Pepe@ropesgray.com
`Matthew.Shapiro@ropesgray.com
`James.Stevens@ropesgray.com
`Michael.Morales@ropesgray.com
`
`David S. Chun
`Stepan Starchenko
`ROPES & GRAY LLP
`1900 University Ave., 6th Floor
`East Palo Alto, CA 94303-2284
`Tel: 650.617.4000
`Fax: 650.617.4090
`David.Chun@ropesgray.com
`Stepan.Starchenko@ropesgray.com
`
`Scott Taylor
`(Admission application forthcoming)
`ROPES & GRAY LLP
`Prudential Tower
`800 Boylston Street
`Boston, MA 02199-3600
`Tel: 617.951.7000
`Fax: 617.951.7050
`Scott.Taylor@ropesgray.com
`
`
`17
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 19 of 20
`
`Attorneys for Defendant LG Electronics Inc.
`
`
`
`
`18
`
`

`

`Case 6:21-cv-00520-ADA Document 42 Filed 04/20/22 Page 20 of 20
`
`CERTIFICATE OF SERVICE
`
`The undersigned hereby certifies that, on April 20, 2022, all counsel of record who are deemed
`
`to have consented to electronic service are being served with a copy of this document.
`
`/s/ Stephanie R. Mandir
`Stephanie R. Mandir
`
`19
`
`