Case 6:21-cv-00520-ADA Document 36-13 Filed 03/16/22 Page 1 of 51
`Case 6:21-cv-00520-ADA Document 36-13 Filed 03/16/22 Page 1 of 51
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`EXHIBIT 5
`EXHIBIT 5
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`Case 6:20-cv-00562-ADA Document 43 Filed 04/21/21 Page 1 of 50Case 6:21-cv-00520-ADA Document 36-13 Filed 03/16/22 Page 2 of 51
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`UNITED STATES DISTRICT COURT
`WESTERN DISTRICT OF TEXAS
`WACO DIVISION
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` Plaintiff,
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`PARKERVISION, INC.,
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`
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` v.
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`INTEL CORPORATION,
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` Defendant.
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`
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`Case No. 6:20-cv-00562
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`JURY TRIAL DEMANDED
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`
`PLAINTIFF PARKERVISION’S
`REPLY CLAIM CONSTRUCTION BRIEF
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`TABLE OF CONTENTS
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`Page
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`I.
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`Intel seeks to use the complexity of the technology as cover for
`its gamesmanship. ............................................................................................................... 1
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`II.
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`Intel creates a false narrative regarding the technology of the ’706 patent. ....................... 1
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`A.
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`B.
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`C.
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`Intel attempts to use §112, ¶ 6 and an “empty black box” argument as a
`strategy to improperly narrow the claims to a specific embodiment. ..................... 1
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`Intel’s end game regarding the ’706 patent is a false narrative. ............................. 4
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`Lost in its gamesmanship, Intel takes inconsistent positions. ................................. 6
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`III.
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`IV.
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`Intel ignores previous claim construction rulings. .............................................................. 7
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`U.S. Patent No. 6,049,706 – disputed terms for construction ............................................. 8
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`A.
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`“down-convert and delay module” (claims 1, 7) .................................................... 8
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`1.
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`2.
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`§112, ¶ 6 does not apply ............................................................................. 8
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`Intel’s construction is wrong. .................................................................... 10
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`B.
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`“frequency translator” (claim 34) ......................................................................... 12
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`1.
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`2.
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`§112, ¶ 6 does not apply ........................................................................... 12
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`Intel’s construction is wrong. .................................................................... 12
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`“said input sample”, “said sample” (claims 1, 6, 7, 34) ........................................ 12
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`“delay module” (claims 1, 7, 34, 140) .................................................................. 13
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`1.
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`2.
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`§112, ¶ 6 does not apply ........................................................................... 13
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`Intel’s construction is wrong. .................................................................... 14
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`a.
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`b.
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`Intel improperly seeks to narrow equivalents. .............................. 14
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`Intel improperly seeks to exclude structures. ................................ 14
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`“harmonic” / “harmonics” (’706 patent, claims 1, 6, 7, 28, 34;
`’508 patent, claim 1) ............................................................................................. 15
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`“pulse widths that are established to improve energy transfer” (claim 2) ............ 18
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`C.
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`D.
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`E.
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`F.
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`i
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`G.
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`H.
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`I.
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`J.
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`K.
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`L.
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`“means for under-sampling” (claim 6) ................................................................. 19
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`“first delaying means” (claim 6) ........................................................................... 21
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`“second delaying means” (claim 6) ...................................................................... 24
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`“integral filter/frequency translator” (claim 28) ................................................... 25
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`“modulated signal” (claim 127) ............................................................................ 26
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`“filter tuning means” (claims 134) ........................................................................ 27
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`V.
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`U.S. Patent No. 7,050,508 – disputed terms for construction ........................................... 29
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`A.
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`B.
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`C.
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`D.
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`E.
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`F.
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`“pulse shaping means” (claim 1) .......................................................................... 29
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`“aperture generation means” (claim 1) ................................................................. 30
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`“gating means” (claim 1) ...................................................................................... 32
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`“gating” (claim 1) ................................................................................................. 33
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`“bias signal” (claim 1) .......................................................................................... 35
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`“generating a string of multiple pulses from said string
`of pulses” (claim 1) ............................................................................................... 38
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`VI.
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`U.S. Patent No. 8,190,108 – disputed claim constructions ............................................... 41
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`A.
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`B.
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`C.
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`“control signal” (claim 1)...................................................................................... 41
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`“third switch” (claim 1) ........................................................................................ 42
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`“pulse shaper” (claim 6)........................................................................................ 43
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`ii
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`TABLE OF AUTHORITIES
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`Page(s)
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`Cases
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`Asyst Techs., Inc. v. Empak, Inc.,
`268 F.3d 1364 (Fed. Cir. 2001)..........................................................................................19, 22
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`iii
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`I.
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`Intel seeks to use the complexity of the technology as cover for its gamesmanship.
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`This case involves complex wireless technology. Intel seeks to take advantage of this
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`complexity to engage in gamesmanship. Intel fills its brief with misrepresentations and half-
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`truths. In doing so, Intel creates a false narrative around the technology, seeks to use §112, ¶ 6 to
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`improperly narrow claim scope (including for terms where §112, ¶ 6 does not apply), reimagines
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`§112, ¶ 6 case law, ignores portions of the specification and patentee’s lexicography, seeks to
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`exclude disclosed embodiments, and avoids reading the claims in view of the specification. At
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`bottom, Intel simply is not concerned with the proper constructions. Instead, Intel is solely
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`focused on its non-infringement and invalidity cases.
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`Further, despite ParkerVision pointing out that the Jacksonville and Orlando district
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`courts adopted ParkerVision’s constructions in suits against Qualcomm, Intel fails to address
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`these prior court decisions. Though not binding on this Court, they are informative. Intel cannot
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`simply ignore them. For the reasons discussed in ParkerVision’s opening brief and those below,
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`ParkerVision’s constructions should be adopted.
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`II.
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`Intel creates a false narrative regarding the technology of the ’706 patent.
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`Intel creates a false narrative in this case solely to support its non-infringement defense.
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`ParkerVision breaks down Intel’s strategy and false narrative up front because exposing Intel’s
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`gamesmanship and false narrative demonstrates why Intel’s constructions are wrong.
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`A.
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`Intel attempts to use §112, ¶ 6 and an “empty black box” argument as a
`strategy to improperly narrow the claims to a specific embodiment.
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` The ’706 patent pertains to down-converting a signal using sampling. There are only two
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`systems that can be used to accomplish this: (1) energy transfer (energy sampling) systems and
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`(2) sample and hold (voltage sampling). See Case 6:20-cv-108; Dkt. 51, Sec. III; Dkt. 65, Sec. II.
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`1
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`Intel chips use energy transfer (energy sampling). As such, Intel attempts to improperly
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`exclude energy transfer (energy sampling) systems and limit all of the asserted claims to sample
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`and hold (voltage sampling) systems. In particular, Intel seeks to (1) exclude Figures 17, 19, 23,
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`which incorporate the configuration of Figure 53A/53A-1, which covers both energy transfer
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`(energy sampling) and sample/hold (voltage sampling) systems,1 and (2) limit all asserted claims
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`to Figure 26, which discloses a specific configuration of a sample and hold system.
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`The question for Intel was how could it limit all asserted claims to Figure 26. Intel knew
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`that the only path forward was to use §112, ¶ 6. But Intel ran into another problem. Only one
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`asserted independent claim (claim 6) includes means-plus-function language; the other
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`independent claims 1, 7, 28, and 34 do not. So Intel identified a term in each of claims 1, 7, 28
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`and 34 and asserted that the term is subject to §112, ¶ 6 – “down-convert and delay module,”
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`“frequency translator,” “integral filter/frequency translator” and “delay module.”2
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`In order to eliminate Figures 17, 19 and 23, Intel next alleged that (1) only Figure 26
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`discloses structure and (2) Figures 17, 19 and 23 disclose “empty black boxes” and, thus, cannot
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`be included in the structure for §112, ¶ 6. But this is false. Such a contrived argument is just a
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`means to an end for Intel to exclude energy sampling.
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`1 See ’706 patent, 32:4-12 (disclosing the use of negligible and non-negligible apertures).
`2 These terms connote structure and, thus, are not subject to §112, ¶ 6. Sections III.A, B, D, J.
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`2
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`ParkerVision will use Figure 17 (above) as an example to explain how Intel gets it wrong.
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`As shown above in Figure 17, a down-convert and delay module 1708 (blue) receives an input
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`signal 1704 (purple arrow). The module 1708 (blue) processes the input signal 1704 (purple) and
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`outputs a down-converted signal (orange arrow). As such, the module 1704 (blue) serves as the
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`frequency translator (down-converter) of the system. ’706 patent, 13:43-46. The down-convert
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`and delay modules 1908 and 2308 of Figures 19 and 23 are similar.
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`While Figures 17, 19, 23 show the down-convert and delay modules 1708, 1908, 2308 as
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`boxes, the boxes are not empty as Intel suggests. Intel ignores that modules 1708, 1908, 2308 (as
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`well as module 2624 of Figure 26) are described in the specification as being the aliasing module
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`5300 (blue) of Figures 53A or 53A-1 shown below. ’706 patent, 28:20-60.
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`The aliasing module includes one switch 5308 (yellow) and one capacitor 5310 (pink).
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`Just as with modules 1708, 1908, 2308 of Figures 17, 19, 23, the aliasing module 5300 of Figure
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`3
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`53A/53A-1 receives an input signal (purple) and outputs a down-converted signal (orange). Intel
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`improperly seeks to exclude this one switch/one capacitor configuration.
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`B.
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`Intel’s end game regarding the ’706 patent is a false narrative.
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`Intel tries to exploit the difference in the way the specification discloses the details of
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`Figure 26, on the one hand, and Figures 17, 19, 23, as a hook for its §112, ¶ 6 argument to
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`narrowly limit all asserted independent claims (1, 6, 7, 28, 34) to the embodiment of Figure 26.
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`Unlike Figures 17, 19, 23, the patentees chose to provide details directly in Figure 26
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`itself, including the components of down-convert and delay module 2624 (blue). As shown
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`below right (close-up view of Figure 26), the down-convert and delay module 2624 (blue)
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`includes two switches 2650, 2654 (yellow) and two capacitors 2652, 2656 (pink). Intel seeks to
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`limit the claims to this specific configuration.
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`
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`This limit-all-claims strategy is the same type of strategy that Intel attempted in the
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`parties’ other litigation (6:20-cv-00108), which failed. But regardless of whether the components
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`are shown in a figure (Figure 26) or shown as a box (Figures 17, 19, 23) (which the specification
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`describes as incorporating the structure of other figures), structure is still disclosed. Indeed, if the
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`images of Figure 53A or 53A-1 were included directly in the modules 1708, 1908, 2308, Figures
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`17, 19, 23 would be just like Figure 26. That the patentees chose to use words to incorporate one
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`4
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`figure into another figure, instead of showing the structure directly in the figure, should not cause
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`Figures 17, 19, 23 to be treated differently than Figure 26.
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`By excluding Figures 17, 19, 23 and their incorporated disclosure of Figures 53A and
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`53A-1, not only is Intel seeking to narrow the literal scope of the claims to Figure 26, but Intel
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`also seeks to limit the experts’ ability to argue equivalents.
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`In particular, Intel seeks to limit the claims to a two-stage configuration: (1) under-
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`sampling performed by the components in the blue shaded area (i.e., the combination of the
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`switch 2650 (yellow) and capacitor 2652 (pink)); (2) delay performed by the components in the
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`purple shared area (i.e., the combination of the switch 2654 (yellow) and capacitor 2656 (pink)).
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`Intel construes terms so that all asserted independent claims are limited to this configuration:
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`
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`Claim
`1, 7
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`Term
`“down-convert and delay module”
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`“first delaying means”
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`“integral filter/frequency translator”
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`“frequency translator”
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`6
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`28
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`34
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`
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`Intel’s Narrow Structure
`Blue and purple shaded area of Figure 26 – two switches 2650,
`2654 (yellow) and two capacitors 2652, 2656 (pink)
`Purple shaded area of Figure 26 – switch 2654 (yellow) and
`capacitor 2656 (pink)
`UDF module 2622 of Figure 26 (300-word definition) which
`includes blue and purple shaded area of Figure 26 – two switches
`2650, 2654 (yellow) and two capacitors 2652, 2656 (pink)
`Blue and purple shaded area of Figure 26 – two switches 2650,
`2654 (yellow) and two capacitors 2652, 2656 (pink) of Figure 26
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`But the claims are not so limited. Indeed, the claims recite elements (frequency translator,
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`down-convert and delay module, means for under-sampling/under-sample, means for delaying a
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`sample), which are all disclosed in Figures 53A and 53A-1 and, thus, in Figures 17, 19, 23.
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`5
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`As shown above, the aliasing module of Figures 53A and 53A-1 is a frequency translator
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`(a down-convert and delay module). The switch 5308 (yellow) under-samples the input signal
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`5304 (purple) according to a control signal 5306 (green). The under-sampling results in a down-
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`converted sample of the input signal 5304. The capacitor 5310 (pink) then delays the sample. As
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`such, claims 1, 6, 7, 28 and 34 should cover Figures 17, 19, 23, 53, 53A-1.
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`C.
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`Lost in its gamesmanship, Intel takes inconsistent positions.
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`Intel unwittingly reveals its gamesmanship by taking inconsistent positions. What
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`becomes apparent is that Intel is simply looking for any angle to improperly narrow claim scope.
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`First, the specification discloses that Figures 53A and 53A-1 are exemplary structures of the
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`down-convert and delay module 1708, 1908, 2308, 2624 of Figures 17, 19, 23, 26. See ’706
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`patent, 28:20-60. Based on this disclosure, Intel admits that module 2624 of Figure 26 can
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`include the structure of Figures 53A and 53A-1.3 Yet, at the same time, Intel denies that modules
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`1708, 1908, 2308 of Figures 17, 19, 23 can include the structure of Figures 53A and 53A-1. Intel
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`only takes this position so that Intel can maintain its argument that modules 1708, 1908, 2308 are
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`“empty black boxes” and exclude Figures 17, 19, 23 from its construction of structure.
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`3 In its responsive brief, Intel changed it construction of “means for under-sampling” in claim 6
`to include Figures 53A/53A-1. Intel only did so because it was untenable for Intel to argue that
`these figures do not perform under-sampling. But now Intel is faced with an inconsistency.
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`6
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`Second and related to the point above, Intel incorporates Figures 53A/53A-1 in its
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`construction of “means for under-sampling” but not for “down-convert and delay module,”
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`“integral filter/frequency translator,” and “frequency translator.” This is nonsensical because the
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`“means for under-sampling” is a structure that is part of a “down-convert and delay module,”
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`“integral filter/frequency translator,” and “frequency translator.”
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`Third, the specification discloses that the switched capacitor topology 3204 of Figure 32
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`is an exemplary structure of the delay module 1722 of Figure 17. See ’706 patent, 34:60-35:18.
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`When construing “delay module” and “second delaying means,” Intel identifies delay modules
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`2628, 2830 of Figure 26 and Figure 32 as §112, ¶ 6 structure.4 Intel carefully excludes any
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`mention of delay module 1722 and Figure 17 from its construction. So while Intel admits that
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`Figure 32 discloses structure, Intel’s position is that this same figure cannot provide structure for
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`delay module 1722 of Figure 17 (or delay modules of Figures 19 and 23). This is nonsense and
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`just exposes Intel’s strategy to avoid Figures 17, 19 and 23.
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`Finally, for claim 34, Intel asserts that “frequency translator” is subject to §112, ¶ 6
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`because it does not connote structure. But for claim 1, Intel does not assert that “frequency
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`translator” is subject to §112, ¶ 6. Now Intel may attempt to explain this away by asserting that
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`claim 1, unlike claim 6, recites “a frequency translator, comprising a down-convert and delay
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`module,” and, thus structure is disclosed. But the problem for Intel is that Intel has alleged that
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`the term “down-convert and delay module” also does not connote structure.
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`III.
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`Intel ignores previous claim construction rulings.
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`As set forth in the chart below, two federal Judges construed terms related to the same
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`ParkerVision technology that is in dispute here. Each Judge provided a well-reasoned opinion for
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`4 As discussed in Section IV.D below, “delay module” is not subject to §112, ¶ 6.
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`7
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`his construction. Though not binding on this Court, these constructions are informative.
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`ParkerVision’s arguments, which are consistent with the reasoning of the two Judges and the
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`intrinsic record, demonstrate that these prior constructions are correct. Intel ignores these
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`constructions because they are unhelpful to its case.
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`Term
`“harmonic”
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`“gating means”
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`“gating”
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`“bias signal”
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`Prior Court Construction
`Including the fundamental frequency in the definition of harmonic – “N is . . . an integer
`greater than or equal to 1”5 Dkt. 37-3 at 17 (Judge Dalton).
`“Structure: Figures 28A, 29A, 30A, 31A, 32A, 33A, 53A, 54A, 55, 56, 57A-C, 66-70” Dkt.
`37-2 at 39 (Judge Byron).
`“to change/changing between the open and closed states of a device that can take two states,
`open and closed, as dictated by an independent control input” Dkt. 37-2 at 38 (Judge Byron).
`“(1) a signal having a steady, predetermined level; or (2) the modulating baseband signal” Dkt.
`37-2 at 50 (Judge Byron).
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`IV. U.S. Patent No. 6,049,706 – Disputed terms for construction
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`A.
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`“down-convert and delay module” (claims 1, 7)
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`1.
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`§112, ¶ 6 does not apply
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`The term does not use “means” and, thus, there is a presumption that §112, ¶ 6 does not
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`apply. In its opening brief, ParkerVision pointed out that (1) the term is “down-convert and delay
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`module” not merely “module,” and (2) as set forth in the specification and claims, “down-
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`convert and delay module” includes a switch, storage element (e.g., capacitor) and their
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`connections and, thus, connotes structure. PV Br. at 8-9.
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` Intel ignores that the ’706 patent relates to circuits, which have physical components.
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`Unable to substantively respond to ParkerVision’s positions, Intel skirts the issue by reimagining
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`the law regarding §112, ¶ 6 and providing a questionable expert declaration. First, Intel and its
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`expert carefully assert that a component going by the name “down-convert and delay module” is
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`not a term known by a skilled person and, thus, does not have a “well understood structural
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`meaning.” Intel Br. at 4 (citing Dkt. 41-9, Decl. at 60-61). But that is beside the point. Under the
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`5 Unless otherwise indicated, all emphasis has been added.
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`8
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`law, the question is whether a “down-convert and delay module,” in view of the specification
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`and claims (which disclose physical components – switches, capacitors, and their connections),
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`would be understood by a skilled person to connote structure. It would. Ex. 1 (“Steer Decl.”) ¶
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`20.
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`Tellingly, Intel and its expert avoid this discussion and, instead, assert that the term does
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`not connote a specific or well-understood structure. In particular, Intel and its expert state that
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`multiple switches/capacitors are needed to make a “down-convert and delay module” and
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`ParkerVision’s cited structure does not disclose a “complete” structure. Intel Br. at 6 (citing Dkt.
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`41-9, Decl. ¶¶ 60-66). But whether the term connotes a specific, complete, or well-known
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`structure is irrelevant. So long as the term connotes any structure, §112, ¶ 6 does not apply.
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`Indeed, Intel’s argument is belied by its own construction which includes switches and capacitors
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`as the structure of the “down-convert and delay module.” As such, a skilled person would
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`understand that a “down-convert and delay module” connotes structure.
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`Second, while Intel’s claim construction expert (Dr. van der Weide) states that “down-
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`convert and delay module” does “not have well-understood structural meaning[] in [October]
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`1998” (Dkt. 41-9, Decl. ¶ 60), Intel’s IPR expert (Dr. Subramanian) has a different view. When
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`seeking to invalidate another ParkerVision patent, Intel relied on Dr. Subramanian who was able
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`to identify a “down-conversion module” (switch and capacitor) in a 1996 prior art reference
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`(Larson). See Ex. 2, IPR2020-01302, Dkt. Ex. 1002 at 44, 56-60. Indeed, Intel did not even
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`allege that “down-conversion module” in the claims of the IPR patent were subject to §112, ¶ 6.
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`Finally, in its brief, ParkerVision cites TEK Global v. Sealant Sys. Int’l, Inc., which held
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`that structure recited in dependent claims is relevant to determining whether §112, ¶ 6 applies to
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`a non-“means” term. PV Br. at 8. Unable to distinguish TEK, Intel brushes off its holding as
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`9
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`dicta. It is not. Indeed, in TEK, the Court specifically analyzed whether §112, ¶ 6 applied to a
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`non-“means” term in view of dependents claims.6
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`2.
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`Intel’s construction is wrong.
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`Even assuming that §112, ¶ 6 applies (which it does not), Intel’s structure is wrong. As
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`discussed in Sections IIA-B above, Intel improperly seeks to exclude portions of the
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`specification in order improperly narrow §112, ¶ 6 structure and equivalents.
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`In its opening brief, ParkerVision identified Figures 17, 19, 23, 53A and 53A-1 and their
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`corresponding descriptions as part of the structure. PV Br. at 9 n. 4. But Intel asserts that (1)
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`Figures 17, 19 and 23 should not be included because these figures are “empty black boxes,” and
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`(2) Figures 53A and 53A-1 should not be included because these figures show components for
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`down-converting but not delay. Intel is wrong. Tellingly, Intel avoids a detailed discussion of
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`these figures because it is unhelpful to its position.
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`First, down-convert and delay modules 1708, 1908, 2308 of Figures 17, 19, 23 are not
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`empty black boxes. Though they are shown as boxes, they are not empty. Instead, the
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`specification provides a description of what is inside these boxes (e.g., aliasing module of
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`Figures 53A, 53A-1). See ’706 patent, 28:16-60. Tellingly, if the images of Figure 53A or 53A-1
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`were included directly in modules 1708, 1908, 2308, then Figures 17, 19, 23 would be just like
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`Figure 26. The way in which the patentee chose to express embodiments should not cause
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`Figures 17, 19, 23 to be treated differently than Figure 26 as Intel does.
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`Thus, Figures 17, 19, 23 and their corresponding description should be included in any
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`6 Intel quotes cases to make them appear to counter TEK. They do not. Unlike here, both of
`Intel’s cited cases involve terms that use the word “means” and the plaintiffs sought to avoid the
`result of using “means.” In both cases, Intel’s quote was the court stating that it looks at the
`specification for construing §112, ¶ 6 structure and the dependent claim, and court-made
`doctrine of claim differentiation cannot alter how §112, ¶ 6 structure is determined.
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`construction. Indeed, the down-convert and delay modules 1708, 1908, 2308 also have physical
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`inputs/outputs connected to certain other components. These physical inputs/outputs are part of
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`the structure.7
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`Second, Intel reimagines the law regarding §112, ¶ 6. Intel asserts that Figures 17, 19, 23,
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`53A, 53A-1 should not be included as structure because they do not individually disclose the
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`structure for performing the “complete” claimed function. Intel Br. at 5. This is nonsense. The
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`structure that performs the function – regardless of whether it is found in one figure or spread out
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`amongst multiple, related figures – is part of §112, ¶ 6 structure. Again, that the patentee chose
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`to express embodiments of the invention in different ways is of no moment.
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`Finally, the specification describes aliasing modules of Figures 53A and 53A-1 as
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`structures of down-convert and delay modules 1708, 1908, 2308, 2624. ’706 patent, 28:20-60.
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`Intel, however, asserts that the aliasing modules of Figures 53A and 53A-1 “simply down-
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`convert, but do not delay.” Intel Br. at 5-6. Intel is wrong. The opening and closing of a switch
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`down-converts an input signal to produce a sample and a capacitor delays the sample. Steer
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`Decl. ¶¶ 15-16.
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`Even assuming Intel is correct and Figures 53A and 53A-1 illustrate only the down-
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`conversion portion (not the delay portion) of the down-convert and delay modules, the
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`components in these figures are still part of the structure and, thus, should be included in any
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`§112, ¶ 6 structure.
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`7 In complicated circuits, not only are the components themselves relevant, but the physical
`inputs/outputs and which/how components are connected together are important to the structure
`of circuits and their equivalents.
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`11
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`B.
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`“frequency translator” (claim 34)
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`1.
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`§112, ¶ 6 does not apply
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`This term does not use “means” and, thus, there is a presumption that §112, ¶ 6 does not
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`apply. In its opening brief, ParkerVision pointed out that (1) the term is “frequency translator”
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`not simply “module” or “circuit” and (2) “frequency translator” includes a switch, storage
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`element (e.g., capacitor) and their connections and, thus, connotes structure. PV Br. at 33-34; see
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`also Steer Decl. ¶ 21. Unable to substantively respond to ParkerVision’s positions, Intel yet
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`again pulls the same tricks as it does with “down-convert and delay module.” For the same
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`reasons set forth in Section IV.A.1 above, §112, ¶ 6 should not apply.
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`2.
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`Intel’s construction is wrong.
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`But even assuming that §112, ¶ 6 applies (it does not), Intel’s function and structure are
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`wrong. Yet again, Intel improperly seeks to exclude figures and corresponding descriptions from
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`the specification to improperly narrow the structural scope and equivalents.
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`In its opening brief, ParkerVision identified that Figures 11, 12, 17, 19, 23, 30, 53A and
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`53A-1,8 and their corresponding descriptions, as part of the structure. PV Br. at 33 n. 17. Intel
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`seeks to omit these portions for the same reasons it provided with regard to the “down-convert
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`and delay module.” As set forth in Section IV.A.2, Intel is wrong.
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`C.
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`“said input sample”, “said sample” (claims 1, 6, 7, 34)
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`In its opening brief, ParkerVision explained that Intel is using its construction to re-write
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`the claim language – re-arranging/changing words and negating the claimed relationship between
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`the sample and the input signal. PV Br. at 10. Intel has no substantive response. So Intel states
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`8 Intel’s brief ignores Figures 11, 12 and 30 altogether. With regard to Figures 11, 12 and 30,
`though the frequency translators 1108, 1204, 3006 are shown as boxes, they are not empty.
`Instead, the specification provides a description of the components.’706 patent, 28:29-41.
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`that it merely seeks to assist the jury – a ruse. A jury is certainly capable of reading claims and
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`understanding that the terms refer back to the earlier mention of the terms.
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`D.
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`“delay module” (claims 1, 7, 34, 140)
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`1.
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`§112, ¶ 6 does not apply
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`This term does not use “means” and, thus, there is a presumption that §112, ¶ 6 does not
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`apply. In its opening brief, ParkerVision pointed out that (1) the term is “delay module” not
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`merely “module,” and (2) as set forth in the specification, “delay modules” include switches,
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`capacitors, inductors and/or resistors and, thus, connote structure. PV Br. at 11.
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`Again, Intel ignores that the patent relates to circuits, which have physical components.
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`And again, unable to substantively respond to ParkerVision’s positions, Intel skirts the issue by
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`reimagining the law. Intel asserts that “delay module” does not have a “well-understood specific
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`structural meaning” or “well-known specific structure.” Intel Br. at 8, 9. Again, what is telling is
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`Intel’s use of “specific,” “well-known” and “well-understood” structure. But whether a skilled
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`person knows the specific type of “delay module” and whether the module is well-known or well-
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`understood is beside the point. The issue is whether a skilled person would understand the term
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`to connote structure. Here, even Intel and its expert identify structures (switches, capacitors,
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`inductors and/or resistors) that make up a delay module.9 See Dkt. 41-9 ¶¶ 70-74. As such, a
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`skilled person would understand that a “delay module” connotes structure. Steer Decl. ¶ 23.
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`9 Intel again plays games. Intel keys in on ParkerVision’s mention of a capacitor. Intel Br. at 9.
`Intel asserts that delay modules are more than just a capacitor and, thus, a capacitor, by itself,
`cannot be the structure of a delay module. Intel misses the point of ParkerVision mentioning a
`capacitor. ParkerVision did not need to list additional structures. Whether it is a capacitor by
`itself or combined with other structures, the fact that a delay module uses any structure means
`that the delay module connotes structure and §112, ¶ 6 does not apply.
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`2.
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`Intel’s construction is wrong.
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`Even assuming that §112, ¶ 6 applies (it does not), Intel’s structure is wrong.
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`a.
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`Intel improperly seeks