Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 1 of 24
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`FUTURE LINK SYSTEMS, LLC
`
`
`
`Plaintiff,
`
`Civil Action No. 6:21-cv-00263-ADA
`
`v.
`
`APPLE INC.,
`
`Defendant.
`
`FUTURE LINK SYSTEMS, LLC
`
`Plaintiff,
`
`v.
`
`BROADCOM INC., BROADCOM
`CORP.,
`
`Defendants.
`
`FUTURE LINK SYSTEMS, LLC
`
`Plaintiff,
`
`v.
`
`QUALCOMM INCORPORATED,
`QUALCOMM TECHNOLOGIES, INC.,
`
`Defendants.
`
`FUTURE LINK SYSTEMS, LLC
`
`Plaintiff,
`
`v.
`
`REALTEK SEMICONDUCTOR
`CORPORATION,
`
`Defendant.
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`JURY TRIAL DEMANDED
`
`Civil Action No. 6:21-cv-00264-ADA
`
`JURY TRIAL DEMANDED
`
`Civil Action No. 6:21-cv-00265-ADA
`
`JURY TRIAL DEMANDED
`
`Civil Action No. 6:21-cv-00363-ADA
`
`JURY TRIAL DEMANDED
`
`DEFENDANTS APPLE INC., BROADCOM INC., BROADCOM CORP.,
`QUALCOMM INC., QUALCOMM TECHNOLOGIES, INC. AND
`REALTEK SEMICONDUCTOR CORP.’S REPLY CLAIM CONSTRUCTION BRIEF
`
`U.S. PATENT NOS. 7,917,680; 6,317,804; and 6,807,505
`
`
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`

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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 2 of 24
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`TABLE OF CONTENTS
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`Page
`
`I.
`
`DISPUTED CLAIM CONSTRUCTIONS ..........................................................................1
`
`A.
`
`B.
`
`C.
`
`D.
`
`E.
`
`F.
`
`G.
`
`H.
`
`“A circuit arrangement for interfacing a plurality of functional blocks to
`one another in an integrated circuit device, the circuit arrangement
`comprising” ’804 Patent, Cl. 1 .................................................................................1
`
`“functional block[s]” ’804 Patent, Cls. 1, 2, 9, 10, 17, 40 .......................................2
`
`“Serial Port[s]” ’804 Patent, Cls. 1–5, 8–10, 14, 17, 40 ..........................................3
`
`“serial command, data and clock interconnects” ’804 Patent, Cls. 1, 40 ................6
`
`“selectively couple” ’804 Patent, Cls. 1, 9, 17 .........................................................6
`
`“packet” ’680 Patent, Cls. 1, 7, 8, 20 .......................................................................8
`
`“packet-based communications” (asserted claim 1) / “communicating
`packet data” (asserted claim 8) / “communicate the packets” (asserted
`claim 20) ................................................................................................................10
`
`“performance-based communications order” (asserted claim 1) / “order . . .
`as a function of the communications priority and performance rules”
`(asserted claim 8) / “order to the packets based upon the generated
`protocol-based ordering data and performance-based rules” (asserted
`claim 20) ................................................................................................................12
`
`I.
`
`“internal CPU-based link” ’680 Patent, Cl. 15 ......................................................14
`
`CONCLUSION ..............................................................................................................................15
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`i
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 3 of 24
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`
`
`TABLE OF AUTHORITIES
`
`Page
`
`Cases
`Arctic Cat Inc. v. GEP Power Prods.,
` 919 F.3d 1320 (Fed. Cir. 2019).................................................................................................. 1
`Arthur A. Collins, Inc. v. N. Telecom Ltd.,
` 216 F.3d 1042 (Fed. Cir. 2000).................................................................................................. 9
`Brookhill-Wilk 1, LLC. v. Intuitive Surgical, Inc.,
` 334 F.3d 1294 (Fed. Cir. 2003).................................................................................................. 5
`Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc.,
` 289 F.3d 801 (Fed. Cir. 2002).................................................................................................... 1
`Carrum Tech., LLC v. United Pats., LLC
` No. 2020-2204 (Fed. Cir. Aug. 13, 2021) ................................................................................ 12
`Intel Corp. v. Future Link Sys., LLC,
` No. IPR2016-1401 (P.T.A.B. Dec. 30, 2016) ..................................................................... 12-14
`LG Elecs., Inc. v. Bizcom Elecs., Inc.,
` 453 F.3d 1364 (Fed. Cir. 2006).................................................................................................. 8
`Morton Int’l, Inc. v. Cardinal Chem. Co.,
` 5 F.3d 1464 (Fed. Cir. 1993).................................................................................................... 15
`O2 Micro Int’l Ltd. v. Beyond Innovation Tech. Co.,
` 521 F.3d 1351 (Fed. Cir. 2008)............................................................................................ 9, 11
`Phillips v. AWH Corp.,
` 415 F.3d 1303 (Fed. Cir. 2005).................................................................................................. 3
`Power2B, Inc. v. Samsung Elecs. Co.,
` Case No. 6:20-CV-01183-ADA (Nov. 10, 2021) ................................................................... 15
`Terlep v. Brinkmann Corp.,
` 418 F.3d 1379 (Fed. Cir. 2005).............................................................................................. 2, 3
`V-Formation, Inc. v. Benetton Grp. SpA,
` 401 F.3d 1307 (Fed. Cir. 2005).................................................................................................. 9
`Vitronics Corp. v. Conceptronic, Inc.,
` 90 F.3d 1756 (Fed. Cir. 1996).................................................................................................... 5
`
`
`
`
`
`
`ii
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 4 of 24
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`The Defendants jointly submit this reply brief pursuant to the Court’s Joint Agreed
`
`Scheduling Order, to construe the terms of U.S. Patent Nos. 7,917,680 (the “’680 patent”);
`
`6,317,804 (the “’804 patent”); and 6,807,505 (the “’505 patent”). ECF No. 29 at 3.
`
`I.
`
`DISPUTED CLAIM CONSTRUCTIONS
`
`A.
`
`“A circuit arrangement for interfacing a plurality of functional blocks to one
`another in an integrated circuit device, the circuit arrangement comprising”
`’804 Patent, Cl. 1
`
`The preamble is not limiting where the body of a claim “describes a structurally complete
`
`invention.” Catalina Mktg. Int’l, Inc. v. Coolsavings.com, Inc., 289 F.3d 801, 809 (Fed. Cir.
`
`2002). FLS’s arguments confirm that the preamble does not add structure to what is recited in
`
`the body of the claim, but rather merely requires that the arrangement is “in” a certain type of
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`device. Pl. Br. 1 (“the claimed ‘circuit arrangement’ is ‘in an integrated circuit device.’”).
`
`The specification does not support FLS’s position. FLS alleges that “every embodiment
`
`of the ’804 Patent connects functional blocks together within an integrated circuit device” (Pl.
`
`Br. 3), but that is not correct. In addition to being used in “integrated circuit devices,” the patent
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`discloses that “serial interconnects consistent with the invention” can be used in “data processing
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`systems.” ’804 Patent at 19:66-20:3. It then discloses an embodiment in Figs. 11-12 in which a
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`“system controller 202” that is “using a concurrent serial interconnect consistent with the
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`invention” can be used to connect “external devices” to each other, i.e., devices that are not in
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`the same integrated circuit. Id. at 20:13-14.
`
`FLS further fails to meaningfully contest Defendants’ argument that the preamble merely
`
`recites an intended purpose. It attempts to distinguish Artic Cat on the basis that the preamble
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`there recited “what the invention was for, not what the invention was structurally comprised in,”
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`but the Federal Circuit understood the preamble to be referring to a power distribution module in
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`a personal recreational vehicle. Arctic Cat Inc. v. GEP Power Prods., 919 F.3d 1320, 1328 (Fed.
`
`
`
`1
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`

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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 5 of 24
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`Cir. 2019) (“module . . . in a personal recreational vehicle”).
`
`B.
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`“functional block[s]” ’804 Patent, Cls. 1, 2, 9, 10, 17, 40
`
`In arguing that the patent’s explicit definition is “an example of what a functional block
`
`may include,” and that the specification’s examples are “non-limiting,” Pl. Br. 4, FLS ignores
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`that the written description states that it is “refer[ring] to herein as functional blocks” the “more
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`advanced components” whose common attribute is that they are “configured to perform one or
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`more high level functions in a design.” ’804 Patent at 1:45-51. Although the specification uses
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`the word “typically,” it goes on to explain that components are referred to functional blocks
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`“insofar as” they have the important attribute of performing one or more high level functions.
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`This requirement to perform one or more high level functions is likewise repeated in the patent’s
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`explicit definition of “functional block” to include “any logic circuitry configured to perform
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`one or more high level functions in an integrated circuit device design.” ’804 Patent at 4:40-51
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`(emphasis added). The touchstone of the specification’s definition is the performance of high
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`level functions, which is part of Defendants’ construction. See Defs. Br. 6.
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`Defendants’ construction does not, as FLS implies, ignore that the specification provides
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`an open set of exemplary functional blocks. To the contrary, it uses “such as” to illuminate the
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`meaning of “high level function” to a lay jury without limiting the construction to those specific
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`examples: “such as that of microprocessors, memory controllers, communications interface
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`controllers, etc.” See Terlep v. Brinkmann Corp., 418 F.3d 1379, 1382 (Fed. Cir. 2005).
`
`Defendants’ construction stays true to the patent’s definition and the role the recited
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`functional blocks play in the alleged invention. According to the patent, the increase in
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`“complexity of the generic components” such as the “more advanced components [that] typically
`
`replicate higher level functions . . . referred to herein as functional blocks” resulted in a
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`“difficulty associated with the use of components such as functional blocks aris[ing] from the
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`
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`2
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`

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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 6 of 24
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`need for the various components in a design to communicate with and transfer information
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`among one another.” ’804 Patent at 1:41-59 (emphases added); see also id. at 2:21-23, 2:57-60.
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`FLS’s redundancy arguments necessarily fail as FLS did not put forth a construction
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`limiting “interconnections” to high level functions and simply reverses the teaching of the patent.
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`Pl. Br. 6. As the specification teaches, the complexity of the functional blocks gives rise to the
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`utility of the alleged interconnection invention, not the other way around. Finally, FLS’s
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`definition (as “a logical block that performs a particular function,” Pl. Br. 4) is a litigation-
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`inspired attempt to walk back the patent’s explicit definition of functional block and should be
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`rejected. ’804 Patent at 4:41-42; see also id. at 1:45-51.
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`C.
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`“Serial Port[s]” ’804 Patent, Cls. 1–5, 8–10, 14, 17, 40
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`Defendants’ construction captures the meaning of a serial port as disclosed in the intrinsic
`
`record and set forth in reliable, contemporaneous technical dictionaries. The serial port
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`described in the ’804 patent has three lines: a control line, a command line, and a data line. This
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`dispute focuses on how data is sent over the data line. Because each port has a single data line,
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`data is necessarily sent serially, that is, “one bit a time.” See Defs. Br. Exs. B, C, D, F.1
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`Contrary to FLS’s argument, a serial port does not transmit more than one data bit
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`simultaneously, i.e., at the same point in time. In an effort to contradict this fact, FLS focuses on
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`the patent’s disclosure of multiple data lines (plural) within a network. But the Defendants do
`
`not dispute that the patent discloses the use of multiple serial ports. Indeed, the patent
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`contemplates multiple functional blocks in a network, each of which has a serial port. But the
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`salient point is that each serial port has just one data line. See ’804 Patent at Fig. 1, 5:41:53 and
`
`
`1 FLS criticizes the Defendants’ cited dictionary definitions because they “do not establish
`were authored by persons of skill in the art.” Pl. Br. 8. FLS cites no legal support for such a
`requirement. The Defendants rely on technical dictionaries in the field, as preferred by the
`Federal Circuit. Phillips v. AWH Corp., 415 F.3d 1303, 1318 (Fed. Cir. 2005).
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`
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`3
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 7 of 24
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`Fig. 2, 13:64-14:52. For example, in both Figs. 1 and 2, there are multiple serial ports shown
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`that, collectively, have multiple “data lines.” Likewise, column 5, lines 41-53, cited by FLS,
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`recites “data lines” in the sense that five serial ports 50-58 each include a data line. Id. at 5:41-
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`53. But there is nothing in the specification contemplating that a single serial port has multiple
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`data lines. To the contrary, the specification distinguishes parallel ports that necessarily have
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`“multiple lines so that multiple bits of information can be transmitted simultaneously.” ’804
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`Patent at 2:9-11 (emphasis added). FLS studiously avoids Fig. 7B, precisely because it shows
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`that a “serial port” transmits data one bit at a time. That should end the matter.
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`FLS does not cite any support for its notion that a serial port includes more than one data
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`line but instead attempts to focus on “other potential differences between serial and parallel
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`ports.” But those differences do not support its construction. Just because “only one component
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`can transmit information over a parallel bus at a time,” or, as FLS states, “control information
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`and data typically share the same lines in a parallel bus” (Pl. Br. 7), this does not mean that a
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`serial port has multiple data lines. Indeed, the ’804 patent states, in an unqualified fashion, that
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`“parallel bus architectures require a relatively large number of lines” teaching away from any
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`notion that a serial port has multiple lines. ’804 Patent at 2:23-24. Faced with the complete lack
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`of disclosure supporting its multiple data line theory, FLS argues that the Defendants’
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`construction is a disclaimer of the plain meaning of “serial port.” Pl. Br. 7. To the contrary, as
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`shown by the intrinsic and extrinsic evidence cited, the Defendants’ construction captures the
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`plain and ordinary meaning of the term.
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`In its transparent attempt to contradict the intrinsic evidence, FLS reaches for irrelevant
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`extrinsic sources that post-date the ’804 patent’s November 30, 1998 filing date, and do not, in
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`any event, purport to define “port,” much less “serial port.” Its lead reference was published
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`4
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 8 of 24
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`over a year after the ’804 patent was filed and describes data “pipelines” used inside
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`microprocessors—not serial ports. Pl. Br. 2. Such technology is unrelated to the context of the
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`’804 patent. Although this paper coined the phrase “byte-serial implementation” to describe its
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`pipelines, it has no bearing on the meaning of “serial port” at the time of the ’804 patent, and
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`thus does “not reflect the meanings that would have been attributed to the words in dispute.”
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`Brookhill-Wilk 1, LLC. v. Intuitive Surgical, Inc., 334 F.3d 1294, 1299 (Fed. Cir. 2003).
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`FLS’s other extrinsic references are similar: each post-dates the ’804 patent; none
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`discloses a serial port. The PCI Express Specification was published over five years after the
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`patent’s filing date, and discloses a proprietary “link” architecture. Pl. Ex. 3, at 30. The PCI
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`Express Specification plainly uses the term serial to describe serial “lanes,” where in each lane,
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`bits are transferred one at a time. See Pl. Ex. 3, at 152-53; id. at 155 (“Ordered sets are always
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`transmitted serially on each Lane”); id. at 202. The DVI Specification was published in 1999
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`and discloses a similar “Link Architecture” specific to that standard. Pl. Ex. 4, at 24. The DVI
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`Specification likewise does not disclose the use of multiple lines on a single serial port but
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`instead is a video interface specification that discloses multiple “channels” with each channel
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`being a separate serial channel. Id. at 24 (“The transmitter contains three identical encoders,
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`each driving one serial T.M.D.S. data channel.”). Patent No. 7,802,049 was filed four years after
`
`the ’804 patent, and discloses a link interface similar to that disclosed in FLS’s other extrinsic
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`references. Pl. Ex. 5, at 3:4-27; Pl. Ex. 5, at 4:45-49 (describing multiple serial lanes, each of
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`which transmit data one bit at a time). None of these extrinsic, later-arising technologies utilize
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`“serial ports,” and none may be used to “vary or contradict the claim language.” Vitronics Corp.
`
`v. Conceptronic, Inc., 90 F.3d 1756, 1538 (Fed. Cir. 1996).
`
`Finally, Judge Stark did not find that the ’804 patent “contemplates sending data over
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`5
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 9 of 24
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`multiple lines simultaneously.” Pl. Br. 11 (emphasis added). Instead, Judge Stark found that a
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`serial port can transmit multiple pieces of “information” (e.g., data, command, and/or clock
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`information) simultaneously. While that is true, it is not the defining characteristic of a serial
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`port. As shown above, the intrinsic evidence and all of the contemporaneous technical
`
`dictionaries of record establish that, at the time of the invention, a person of ordinary skill would
`
`have understood that a serial port transmits data “one bit at a time.”2
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`D.
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`“serial command, data and clock interconnects” ’804 Patent, Cls. 1, 40
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`FLS acknowledges that “the adjective ‘serial’ modifies each of the ‘command, data, and
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`clock’ interconnects.” Pl. Br. 11. FLS also appears to acknowledge that the claim term requires
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`only one of each type of serial interconnect. Id. at 11-12 (“FLS’s alternative construction . . .
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`only requires one of each type of interconnect”). If this understanding is correct, there does not
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`appear to be a live dispute between the parties. Nevertheless, the Defendants believe that their
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`construction is clearer as to the latter point.
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`E.
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`“selectively couple” ’804 Patent, Cls. 1, 9, 17
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`The Defendants’ brief explained that, in prosecution and consistent with the specification,
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`the patentee traversed a rejection over “programmable” art to avoid prior art that disclosed pre-
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`configured pathways. Defs. Br. 15-16.
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`FLS does not dispute that, in prosecution, the patentee distinguished its claims from the
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`prior art by arguing that the prior art did disclose programmable pathways as opposed to
`
`
`2 FLS’s intrinsic evidence in support of its position that data is sent over the command line is
`without basis. As a preliminary matter, the claims require “separate serial command, data and
`clock interconnects,” so to the extent the specification does disclose that an interconnect
`communicates both command and data, any such embodiment is not relevant to the asserted
`claims. ’804 Patent at 2:40-41 (criticizing arrangements where “control information and data . . .
`share the same lines”). But FLS is simply wrong about the disclosure it relies on. The “Port
`Status Command” FLS refers to (Pl. Br. 10) nowhere describes the “Port ID of Responding Port”
`on the command line as “data.” ’804 Patent at 14:32-49. That is pure attorney argument.
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`6
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 10 of 24
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`“dynamically configurable” pathways. Defs. Br. 17; Ex. A, at 133. The construction should
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`make clear to the jury the distinction the patentee has drawn between the claimed “dynamic”
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`configuration and the one-time configuration the patentee distinguished in prosecution.
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`FLS also argues that the patentee was not defining “selectively couple,” but was rather
`
`merely defining the term “selectable.” Pl. Br. 12-13. But FLS does not suggest there is any
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`substantive difference between “selectively” and “selectable.” Nor does FLS explain why the
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`patentee would be distinguishing art based on a “selectable” term not found in the claims.
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`Instead, the patentee was distinguishing the claim language from the prior art. The patentee’s
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`sentence was relying on the claimed “interface controller” limitation, and referenced the claimed
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`“logical” communications channels:
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`Through the use of a plurality of serial ports and an interface controller that are
`integrated onto the same integrated circuit device as a plurality of functional blocks,
`Applicants’
`claimed
`configuration
`provides
`dynamically-configurable
`(‘selectable’) pathways between functional blocks to enable rapid and concurrent
`point-to-point communications between such functional blocks over ‘logical’
`communications channels.
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`Defs. Br. Ex. A, at 133 (emphases added).
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`Further, FLS’s challenge that “‘dynamically’ is in some respects broader than
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`‘selectively’ because ‘dynamic’ coupling does not suggest that the coupling must be done
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`‘selectively’” is without merit. Pl. Br. 13. To leave no ambiguity, the Defendants are attempting
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`neither to broaden nor to narrow the plain meaning of “selectively couple,” but rather simply to
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`ascribe the scope the patentee plainly gave it in prosecution.3
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`Lastly, FLS argues that the Defendants’ construction results in some inconsistency with
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`surrounding claim language, pointing out that the Defendants’ construction recites “pathways”
`
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`3 That said, the Defendants accept FLS’s representation that its understanding of the plain
`meaning of “selectively coupling” is narrower than the Defendants’ proposal.
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`
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`7
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 11 of 24
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`while the claim already recites “logical communication channels.” Pl. Br. 13. However, the
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`Defendants’ proposal is consistent with arguments in prosecution, which recited both “pathways”
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`and the logical communications channel. Defs. Br. Ex. A, at 133 (“Applicants’ claimed
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`configuration provides dynamically-configurable (‘selectable’) pathways” to enable
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`communications “over ‘logical’ communications channels.”). Similarly, FLS argues that the
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`Defendants’ construction adds a potential redundant “between.” Pl. Br. 13. This is not an
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`“inconsistency”; at most, it is a redundancy. The root source of any redundancy is the patentee’s
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`own arguments. Defs. Br. Ex. A, at 133 (“provides . . . pathways between functional blocks to
`
`enable . . . communications between such functional blocks” (emphasis added)). There is no
`
`inconsistency or lack of clarity.
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`F.
`
`“packet” ’680 Patent, Cls. 1, 7, 8, 20
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`The Defendants’ construction of “packet” captures the meaning of the term as used by the
`
`inventor, by taking the definition expressly set forth in the industry standard directly referenced
`
`by the ’680 patent itself. Defs. Br. 17-18; Ex. G, at 22. This approach is indisputably proper.
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`LG Elecs., Inc. v. Bizcom Elecs., Inc., 453 F.3d 1364, 1375 (Fed. Cir. 2006). FLS protests that
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`the ’680 patent does not reference the specific definition of “packet” in the PCI Express Spec.
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`Pl. Br. 16. But the same was true in LG, yet the Federal Circuit recognized that a standard
`
`referenced in the patent to illustrate the preferred embodiment provided the meaning of the term
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`as used by the inventor. Id. at 1374-75.
`
`FLS objects that, in LG, “there was no evidence that the term at issue . . . had a plain
`
`meaning in the art aside from the specification” referenced in the patent. Pl. Br. 17. But the
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`Federal Circuit in LG reaffirmed decisions holding that a patent citing a standard that “sheds
`
`light on the meaning of a term . . . may indicate not only the meaning of the term to persons
`
`skilled in the art”—i.e., the plain meaning that FLS touts—“but also that the patentee intended to
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`8
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 12 of 24
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`adopt that meaning.” Id. (quoting Arthur A. Collins, Inc. v. N. Telecom Ltd., 216 F.3d 1042,
`
`1045 (Fed. Cir. 2000)). FLS does not attempt to distinguish the numerous cases holding that a
`
`standard cited in the patent specification is intrinsic evidence that directly illuminates the proper
`
`construction of a claim term.4 See, e.g., Defs. Br. 18; V-Formation, Inc. v. Benetton Grp. SpA,
`
`401 F.3d 1307, 13111 (Fed. Cir. 2005) (collecting cases). In any case, FLS does not argue that
`
`“packet” has a single well-understood meaning in the art, so construing the term is appropriate.
`
`O2 Micro Int’l Ltd. v. Beyond Innovation Tech. Co., 521 F.3d 1351, 1361 (Fed. Cir. 2008).
`
`Separately, the Defendants’ construction is correct because it incorporates two widely
`
`recognized and important aspects of a “packet,” as that term is used in the art. First, it shows that
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`a packet is transmitted atomically across a communication link—as a “fundamental unit of
`
`information transfer,” not one that is broken apart and transmitted at disparate times or across
`
`different links.5 This is immediately clear from the PCI Express Spec, and moreover, each
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`dictionary definition cited by the Defendants imposes this requirement. See Ex. C, at 66 (“a unit
`
`of data”); Ex. H, at 385 (“a unit of information transmitted as a whole”); Ex. I, at 359 (“a group
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`of consecutive characters”); Ex. J, at 364 (“[a] group of bits … transmitted as a composite
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`whole”). The dictionaries FLS cites likewise requires packets to be transmitted atomically. Ex.
`
`7, at 4 (“transmitted as a group”); Ex. 8, at 2; Ex. 9, at 4 (“unit of data”).6
`
`
`4 The CRSR Defendants have never argued that the PCI Express Spec “defines ‘packet’
`generally,” but rather that the definition of “packet” expressly given in the PCI Express Spec
`(and included as intrinsic evidence by reference) is the best guide to the meaning of the term.
`5 Moreover, data from a single packet must be communicated as a “unit” or it would be
`incapable of being “ordered” or prioritized with other “packets” as required by the claim.
`6 FLS suggests that this construction is confusing because the phrase “fundamental unit of
`information transfer” could refer to a single bit (binary digit). See Pl. Br. 15. But FLS cannot
`seriously dispute that a POSITA could understand and correctly apply the PCI Express Spec—
`PCI Express has been incorporated into uncountable products designed across the world for over
`two decades. See, e.g., Ex. N, Fig. 2-2, PCI Express Spec at 44 (showing an example packet
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 13 of 24
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`Second, the Defendants’ construction clarifies that a packet is transmitted sequentially,
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`with a header “followed by” an optional data payload. This is indisputably true for PCI Express
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`“packets.” Ex. G, at 21 (defining “header” as “[a] set of fields that appear at the front of a
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`Packet” (emphasis added)); id. at 20 (defining “data payload” as “information following the
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`header in some packets” (emphasis added)). Multiple dictionaries show packets are well-
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`understood in the industry to include “a header” that contains “source and destination addresses,”
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`Ex. H, at 385. Other dictionaries do not use the term “header,” but acknowledge that address
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`information appears at the front of packets. See, e.g., Ex. I, at 359 (describing “packets that
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`begin with labels indicating the machine to which they are addressed”); Ex. J, at 364 (describing
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`“addressing information defining the source and the destination of the packet”).7
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`FLS’s proposed construction captures neither of these important aspects of a “packet”
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`and is thus both ambiguous and inadequate. The Court should adopt the definition of “packet”
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`expressly set out in the PCI Express Spec.
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`G.
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`“packet-based communications” (asserted claim 1) / “communicating packet
`data” (asserted claim 8) / “communicate the packets” (asserted claim 20)
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`FLS’s response to the Defendants’ construction is based on a demonstrably false premise.
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`FLS brushes aside the Delaware District Court’s construction because, it says, the Delaware
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`Court did not consider its current “plain and ordinary meaning” construction. Pl. Br. 18 (“FLS
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`did not propose a ‘plain and ordinary meaning’ construction, but instead argued that ‘packet-
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`based communications’ included any communications that were, in some sense, ‘based on
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`packets.’”). Yet the following image appears in FLS’s brief in the Delaware Court:
`
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`with a “TLP header” in the first bytes); see also id. at 59 (headers include, e.g., a related
`address).
`7 FLS asserts that a POSITA “would not have understood packets as being defined by [a
`header] or restricted to [a header].” But it offers no support for that factual assertion other than
`attorney argument. Pl. Br. 15.
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 14 of 24
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`Ex. L, at 28 (FLS stating that “plain meaning … should control”). FLS not only misrepresents
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`its position in prior litigation, but admits to taking a different position as to the “plain and
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`ordinary meaning” of these terms. FLS contrasts its currently proposed “plain and ordinary
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`meaning”—“communication of packets”—with its “plain and ordinary meaning” in the
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`Delaware action, “communications based on packets.” Pl. Br. 18. A “plain and ordinary
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`meaning” construction would resolve nothing, as FLS has argued more than one “plain meaning”
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`of the term. See O2 Micro, 521 F.3d at 1361.
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`The Defendants’ constructions (which were adopted by the Delaware Court) are correct
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`because the “intrinsic evidence establishes that the claims and patent as a whole are directed to
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`communication and processing of information as packets.” Intel Corp. v. Future Link Systems,
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`LLC, No. 14-377-LPS, 2016 WL 4162648, at *11 (D. Del. Aug. 2, 2016). Without citing
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`intrinsic evidence, FLS argues that “communication as packets” is too limiting because a
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`“network…does not necessarily implement ‘communication as packets.” Pl. Br. 17. That misses
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`the point. FLS’s claims require “communication as packets” because the invention is directed to
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`the ordering of packets. The specification refers to “ordering of the packets,” packet-based
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`processing, and “the order in which the packets are to be processed,” all of which requires
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`communication as packets, not simply communicating data that is somehow “based on” packets.
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`See, e.g., ’680 Patent at Abstract; 2:37-39, 41-42, 2:65-3:2. Furthermore, the applicant
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`distinguished the prior art in prosecution because the amended claims require “performance-
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`based ordering of the previously-ordered packets.” Ex. K, at 7-8. Where the intrinsic evidence
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`uniformly requires the ordering of packets, which is predicated on data being communicated as
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`Case 6:21-cv-00263-ADA Document 47 Filed 12/01/21 Page 15 of 24
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`packets, whether some hypothetical “network” untethered to the patent may possibly do
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`something else is irrelevant. See Carrum Tech., LLC v. United Pats., LLC, No. 2020-2204, 2021
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`WL 3574209 (Fed. Cir. Aug. 13, 2021) (rejecting “plain meaning” of a claim phrase that was
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`“untethered to the specification”).
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`H.
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`“performance-based communications order” (asserted claim 1) / “order . . .
`as a function of the communications priority and performance rules”
`(asserted claim 8) / “order to the packets based upon the generated protocol-
`based ordering data and performance-based rules” (asserted claim 20)
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`The Defendants’ constructions make explicit what FLS has already admitted: (1) that
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`each independent claim of the ’680 patent requires an ordering step applying protocol-based
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`rules, followed by a second separate ordering step applying performance-based rules, and (2) that
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`the performance-based rules applied are independent from the protocol whose rules are applied.
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`FLS concedes that each independent claim recites “the protocol and performance steps …
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`as two separate steps,” that “the claims … cannot be satisfied by a method or device that
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`includes only a single step,” and that “the performance-based step in each claim must come after
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`the protocol-based step.” Pl. Br. 19, 22. The structure of each claim r