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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 1 of 23
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`EXHIBIT 9
`EXHIBIT 9
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`case 620-ev-01216-ADA DocumerMBIMITTTANMTERILEAEA
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 2 of 23
`US006309926B1
`(10) Patent No:
`«2 United States Patent
`US 6,309,926 B1
`Bell et al.
`(45) Date of Patent:
`*Oct. 30, 2001
`
`
`(54) THIN RESIST WITH NITRIDE HARD MASK
`FOR GATE ETCH APPLICATION
`
`(75)
`
`Inventors: Scott A. Bell, San Jose; Christopher F.
`Lyons, Fremont; Harry J. Levinson,
`Saratoga; Khanh B. Nguyen, San
`:
`:
`Mateo; Fei Wang; Chih Yuh Yang,
`both of San Jose, all of CA (US)
`
`(73) Assignee: Advanced Micro Devices, Sunnyvale,
`CA (US)
`
`(*) Notice:
`
`This patent issued on a continued pros-
`ecution application filed under 37 CFR
`1.53(d), and is subject to the twenty year
`patent
`term provisions of 35 U.S.C.
`154(a)(2).
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`US.C. 154(b) by 0 days.
`
`.
`
`7/1994 Kiharaetal. .
`5,332,648
`11/1995 Schmidtetal. .
`5,464,538
`4/1996 Tennantet al.
`.
`5,510,230
`5/1996 Tennantet a.
`5,521,031
`oo ‘i100 auetal .
`5679608
`101997 Cheun ‘et
`al
`3679,
`g etal. .
`5,786,262
`7/1998 Jang etal. .
`5,817,567
`10/1998 Jangetal. .
`.- 438/604
`.
`5,897,366 *
`4/1999 Shiralagi et al.
`w.. 438/714
`5,928,964 *
`7/1999 Brankner...........
`5,930,634 *
`7/1999 Hause etal. ..
`. 438/307
`5,998,264 * 12/1999 Wu oe.
`«+ 438/260
`
`
`.-. 430/316
`6,027,861 *
`2/2000 Yu etal.
`9/2000 Koet al...
`.. 438/723
`6,117,791 *
`6,159,829 * 12/2000 Warren etal. ....
`... 438/530
`6,225,168 *
`5/2001 Gardneret al. oe 438/287
`* cited by examiner
`
`
`
`
`Primary Examiner—John F. Niebling
`Assistant Examiner—Jennifer M. Kennedy
`(74) Attorney, Agent, or Firm—Amin & Turocy, LLP
`(57)
`ABSTRACT
`
`(21) Appl. No.: 09/205,211
`A method of forming a gate structure is provided. In the
`.
`method,a nitride layer is formed on a gate material layer. An
`Filed:
`(22)
`Dec. 4, 1998
`_—ultra-thin photoresist layer is formed on the nitride layer.
`(SL)
`Tint, C07 cecccccssccsssscssssesssssseseesesssnsee HOLL 21/8242
`The ultra-thin photoresist
`layer is patterned with short
`(52) US. Che acces
`438/257; 438/264
`
`wavelength radiation to define a pattern for the gate. The
`(58) Field of Search oo... 438/257, 264
`, ultra-thin photoresist layer is used as a mask duringafirst
`
`(56)
`References Cited
`etch step to transfer the gate pattern to the nitride layer. The
`first etch step includes an etch chemistry that is selective to
`the nitride layer over the ultra-thin photoresist layer. The
`nitride layer is used as a hard mask during a secondetch step
`to form the gate by transferring the gate pattern to the gate
`‘material layer via the secondetch step.
`
`U.S. PATENT DOCUMENTS
`.
`1506,006 Dios Hescampeotal.
`.
`4,804,637 *
`2/1989 Smayling et al. cscs 437/52
`5,040,020
`8/1991 Rauschenbachetal. .
`5,079,600
`1/1992 Schnuret al.
`.
`
`28 Claims, 11 Drawing Sheets
`
`
`
`

`

`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 3 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 3 of 23
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`U.S. Patent
`
`Oct. 30, 2001
`
`Sheet 1 of 11
`
`US 6,309,926 B1
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` yyJOUd|‘614
`
`
`
`
`

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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 4 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 4 of 23
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`U.S. Patent
`
`Oct. 30, 2001
`
`Sheet 2 of 11
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`US 6,309,926 B1
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`

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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 5 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 5 of 23
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`U.S. Patent
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`Oct. 30, 2001
`
`Sheet 3 of 11
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`US 6,309,926 B1
`
`Fig. 6
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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 6 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 6 of 23
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`U.S. Patent
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`Oct. 30, 2001
`
`Sheet 4 of 11
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`US 6,309,926 B1
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`Fig. 8
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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 7 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 7 of 23
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`U.S. Patent
`
`Oct. 30, 2001
`
`Sheet 5 of 11
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`US 6,309,926 B1
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`a— 126
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`Fig. 12
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`

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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 8 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 8 of 23
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`U.S. Patent
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`Oct. 30, 2001
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`Sheet 6 of 11
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`US 6,309,926 B1
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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 9 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 9 of 23
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`U.S. Patent
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`Oct. 30, 2001
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`Sheet 7 of 11
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`US 6,309,926 B1
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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 10 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 10 of 23
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`U.S. Patent
`
`Oct. 30, 2001
`
`Sheet 8 of 11
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`US 6,309,926 B1
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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 11 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 11 of 23
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`U.S. Patent
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`Oct. 30, 2001
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`Sheet 9 of 11
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`US 6,309,926 B1
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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 12 of 23
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`U.S. Patent
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`US 6,309,926 B1
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`Oct. 30, 2001
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`Sheet 10 of 11
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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 13 of 23
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`U.S. Patent
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`Oct. 30, 2001
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`Sheet 11 of 11
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`US 6,309,926 B1
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`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 14 of 23
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`US 6,309,926 B1
`
`1
`THIN RESIST WITH NITRIDE HARD MASK
`FOR GATE ETCH APPLICATION
`
`TECHNICAL FIELD
`
`invention generally relates to photo-
`The present
`lithography, and moreparticularly relates to a method of
`forming sub-micron gates using short wavelength radiation
`and ultra-thin photoresists.
`BACKGROUND OF THE INVENTION
`
`2
`(EUV) radiation and/or deep UV radiation in fabricating
`gates. As noted above, EUV and deep UV radiation are
`preferred radiation sources in lithographic processes where
`fine resolution is desired. The short wavelengths of these
`types of radiation afford for fine patterning (e.g., critical
`feature sizes <0.25 um). However, these types of radiation
`are highly absorbed by photoresist material which conse-
`quently limits the depth of penetration by the radiation into
`the photoresist material.
`By employing a nitride layer to be patterned as a hard
`mask for use in connection with etching the gates,
`the
`In the semiconductor industry, there is a continuing trend
`present invention affords for expanding available etch chem-
`toward higher device densities. To achieve these high
`istries useable in EUV and/or deep UV lithographic pro-
`densities, there has been and continues to be efforts toward
`cesses. In particular, these types of lithographic processes
`scaling down device dimensions(e.g., at submicron levels)
`require the use of very thin photoresists as a result of the
`on semiconductor wafers. In order to accomplish such high
`depth of penetration limitations of the short wavelength
`device packing density, smaller and smaller feature sizes are
`radiation. Such very thin photoresists are limited in their
`required. This may include the width and spacing ofinter-
`capacity as etch barriers due to the thickness thereof.
`connecting lines, spacing and size of memory cells, and
`is
`In the present
`invention,
`the ultra-thin photoresist
`surface geometry of various features such as corners and
`employed in patterning and etching the nitride thereunder to
`edges.
`form a hard mask. A gate pattern formed in the photoresist
`The requirement of small features with close spacing
`with the short wavelength radiation is transferred to the
`between adjacent features requires high resolution photo-
`nitride layer byafirst etch step. The patterned nitride layer
`lithographic processes.
`In general,
`lithography refers to
`is used as a hard mask for a subsequent second etch step to
`processes for pattern transfer between various media. It is a
`etch a gate material layer (e.g., polysilicon or metal) so as to
`technique used for integrated circuit fabrication in which a
`form a gate corresponding to the gate pattern. This meth-
`siliconslice, the wafer, 1s coated uniformly with a radiation-
`odology is used in conjunction with fabrication steps
`sensitive film, the photoresist, and an exposing source (such
`employed in making the particular device(s) (e.g., memory
`as optical light, x-rays, or an electron beam) illuminates
`cells, analog devices) using the gate. Thus,
`the present
`selected areas of the surface through an intervening master
`invention affords for taking advantage of the fine resolution
`template, the mask, for a particular pattern. The photoresist
`patterning available from EUV and deep UV lithographic
`receives a projected image of the subject pattern. Once the
`processes and mitigates the limitations associated therewith
`imageis projected, it is indelibly formed in the photoresist.
`with respect to etch chemistry.
`The projected image may beeither a negative or a positive
`One specific aspect of the present invention relates to a
`image of the subject pattern. Exposure of the photoresist
`method of forming a gate structure. In the method, a nitride
`through a photomask causes the image area to becomeeither
`layer is formed on a gate material
`layer. An ultra-thin
`more or less soluble (depending on the coating) in a par-
`photoresist layer is formed on the nitride layer. The ultra-
`ticular solvent developer. The more soluble areas are
`thin photoresist layer is patterned with short wavelength
`removed in the developing process to leave the pattern
`radiation to define a pattern for the gate. The ultra-thin
`image in the photoresist as less soluble polymer.
`40
`photoresist layer is used as a mask duringafirst etch step to
`Projection lithography is a powerful and essential tool for
`transfer the gate pattern to the nitride layer. The first etch
`microelectronics processing. As feature sizes are driven
`step includes an etch chemistry that is selectiveto the nitride
`smaller and smaller, optical systems are approaching their
`layer over the ultra-thin photoresist layer. The nitride layer
`limits caused by the wavelengths of the optical radiation. A
`is used as a hard mask during a second etch step to form the
`recognized way of reducing the feature size of circuit
`gate by transferring the gate pattern to the gate materiallayer
`elements is to lithographically image the features with
`via the second etch step.
`radiation of a shorter wavelength. “Long” or “soft” x-rays
`Anotherspecific aspect of the present invention relates to
`(extreme ultraviolet (EUV), deep ultraviolet (DUV)), wave-
`a memorycell structure including a plurality of memory
`length range of 5-200 nm are now at
`the forefront of
`research in an effort to achieve the smaller desired feature
`cells, each of the memorycells including a floating gate, at
`sizes.
`least two of the floating gates being separated by a distance
`below about 0.18 um. In forming the memorycell structure
`Although EUV lithography provides substantial advan-
`a first nitride layer is formed onafirst gate material layer. A
`tages with respect to achieving high resolution patterning,
`first ultra-thin photoresist layer is formed on the first nitride
`the shorter wavelength radiation is highly absorbed by the
`layer. The ultra-thin photoresist layer is patterned with short
`photoresist material. Consequently, the penetration depth of
`wavelength radiation to define a pattern for the floating
`the radiation into the photoresist is limited. The limited
`gates. The ultra-thin photoresist layer is used as a mask
`penetration depth of the shorter wavelength radiation
`duringafirst etch step to transfer the floating gate pattern to
`requires the use of ultra-thin photoresists so that the radia-
`the first nitride layer. The first etch step includes an etch
`tion can penetrate the entire depth of the photoresist in order
`chemistry that is selective to the first nitride layer over the
`to effect patterning thereof. However, the thinness of such
`first ultra-thin photoresist layer. The first nitride layeris used
`ultra-thin photoresists results in the etch resistance thereof
`as a hard mask during a second etch step to form the floating
`being relatively low. In other words,
`the etch protection
`gates by transferring the floating gate pattern to the first gate
`afforded by ultra-thin photoresists is limited which in turn
`material layer via the second etch step. An interpoly dielec-
`limits the EUV lithographic process.
`tric layer is formed over the floating gates. A second gate
`SUMMARYOF THE INVENTION
`material layer is formed over the interpoly dielectric layer.
`Asecond nitride layer is formed on the second gate material
`layer. A second ultra-thin photoresist layer is formed on the
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`The present invention relates to a method to facilitate
`lithographic processes employing extreme ultra-violet
`
`

`

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`US 6,309,926 B1
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`4
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`3
`second nitride layer. The second ultra-thin photoresist layer
`is patterned with short wavelength radiation to define a
`FIG. 1 is a prior art schematic cross-sectional illustration
`pattern for control gates. The second ultra-thin photoresist
`of a conventional patterned resist used in the formation of
`layer is used as a mask duringathird etch step to transfer the
`gates;
`control gate pattern to the second nitride layer. The third etch
`step includes an etch chemistrythat is selective to the second
`FIG. 2a is a perspective illustration of a memory cell
`nitride layer over the second ultra-thin photoresist layer. The
`structure formed in accordance with one aspect of the
`second nitride layer is used as a hard mask during a fourth
`present invention;
`etch step to form the control gates bytransferring the control
`FIG. 2b is a schematic illustration of a stacked gate
`gate pattern to the second gate material layer via the fourth
`memorycell in accordance with one aspect of the present
`etch step.
`invention;
`Still another aspect of the present invention relates to a
`FIG. 3 is a schematic cross-sectional illustration of a
`methodof forming a gate. A nitride layer is formed on a gate
`materiallayer, the nitride layer having a thickness within the
`range of 50 A-2000 A. An ultra-thin photoresist layer is
`formed on the nitride layer, the ultra-thin photoresist layer
`having a thickness within the range of 50 A-2000 A. The
`ultra-thin photoresist layer is patterned with short wave-
`length radiation to define a pattern for the gate, the short
`wavelength radiation falling within the range of about 11 nm
`to 13 nm. Theultra-thin photoresist layer is used as a mask
`during a first etch step to transfer the gate pattern to the
`nitride 1 layer. Thefirst etch step includes an etch chemistry
`that
`is selective to the nitride layer over the ultra-thin
`photoresist layer. The nitride layer is used as a hard mask
`during a second etch step to form the gate by transferring the
`gate pattern to the gate material layer via the second etch
`step.
`invention relates to a
`Another aspect of the present
`method for fabricating a memory cell structure. A first
`nitride layer is formed on a first gate material layer. A first
`ultra-thin photoresist layer of FIG. 7 after the patterning step
`ultra-thin photoresist layer is formed on the first nitride
`is substantially complete in accordance with one aspect of
`layer. The ultra-thin photoresist layer is patterned with short
`the present invention;
`wavelength radiation to define a pattern for the floating
`FIG. 9 is a schematic cross-sectional illustration of the
`gates. The ultra-thin photoresist layer is used as a mask
`nitride layer of FIG. 8 undergoing an etching step in
`35
`duringafirst etch step to transfer the floating gate pattern to
`accordance with one aspect of the present invention;
`the first nitride layer. The first etch step includes an etch
`FIG. 10 is a schematic cross-sectional illustration of the
`chemistry that is selective to the first nitride layer over the
`nitride layer of FIG. 9 after the etching step is substantially
`first ultra-thin photoresistlayer. The first nitride layeris used
`complete in accordance with one aspect of the present
`as a hard mask during a second etch step to form the floating
`invention;
`gates by transferring the floating gate pattern to the first gate
`FIG. 11 is a schematic cross-sectional illustration of the
`material layer via the second etch step. An interpoly dielec-
`layer of FIG. 10 undergoing an etching step in
`poly I
`tric layer is formed over the floating gates. A second gate
`accordance with one aspect of the present invention;
`material layer is formed over the interpoly dielectric layer.
`FIG. 12 is a schematic cross-sectional illustration of the
`Asecond nitride layer is formed on the second gate material
`layer. Asecond ultra-thin photoresist layer is formed on the
`first gate material layer of FIG. 11 after the etching step is
`second nitride layer. The second ultra-thin photoresist layer
`substantially complete in accordance with one aspect of the
`is patterned with short wavelength radiation to define a
`present invention;
`FIG. 13 is a schematic cross-sectional illustration of the
`pattern for control gates. The second ultra-thin photoresist
`layer is used as a mask duringathird etch step to transfer the
`nitride hard mask of FIG. 12 undergoing a stripping process
`50
`control gate pattern to the second nitride layer. The third etch
`in accordance with one aspect of the present invention;
`step includes an etch chemistrythat is selective to the second
`FIG. 14 is a schematic cross-sectional illustration of the
`nitride layer over the second ultra-thin photoresist layer. The
`structure of FIG. 13 after the nitride hard mask has been
`second nitride layer is used as a hard mask during a fourth
`removed in accordance with one aspect of the present
`etch step to form the control gates bytransferring the control
`invention;
`gate pattern to the second gate material layer via the fourth
`FIG. 15 is a perspective illustration of the structure of
`etch step.
`FIG. 14;
`To the accomplishmentof the foregoing and related ends,
`FIG. 16 is a schematic cross-sectional illustration of an
`the invention, then, comprises the features hereinafter fully
`described and particularly pointed out in the claims. The
`following description and the annexed drawingsset forth in
`detail certain illustrative embodiments of the invention.
`These embodimentsare indicative, however, of but a few of
`the various ways in which the principles of the invention
`may be employed. Other objects, advantages and novel
`features of the invention will become apparent from the
`following detailed description of the invention when con-
`sidered in conjunction with the drawings.
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`substrate including field oxide and channel regions with a
`poly I layer formed thereon in accordance with one aspect of
`the present invention;
`FIG. 4 is a perspective view of the structure of FIG. 3;
`FIG. 5 is a schematic cross-sectional illustration of a
`
`nitride layer formed over the first gate material layer of
`FIGS. 3 and 4 in accordance with one aspect of the present
`invention;
`FIG. 6 is a schematic cross-sectional illustration of an
`ultra-thin photoresist layer formed over the nitride layer of
`FIG. 5 in accordance with one aspect of the present inven-
`tion;
`FIG. 7 is a schematic cross-sectional illustration of the
`
`ultra-thin photoresist layer of FIG. 6 undergoing a patterning
`step in accordance with one aspect of the present invention;
`FIG. 8 is a schematic cross-sectional illustration of the
`
`ONOlayer formed overthefirst gate material layer of FIGS.
`14 and 15 in accordance with one aspect of the present
`invention;
`FIG. 17 is a perspective illustration of the structure of
`FIG. 15;
`FIG. 18 is a schematic cross-sectional illustration of a
`
`second gate material layer formed over the ONO layer of
`FIGS. 16 and 17 in accordancewith one aspect of the present
`invention;
`
`

`

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`US 6,309,926 B1
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`5
`FIG. 19 is a perspective illustration of the structure of
`FIG. 18;
`FIG. 20 is a schematic cross-sectional illustration of a
`
`nitride layer formed over the second gate material layer of
`FIGS. 18 and 19 in accordance with one aspect of the present
`invention;
`FIG. 21 is a schematic cross-sectional illustration of the
`structure of FIG. 20 from another direction in accordance
`
`with one aspect of the present invention;
`FIG. 22 is a schematic cross-sectional illustration of an
`ultra-thin photoresist layer formed over the nitride layer of
`FIG. 21 in accordance with one specific aspect of the present
`invention;
`FIG. 23 is a schematic cross-sectional illustration of the
`
`ultra-thin photoresist layer of FIG. 22 undergoing a pattern-
`ing step in accordance with one aspect of the present
`invention;
`FIG. 24 is a schematic cross-sectional illustration of the
`ultra-thin photoresist layer of FIG. 23 after the patterning
`step is substantially complete in accordance with one aspect
`of the present invention;
`FIG. 25 is a schematic cross-sectional illustration of the
`
`nitride layer of FIG. 24 undergoing an etching step in
`accordance with one aspect of the present invention;
`FIG. 26 is a schematic cross-sectional illustration of the
`
`nitride layer of FIG. 25 after the etching step is substantially
`complete in accordance with one aspect of the present
`invention;
`FIG. 27 is a schematic cross-sectional illustration of the
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`FIG. 1 is a cross-sectional illustration of a conventional
`photoresist layer 20 being used in the formation of gate(s).
`As shown, the photoresist layer 20 is substantially thick
`(e.g., 5,000-10,000 A). The photoresist layer 20 is shown
`patterned so as to define a gate which will be etched into an
`underlying gate material layer 22 so as to form the gate.
`However, the thickness of the photoresist layer 20 is not
`conducive for use with short wavelength radiation because
`these types of radiation would be highly absorbed by the
`photoresist layer 20 and not penetrate the entire thickness “t”
`of the layer 20. As a result, such a conventional scheme for
`forming a gate would not be able to take advantage of the
`improved resolution of patterning offered by the short wave-
`length radiation.
`Turning now to the present invention in detail, FIG. 2a
`illustrates a memory device 30 including a plurality of
`memory cells 30' formed in accordance with the present
`invention. The memory device 30 includes a substrate 32,
`which comprises regionsof thick oxide (field oxide) 34 and
`thin oxide (tunnel oxide) 36. Thefield oxide 34 provides for
`electrically insulating transistors from one another. Although
`only a few memory cells 30' are shown for ease of
`understanding, it is to be appreciated that the memory cell
`structure 30 may include thousands or even millions of such
`memory cells 30'. The memory cells 30' include a floating
`gate 38 (e.g., poly I gate, alternatively a first metal gate), an
`interpoly dielectric layer 40, a control gate 44 (e.g., poly II
`gate, alternatively a second metal gate), and a protective
`capping layer 50. Through the use of short wavelength
`radiation and an ultra-thin photoresist, the present invention
`provides for forming the memory cells 30' substantially
`close together. More particularly, a distance “d,” between
`the floating gates 38 of adjacent memory cells 30' may be
`less than 0.251 um.
`FIG. 25 is a schematic illustration of the memorycell 30'
`which typically includes a source 62, a drain 64, and a
`channel 66 in the substrate 30; and a stacked gate structure
`70 overlying the channel 66. The stacked gate 70 includes a
`thin gate dielectric layer 72 (commonly referred to as the
`tunnel oxide) formed on the surface of the substrate 32. The
`tunnel oxide layer 72 coats a portion of the top surface of the
`silicon substrate 32 and serves to support an array of
`different layers directly over the channel 66. The stacked
`gate 70 includes the lower mostorfirst film layer 38, such
`as doped polycrystalline silicon (polysilicon or poly I) layer
`orfirst metal layer (e.g., Cu, Al) which servesas the floating
`gate 38 that overlies the tunnel oxide 72. On top ofthe first
`gate material layer 38 is the interpoly dielectric layer 40. The
`interpoly dielectric layer 40 is preferably a multilayer insu-
`lator such as an oxide-nitride-oxide (ONO)layer having two
`The present invention will now be described with refer-
`oxide layers sandwichinga nitride layer, or as an alternative
`ence to the drawings, wherein like reference numerals are
`can be another dielectric layer such as tantalum pentoxide.
`usedto refer to like elements throughout. The method of the
`Finally, the stacked gate 70 includes the second gate material
`present invention will be described with reference to the
`layer 44 (e.g., second polysilicon layer (poly ID) which
`formation of gates using a photolithographic process
`serves as a polysilicon control gate, or second metal layer
`employing radiation of short wavelength (e.g., EUV radia-
`such as Cu or Al) overlying the ONO layer 40. The control
`tion and/or deep UVradiation) and an ultra-thin photoresist.
`gates 44 of the respective memory cells 30' that are formed
`The following detailed description is of the best modes
`in a given row share a common word line (WL) associated
`presently contemplated by the inventors for practicing the
`with the row ofcells. In addition, the drain regions 64 of the
`invention. It should be understood that the description of
`respective cells are connected together by a conductive bit
`these preferred embodiments are merely illustrative and that
`line (BL). The channel 66 of the cell 30' conducts current
`they should not be taken in a limiting sense. Furthermore,
`between the source 62 and the drain 64 in accordance with
`although the present invention is described primarily within
`an electric field developed in the channel 66 by the stacked
`the context of forming memorycells and gates thereof, it is
`gate structure 70.
`to be appreciated that the present invention may be applied
`The memory cell 30' (e.g., flash memorycell) operates in
`to forming other gates (e.g., analog gate, gates for other
`types of memory cells), and such applications are intended
`the following manner. The memorycell 30' is programmed
`by applyingarelatively high voltage V,, (e.g. approximately
`to fall within the scope of the present invention.
`
`second gate material layer of FIG. 26 undergoing an etching
`step in accordance with one aspect of the present invention;
`FIG. 28 is a schematic cross-sectional illustration of the
`second gate material layer of FIG. 27 after the etching step
`is substantially complete in accordance with one aspect of
`the present invention;
`FIG. 29 is a schematic cross-sectional illustration of the
`
`nitride hard mask of FIG. 28 undergoing a stripping process
`in accordance with one aspect of the present invention;
`FIG. 30 is a schematic cross-sectional illustration of the
`
`memorystructure substantially complete in accordance with
`one aspect of the present invention; and
`FIG. 31 is a perspective illustration of the memory
`structure in accordance with one aspect of the present
`invention.
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`

`

`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 17 of 23
`Case 6:20-cv-01216-ADA Document 41-9 Filed 10/06/21 Page 17 of 23
`
`US 6,309,926 B1
`
`8
`appreciated that although specific layering materials are
`identified in the preferred embodiment, any materials suit-
`able for carrying out the present invention may be employed
`and fall within the scope of the claims. A first gate material
`layer 78 (which may comprise doped polycrystalline silicon
`(polysilicon or poly I) or a metal such a Cu or Al, for
`example) is shown laid down over the substrate 32. FIG. 4
`is a perspective illustration of the partially complete memory
`device structure of FIG. 3.
`
`15
`
`20
`
`25
`
`30
`
`7
`12 volts) to the control gate 44 and a moderately high
`voltage Vp, (e.g., approximately 9 volts) to the drain 64 in
`orderto produce “hot” (high energy) electrons in the channel
`66 near the drain 64. The hot electrons accelerate across the
`tunnel oxide 72 and into the floating gate 38 and become
`trapped in the floating gate 38 because the floating gate 38
`is surrounded by insulators (the interpoly dielectric 40 and
`the tunnel oxide 72). As a result of the trapped electrons, a
`threshold voltage (V,) of the memorycell 30' increases by
`10
`Turning now to FIG. 5,afirst nitride layer 80 is formed
`about 3 to 5 volts. This changein the threshold voltage (and
`overthe first gate material layer 78. The nitride layer 80 will
`thereby the channel conductance) of the memory cell 30'
`serve as a hard mask during etching of the underlyingfirst
`created by the trapped electrons is what causes the memory
`gate material layer 78. Any suitable technique for forming
`cell 30' to be programmed.
`the nitride layer 80 may be employed such as Low Pressure
`To read the memorycell 30', a predetermined voltage V,
`Chemical Vapor Deposition (LPCVD), Plasma Enhanced
`that
`is greater than the threshold voltage of an unpro-
`Chemical Vapor Deposition (PECVD), High Density
`grammed memorycell, but less than the threshold voltage of
`Chemical Plasma Vapor Deposition (HDPCVD), sputtering
`a programmed memorycell, is applied to the control gate 44.
`or high density plasma chemical vapor deposition
`If the memory cell 30' conducts, then the memory cell 30'
`(HDPCVD)techniques to a thickness suitable for serving as
`has not been programmed (the memory cell 30' is therefore
`a hard mask for a selective etch of the first gate material
`at a first logic state, e.g., a zero “O”). Conversely, if the
`layer 78. Thus, for example, in one aspect of the present
`memory cell 30' does not conduct, then the memory cell 30'
`invention the thickness of the nitride layer 80 is between the
`has been programmed (the memorycell 30' is therefore at a
`range of about 50 A-5000 A.In another aspect, the thickness
`second logic state, e.g., a one “1”). Thus, each memorycell
`of the nitride layer 80 is between the range of about 50
`30' may be read in order to determine whether it has been
`A-3000 A. In another aspect, the thickness of the nitride
`programmed (and therefore identify the logic state of the
`layer 80 is between the range of about 50 A-2000 A. In
`memory cell 30’).
`another aspect,
`the thickness of the nitride layer 80 is
`In order to erase the memory cell 30', a relatively high
`between the range of about 50 A-1500 A.In another aspect,
`voltage Vs (e.g, approximately 12 volts) is applied to the
`the thickness of the nitride layer 80 is between the range of
`source 62 and the control gate 44 is held at a ground
`about 50 A-1000 A.In still another aspect, the thickness of
`potential (V,,=0), while the drain 64 is allowed to float.
`the nitride layer 80 is between the range of about 50 A-500
`A.
`Under these conditions, a strong electric field is developed
`across the tunnel oxide 72 between the floating gate 38 and
`the source region 62. The electrons that are trapped in the
`floating gate 38 flow toward and clusterat the portion of the
`floating gate 38 overlying the source region 62 and are
`extracted from the floating gate 38 and into the source region
`62 by way of Fowler-Nordheim tunneling through the tunnel
`oxide 72. Consequently, as the electrons are removed from
`the floating gate 38, the memory cell 30' is erased.
`Having described a structural arrangement of the memory
`cell 30', attention is now brought
`to fabrication of the
`memory device 30 in accordance with the novel photolitho-
`graphic process of the present invention.
`The gates 38 and 44 are formed employing photolitho-
`graphic techniques utilizing short wavelength radiation and
`ultra-thin photoresists. Accordingly, substantially smaller
`dimensionsof the gates 38 and 44 are achieved as compared
`to gates formed in accordance with the prior art technique
`discussed with respect to FIG. 1. Furth