Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 1 of 118
`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 1 of 118
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`EXHIBIT 24
`EXHIBIT 24
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 2 of 118
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`Appendix A1
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 3 of 118
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`
`
`Analysis of Infringement of U.S. Patent No. 6,660,651 by Western Digital Corporation
`(Based on Public Information Only)
`
`Plaintiff Ocean Semiconductor LLC (“Ocean Semiconductor”), provides this preliminary and exemplary infringement analysis with respect to
`
`infringement of U.S. Patent No. 6,660,651, entitled “ADJUSTABLE WAFER STAGE, AND A METHOD AND SYSTEM FOR PERFORMING
`PROCESS OPERATIONS USING SAME” (the “’651 patent”) by Western Digital Corporation (“WD”). The following chart illustrates an
`exemplary analysis regarding infringement by Defendant WD’s semiconductor products, systems, devices, components, integrated circuits, and
`products containing such circuits, fabricated or manufactured using ASML’s semiconductor fabrication or manufacturing equipment and/or platforms
`(e.g., ASML’s TWINSCAN system). Such products include, without limitation, automotive products (e.g., iNAND® AT EU312, iNAND® AT
`EM122, iNAND® AT EM132, Automotive AT LD332, AT 132 (e.g., grades 2 and 3), AT 122 (e.g., grades 2 and 3), Industrial Wide Temp IX
`QD332, Industrial Ext Temp IX QD332, Industrial Ext Temp IX QD334, Industrial Wide Temp IX QD342, Commercial CL SN720, Commercial CL
`SN520), connected home products (e.g., iNAND® CH EM123/133, CH LD313, CH LD513, CH QD313, CH QD513, CH XB 513, CH XB 313, WD
`AV-25, WD AV-GP 1000, CL SN720, CL SN520, PC SA530), industrial and IoT products (e.g., iNAND® IX EM132, iNAND® IX EM122,
`iNAND® IX EU312, iNAND® IX MC EM131, Industrial IX LD342, Industrial IX LD332, Industrial IX QD342, Industrial IX QD332, Industrial IX
`QD334, Commercial CL SN720, Commercial CL SN520, Commercial PC SN730, Commercial X600, Commercial PC SA530), mobile products
`(e.g., MC EU521, MC EU511, MC EU311/d, MC EM131/c, MC EM121/b, MC EM111/a, Commercial CL QD501, Commercial CL QD301,
`Commercial CL QD101), and surveillance products (e.g. CL EM132/122, IX EM122 Wide Temp, IX EM122 Extended Temp, WD PurpleTM SC
`QD101 Ultra Endurance microSDTM Card), flash memory (e.g., 3D flash and NAND flash), RISC-V SweRVCore Family (e.g., EH1 and EH2)
`, and similar systems, products, devices, and integrated circuits (“’651 Infringing Instrumentalities”).
`
`The analysis set forth below is based only upon information from publicly available resources regarding the ’651 Infringing Instrumentalities,
`
`as WD has not yet provided any non-public information.
`
`Unless otherwise noted, Ocean Semiconductor contends that WD directly infringes the ’651 patent in violation of 35 U.S.C. § 271(g) by
`
`using, selling, and/or offering to sell in the United States, and/or importing into the United States, the ’651 Infringing Instrumentalities. The
`following exemplary analysis demonstrates that infringement. Unless otherwise noted, Ocean Semiconductor further contends that the evidence
`below supports a finding of indirect infringement under 35 U.S.C. § 271(b) in conjunction with other evidence of liability.
`
`Unless otherwise noted, Ocean Semiconductor believes and contends that each element of each claim asserted herein is literally met through
`
`WD’s provision or importation of the ’651 Infringing Instrumentalities. However, to the extent that WD attempts to allege that any asserted claim
`element is not literally met, Ocean Semiconductor believes and contends that such elements are met under the doctrine of equivalents. More
`specifically, in its investigation and analysis of the ’651 Infringing Instrumentalities, Ocean Semiconductor did not identify any substantial
`differences between the elements of the patent claims and the corresponding features of the ’651 Infringing Instrumentalities, as set forth herein. In
`
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`1
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 4 of 118
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`each instance, the identified feature of the ’651 Infringing Instrumentalities performs at least substantially the same function in substantially the same
`way to achieve substantially the same result as the corresponding claim element.
`
`Ocean Semiconductor notes that the present claim chart and analysis are necessarily preliminary in that Ocean Semiconductor has not
`obtained substantial discovery from WD nor has WD disclosed any detailed analysis for its non-infringement position, if any. Further, Ocean
`Semiconductor does not have the benefit of claim construction or expert discovery. Ocean Semiconductor reserves the right to supplement and/or
`amend the positions taken in this preliminary and exemplary infringement analysis, including with respect to literal infringement and infringement
`under the doctrine of equivalents, if and when warranted by further information obtained by Ocean Semiconductor, including but not limited to
`information adduced through information exchanges between the parties, fact discovery, claim construction, expert discovery, and/or further analysis.
`
`
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`2
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`

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`USP No. 6,660,651
`
`19. A method,
`comprising: providing a
`process chamber
`comprised of a wafer
`stage, said wafer stage
`having a surface that is
`adjustable;
`
`
`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 5 of 118
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`Infringement by the ’651 Infringing Instrumentalities
`The ’651 Infringing Instrumentalities provide a process chamber comprised of a wafer stage, the wafer stage
`having a surface that is adjustable.
`
`For example, each TWINSCAN system includes a process chamber. See ASML Corporate Responsibility Report
`2015, available at
`https://www.sec.gov/Archives/edgar/data/937966/000093796616000015/corporateresponsibiltyrepo.htm; see also
`ASML products, available at https://www.asml.com/en/products/duv-lithography-systems:
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`3
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`As an example, each TWINSCAN system includes a process chamber as shown below:
`
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`4
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 7 of 118
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`process chamber
`
`
`
`projection lens
`
`
`See ASML Twinscan Technical Backgrounder, available at
`See ASML Twinscan Technical Backgrounder, available at
`https://www.chiphistory.org/landmarks/lm_asml twinscan_step_and scan aligner 1990/ip
`asml twinscan_ step
`and
`https://www.chiphistory.org/landmarks/lm_asml_twinscan_step_and_scan_aligner_1990/ip_asml_twinscan_step_and
`
`scan_aligner_1990.htm (annotated).
`_scan_aligner_1990.htm (annotated).
`
`See also EUV Lithographytools shipping in 2018, available at https://www.nextbigfuture.com/2017/04/euv-
`See also EUV Lithography tools shipping in 2018, available at https://www.nextbigfuture.com/2017/04/euv-
`lithography-tools-shipping-in-2018.html:
`lithography-tools-shipping-in-2018.html:
`
`
`
`
`
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`5
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 8 of 118
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`
`
`
`TSMC uses, for example, ASML’s extreme ultraviolet (EUV) lithography systems on 5nm and 7nm products. See
`e.g., TSMC 5nm Technology, available at https://www.tsmc.com/english/dedicatedFoundry/technology/5nm.htm
`(“TSMC's 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high
`performance computing applications. It is scheduled to start risk production in the second half of 2019. TSMC's 5nm
`technology is the second available EUV process technology. It showed promising imaging capability with expected
`good wafer yield.”); see also TSMC Celebrates 25th Anniversary of the North American Technology Symposium,
`available at
`https://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&language=E&newsid=THGOWQTHTH
`(“The World’s first commercially available 7nm EUV in volume production in 2019”).
`
`As another example, the TWINSCAN system performs the method of providing a process chamber:
`
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`6
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`
`See ASML DUV Lithography Systems, available at https://www.asml.com/en/products/duv-lithography-
`systems/twinscan-nxt1980di (last visited Apr. 30 2019).
`
`The process chamber can be used for wafer exposure during lithography:
`
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`7
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 10 of 118
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`
`
`
`See See H. Butler, ASML Fellow, “A perspective on stage dynamics and control,” Mechatronic Systems
`Development, at 3, available at https://pdfs.semanticscholar.org/e49e/90dc78072b03036012e69a913fdfe4ddb935.pdf
`(last visited Apr. 30, 2020) (“Perspective on Stage Dynamics and Control”) (annotated).
`
`The process chamber includes an adjustable wafer stage having a surface that is adjustable:
`
`“In Figure 4, the table holding the wafer is called the mirror block because of the mirroring side surfaces, which
`allow interferometric position measurement (IFM).”
`
`See H. Butler, ASML Fellow, “Position Control in Lithographic Equipment [Applications of Control],” IEEE
`Control Systems (Nov. 2011), at 31 available at
`https://www.researchgate.net/profile/Hans_Butler/publication/224258614_Position_Control_in_Lithographic_Equ
`ipment_Applications_of_Control/links/5570590b08ae193af41ff41e/Position-Control-in-Lithographic-Equipment-
`Applications-of-Control.pdf (last visited Apr. 30, 2020) (“Position Control”).
`
`For example, the adjustable wafer stage or mirror block of the TWINSCAN system is shown below:
`
`
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`8
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`adjusting said surface of
`said wafer stage by
`actuating at least one of
`a plurality of pneumatic
`cylinders that are
`operatively coupled to
`said wafer stage to
`accomplish at least one
`of raising, lowering and
`varying a tilt of said
`surface of said wafer
`stage;
`
`
`
`
`
`See Applications Products and Business Opportunity at 6.
`
`The ’651 Infringing Instrumentalities adjust the surface of the wafer stage by actuating at least one of a plurality of
`pneumatic cylinders that are operatively coupled to said wafer stage to accomplish at least one of raising, lowering
`and varying a tilt of said surface of said wafer stage.
`
`For example, the TWINSCAN system adjusts the surface of the wafer stage by raising, lower, or tilting via wafer
`leveling using vertical actuators (e.g., in the “z direction”):
`
`“Vertical actuators, which are mounted between the air foot and mirror block, allow the mirror block to be moved
`in z direction, as well as in rotational directions around the x and y axes, called x and Ψ, respectively.”
`
`See Position Control at 41; see also id. at 38 (“For wafer leveling, the actuators drive the mirror block with respect
`to the air foot, and hence vertical reaction forces can directly enter the silent, vibration-free, metro-frame world.
`Leveling now needs to be performed during scanning, making use of the wafer-height measurement by the level
`sensor.”).
`
`As another example, the TWINSCAN system actuates one of the six Lorentz actuators that are mounted between
`the air foot and the wafer stage to accomplish at least one of raising, lowering and varying a tilt of the surface of
`the wafer stage:
`
`
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`9
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 12 of 118
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`
`“Vertical actuators, which are mounted between the air foot and mirror block, allow the mirror block to be moved
`in z direction, as well as in rotational directions around the x and y axes, called x and Ψ, respectively.”
`
`See Position Control at 41.
`
`Generally, the wafer stage is equipped with DOF Lorentz actuators (e.g., three DOF actuators for the horizontal
`directions and three DOF actuators for the vertical directions):
`
`“The table also had vertical movement directions for the purpose of focusing the wafer in the image plane of the
`lens, requiring a measurement of the distance of the wafer to the lens by means of a level sensor system. The
`horizontal stage position was measured by an interferometer system. The stage was guided by means of
`mechanical bearings ‘rolling’ over the motor beams. With regard to controlling the stage, the horizontal
`controllers (3-DOF) acted independently from the vertical directions (also 3-DOF).”
`
`See Perspective on Stage Dynamics and Control at 1.
`
`As an example, for the x and y direction, the wafer table is adjusted by three Lorentz actuators such that the stage
`floats over a granite stone by means of an air bearing and the Lorentz actuators are connected to this granite stone:
`
`
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`
`10
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 13 of 118
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`
`
`
`See Position Control at 31 (annotated).
`
`In total, the TWINSCAN includes 6-DOF Lorentz actuators and 6-DOF stage control, in addition to offline
`leveling:
`
`“In TWINSCANTM, a further perfection in the basic design was made by using balance masses, full 6-DOF
`Lorentz actuators and 6-DOF stage control, in addition to off-line levelling.”
`
`See Perspective on Stage Dynamics and Control at 3.
`
`As another example, the vertical directions of the wafer stage can be achieved using Lorentz actuators:
`
`“To avoid vibrations entering the mirror block, a Lorentz actuator is now also used for vertical directions, providing
`isolation in these directions as well. Because the required vertical range is smaller than 1 mm, no separate long-stroke
`motor is required. A 6DOF Lorentz-actuated block is the result”
`
`
`
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`11
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 14 of 118
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`See Position Control at 40.
`
` A
`
`
`
` diagram showing the vertical connection that facilitates the vertical movement of the wafer stage is shown below:
`
`
`
`
`See Position Control at 41 (annotated).
`
`In one example, the wafer stage rotates around the center of the lens above it in the vertical directions using the
`actuators:
`
`“The stage now rotates around the lens center instead of its center of mass. Especially in the vertical directions, the
`applicable rotations may show a high acceleration, depending on the vertical topology of the wafer surface.”
`
`See Position Control at 42.
`
`
`
`
`12
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 15 of 118
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`The wafer stage can also be tilted to help keep the wafer in focus:
`
`“The reason for this lies in the scanning levelling: when the stage has to tilt around a horizontal axis to keep the wafer
`in focus, the stage tends to rotate around its center of mass, introducing a horizontal shift on wafer level.”
`
`See Perspective on Stage Dynamics and Control at 2.
`
`The ’651 Infringing Instrumentalities position a wafer on the wafer stage.
`
`For example, the TWINSCAN system positions the wafer on the wafer stage:
`
`“After stepping the wafer to a new position, the wafer stage is allowed to wait until its position has settled such
`that the remaining error is sufficiently low before switching on the illuminating light. The MA and MSD after the
`step motion indicate the usability of the system for imaging.”
`
`See Position Control at 35.
`
`The wafer is also positioned onto the wafer stage so that exposure can start:
`
`“At the second stage, the wafer is loaded, and its surface is mapped in horizontal and vertical planes with respect
`to the stage itself. After the stage swap, the stage that is now positioned under the projection lens is aligned to the
`reticle in 6DOF by means of a through-the-lens optical system. With the wafer surface position known with
`respect to the stage and the stage position known with respect to the reticle, exposure can start.”
`
`See Position Control at 40.
`
`
`The ’651 Infringing Instrumentalities perform a process operation on the wafer position on the wafer stage.
`
`For example, the TWINSCAN system performs stepper imaging or double patterning as part of the step-and-scan
`in exposing a wafer:
`
`“After stepping the wafer to a new position, the wafer stage is allowed to wait until its position has settled such
`that the remaining error is sufficiently low before switching on the illuminating light. The MA and MSD after the
`step motion indicate the usability of the system for imaging.”
`
`See Position Control at 35.
`
`positioning a wafer on
`said wafer stage; and
`
`
`performing a process
`operation on said wafer
`positioned on said wafer
`stage.
`
`
`
`13
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`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 16 of 118
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`
`Once the wafer is loaded, and its surface is mapped in horizontal and vertical planes with respect to the stage itself,
`the stage positioned under the projection lens is aligned to the reticle by means of a through-the-lens optical system.
`With the wafer surface position known with respect to the stage and the stage position known with respect to the
`reticle, exposure can start:
`
`“Stage position measurement is now performed in all degrees of freedom by interferometers, with reference beams
`directed at the projection lens. This method provides a direct relative measurement of the position with respect to
`the lens. At the second stage, the wafer is loaded, and its surface is mapped in horizontal and vertical planes with
`respect to the stage itself. After the stage swap, the stage that is now positioned under the projection lens is aligned
`to the reticle in 6DOF by means of a through-the-lens optical system. With the wafer surface position known with
`respect to the stage and the stage position known with respect to the reticle, exposure can start.”
`
`See Position Control at 40.
`
`As another example, the TWINSCAN system performs a process operation on the wafer position on the wafer
`stage, as shown below:
`
`“A solution was found by equipping the system with two wafer stages [7]. While the first stage exposes the wafer,
`the second stage unloads the previous wafer from the tool, loads a new wafer on the stage, aligns the horizontal
`placement of the wafer on the stage, and measures the wafer height map used to focus the wafer during exposure.
`When both stages are finished with their tasks, the stages are swapped and a new cycle begins. In this way, the
`number of wafers that is processed is enlarged by removing overhead time from the expose cycle. The increased
`stage acceleration and speed further improves throughput.”
`
`See Position Control at 39-40; see also id. at 37:
`
`“Figure 16 shows a more detailed timing diagram of the stage movement during a scan. Figure 16(b) shows an
`acceleration setpoint profile, which in this example is a thirdorder profile instead of the previously used second-
`order profile. Figure 16(a) shows the velocity setpoint profile. At t5t0, the acceleration phase ends, and a constant
`velocity is reached. After a certain settling time, which allows the remaining controller error to be reduced to an
`acceptable value, the first point in the die to be exposed enters the illumination slit at t5t1. At t5t2, this first point
`on the die leaves the slit again. The stage-positioning errors in the interval 3t1, t2 4 determine the effect on overlay
`and imaging. Hence, the calculated MA and MSD values over this first interval correspond to the effect of
`
`
`
`14
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`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 17 of 118
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`positioning errors on the first point in the die. At t5t3, the last point of the die enters the slit, and, finally, at t5t4
`the die leaves the slit again, making the interval 3t3, t4 4 the last window over which MA and MSD values need to
`be calculated. Hence, the total scan length of the stage equals the length of the die, plus the height of the slit, plus
`the length needed for settling of the stage. After t5t4, the stage decelerates again to standstill or follows another
`trajectory that brings the stage to the start of the next die.”
`
`As a further example, “the ASML® TWINSCAN® NXE:3350B production-ready EVU system produces 125
`computer wafers per hour using 13.5 nm wavelength light.” See V. Marra, “ASML Advances Computing
`Breakthroughs with Multiphysics Modeling” at 4.
`
`As yet another example, the TWINSCAN system performs a process operation on the wafer position on the wafer
`stage:
`
`
`
`
`15
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`

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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 18 of 118
`
`
`See S. Miller, “Holistic View of Lithography for Double Patterning” (2009) at 25 (“Holistic View of
`Lithography”), ASML Sokudo Litho Breakfast Forum at 25, available at https://www.screen.co.jp/eng/spe/mt-
`images/SOKUDO_LBF2009_ASML.pdf (last visited June 15, 2021).
`
`As a further example, the ’651 Infringing Instrumentalities, including the TWINSCAN system, perform “Mask 1
`Etch”:
`
`
`
`
`
`
`16
`
`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 19 of 118
`
`
`
`
`“Figure 10. Work flow overview for test 2: imposing a pre-defined counter reticle heating fingerprint into the
`reticle to extend the TWINSCANTM K18 actuator range and reduce the intra-field overlay. The ASML
`TWINSCANTM was used for XPA read outs and the exposures. The RegC® tool was used to induce the pre-
`defined fingerprint into the reticle and correct the intra-field fingerprint.”
`
`See K. Gorhad et al., “Co-optimization of RegC® and TWINSCANTM corrections to improve the intra-field on-
`product overlay performance” at Fig. 10 (“Co-optimization of RegC® and TWINSCANTM Corrections”)
`available at https://www.semanticscholar.org/paper/Co-optimization-of-RegC-and-TWINSCAN-corrections-to-
`Gorhad-Sharoni/98d36fbae8f0d07a3051bcb3c29352db5ff172fc
`
`
`As a further example, the’651 Infringing Instrumentalities perform etch and deposition processes:
`
`
`
`
`17
`
`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 20 of 118
`
`
`See Y. Cao, “Machine learning in computational lithography,” (“Machine Learning in Computational
`Lithography”) at 15 (2019), available at https://www.ebeam.org/docs/SPIE2019-yu-cao.pdf (last visited June 19,
`2021).
`
`As a further example, the ’651 Infringing Instrumentalities perform etching, as shown below:
`
`
`
`
`
`
`18
`
`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 21 of 118
`
`
`See J. Koonmen, “Applications Products and Business Opportunity,” at 5.
`
`As a further example, the ’651 Infringing Instrumentalities “co-optimize[] its scanner process with etch and reticle
`process steps,” as shown below:
`
`
`
`
`
`
`19
`
`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 22 of 118
`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 22 of 118
`
`
`s Pattern Fidelity control with holistic co-optimization of
`scanner, etcher and mask
`
`ASML
`
`
`
`btot
`Leics)
`
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`etersteas)|
`
`
`After Etch
`After Litho
`
`et
`
`
`ea
`Bert te ae
`barb iris
`
`metrology
`
`
`
`(100% wafers)
`Metrology
`beam Metrology
`Metrology
`
`
`
`
`
`
`
`betel Rie geal
`
`Toe oat
`
`
`
`
` Computational
`eeeoes ob
`Lithography
`
`
`
`(https://electroiq.com/wp-content/uploads/2018/07/process-complexity.png)
`
`ASMLco-optimizes its scanner processwith etch andreticle process steps. Source: ASML
`
`
`See Process Complexity at 2; see also Scanner and Etch Co-optimized Corrections (showing “combining scanner
`See Process Complexity at 2; see also Scanner and Etch Co-optimized Corrections (showing “combining scanner
`and etch corrections in one control”):
`and etch corrections in one control”):
`
`
`
`
`
`
`
`20
`20
`
`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 23 of 118
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`
`
`The ’651 Infringing Instrumentalities comprise at least one of a deposition chamber and etching chamber.
`
`For example, the TWINSCAN system provides a process chamber that includes an etching chamber to perform
`etching:
`
`
`
`
`20. The method of claim
`19, wherein providing a
`process chamber
`comprises providing at
`least one of a deposition
`chamber and an etching
`chamber.
`
`
`
`21
`
`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 24 of 118
`
`
`See Holistic View of Lithography at 25.
`
`As a further example, the ’651 Infringing Instrumentalities, including the TWINSCAN system, perform “Mask 1
`Etch,” as shown below:
`
`
`
`
`
`
`22
`
`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 25 of 118
`
`
`“Figure 10. Work flow overview for test 2: imposing a pre-defined counter reticle heating fingerprint into the
`reticle to extend the TWINSCANTM K18 actuator range and reduce the intra-field overlay. The ASML
`TWINSCANTM was used for XPA read outs and the exposures. The RegC® tool was used to induce the pre-
`defined fingerprint into the reticle and correct the intra-field fingerprint.”
`
`See Co-optimization of RegC® and TWINSCANTM corrections at Fig. 10.
`
`As a further example, the’651 Infringing Instrumentalities perform etch and deposition processes, as shown below:
`
`
`
`
`
`
`23
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`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 26 of 118
`
`
`See Machine Learning in Computational Lithography at 15.
`
`As a further example, the ’651 Infringing Instrumentalities perform etching, as shown below:
`
`
`
`
`
`
`24
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`

`

`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 27 of 118
`
`
`See J. Koonmen, “Applications Products and Business Opportunity,” at 5.
`
`As a further example, the ’651 Infringing Instrumentalities “co-optimize[] its scanner process with etch and reticle
`process steps,” as shown below:
`
`
`
`
`
`
`25
`
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 28 of 118
`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 28 of 118
`
`
`N Pattern Fidelity control with holistic co-optimization of
`scanner, etcher and mask
`
`ASML
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`Pubic
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`ts wh th
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`Bare t g
`Barohe a
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`metrology
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`eth eee]
`gellela]
`beam Metrology
`
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`betel Rie geal
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`oe oat
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` Computational
`eeeoteby
`Lithography
`
`(https://electroiq.com/wp-content/uploads/2018/07/process-complexity.png)
`
`ASMLco-optimizes its scanner process with etch and reticle process steps. Source: ASML
`
`
`See P. Doe, “Process complexity means exponentially increasing data volumesand analysis challenges, with co-
`See P. Doe, “Process complexity means exponentially increasing data volumes and analysis challenges, with co-
`optimization across process steps,” (“Process Complexity”) at 2, Semiconductor Digest , available at
`optimization across process steps,” (“Process Complexity”) at 2, Semiconductor Digest , available at
`https://sst.semiconductor-digest.com/2018/07/process-complexity-means-exponentially-increasing-data-volumes-
`https://sst.semiconductor-digest.com/2018/07/process-complexity-means-exponentially-increasing-data-volumes-
`
`and-analysis-challenges-with-co-optimization-across-process-steps/(last visited June 19, 2021); see also I. Jeong
`and-analysis-challenges-with-co-optimization-across-process-steps/ (last visited June 19, 2021); see also I. Jeong
`et al., “Scanner and etch co-optimized corrections for better overlay and CD control” (“Scanner and Etch
`et al., “Scanner and etch co-optimized corrections for better overlay and CD control” (“Scanner and Etch
`Optimized Corrections”) (March 20, 2019), available at https://www.spiedigitallibrary.org/conference-
`Optimized Corrections”) (March 20, 2019), available at https://www.spiedigitallibrary.org/conference-
`proceedings-of-spie/10963/1096308/Scanner-and-etch-co-optimized-corrections-for-better-overlay-
`proceedings-of-spie/10963/1096308/Scanner-and-etch-co-optimized-corrections-for-better-overlay-
`and/10.1117/12.2516578.short (last visited June 19, 2021) (showing “scannerandetch corrections in one
`and/10.1117/12.2516578.short (last visited June 19, 2021) (showing “scanner and etch corrections in one
`control”):
`control”):
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 29 of 118
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`As a further example, the’651 Infringing Instrumentalities also include a chamber for deposition of pin-on-glass,
`anti-reflective coating and photoresist, as shown below:
`
`“Patterning was achieved by depositing 100nm SOC, 30nm spin-on-glass (SOG), 29nm Anti-Reflective Coating
`(ARC), and 105nm photoresist (PR) in an ASML Twinscan NXT:1950i 193nm immersion scanner, followed by
`lithographic patterning of line/space patterns.”
`
`See J. Soethoudt et al., “Defect mitigation in area-selective atomic layer deposition of ruthenium on titanium
`nitride/dielectric nanopatterns” (“Atomic Layer Deposition”) at 8, available at
`https://lirias.kuleuven.be/2844955?limo=0 (last visited June 19, 2021).
`
`The ’651 Infringing Instrumentalities position a wafer on the wafer stage after the wafer stage has been adjusted.
`
`For example, the TWINSCAN system positions the wafer on the exposure table of the dual-wafer stage after the
`
`27
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`21. The method of
`claim 19, wherein
`
`
`
`

`

`positioning a wafer on
`said wafer stage
`comprises positioning a
`wafer on said wafer
`stage after said wafer
`stage has been adjusted.
`
`22. The method of
`claim 19, wherein
`positioning a wafer on
`said wafer stage
`comprises positioning a
`wafer on said wafer
`stage before said wafer
`stage has been adjusted.
`
`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 30 of 118
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`exposure of a previous wafer is done and the exposure table is adjusted to receive a new wafer for the next cycle
`of exposure.
`
`See, e.g., P. Drabik, “Performance prediction for Stage Positioning Measurement (SPM),” Master’s Thesis,
`Eindhoven University of Technology, Department of Mathematics and Computer Science, available at
`https://pure.tue.nl/ws/files/72326295/Master_Thesis_Pawel_Drabik_Public.pdf (“Stage Positioning
`Management”) at 1-2:
`
`“These systems are designed as wafer scanners which Performance prediction for Stage Positioning Measurement
`(SPM) 1 CHAPTER 1. INTRODUCTION perform the exposure process in step and scan fashion as presented in
`Figure 1.1. The reticle with circuit pattern is placed on a reticle stage (RS), whereas the silicon wafer is placed on
`a wafer stage (WS). During the scan movement the light is switched on with a desired dose and the exposure
`process starts. The stages move according to each other performing synchronized zig-zag movements. Next during
`the step movement the light is switched off, the reticle goes back to its initial position and the silicon wafer is
`prepared for exposure of a next die. The process repeats itself until all of the dies have been processed. Next, the
`reticle mask is replaced with a new one and the process can start all over again, exposing a new layer on top of the
`previous one. The exposure of consecutive layers needs to be done with nanometer precision in order to deliver
`highest quality circuits.”
`
`Also, the exposure table is re-adjusted from the previous exposure before receiving the next wafer.
`
`The ’651 Infringing Instrumentalities position a wafer on the wafer stage after said wafer stage has been adjusted.
`
`For example, the TWINSCAN system positions the wafer on the measurement table of the dual-wafer stage before
`the stage position of the measurement table is adjusted:
`
`“While the first stage exposes the wafer, the second stage unloads the previous wafer from the tool, loads a new
`wafer on the stage, aligns the horizontal placement of the wafer on the stage, and measures the wafer height map
`used to focus the wafer during exposure. When both stages are finished with their tasks, the stages are swapped
`and a new cycle begins. In this way, the number of wafers that is processed is enlarged by removing overhead time
`from the expose cycle. T.”
`
`See Position Control at 35.
`
`See also Stage Positioning Management at 3:
`
`
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 31 of 118
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`23. The method of
`claim 19, wherein
`performing a proces
`operation on said wafer
`comprises performing at
`least one of a deposition
`process and an etching
`proces in said process
`chamber.
`
`
`24. The method of
`claim 19, wherein
`adjusting said surface of
`said wafer stage
`
`
`
`The ’651 Infringing Instrumentalities perform a proces operation on the wafer comprises performing at least one
`of a deposition process and an etching process in the process chamber.
`
`See Claim 20.
`
`
`
`The ’651 Infringing Instrumentalities adjust the surface of the wafer stage by actuating at least one of three
`pneumatic cylinders, each of which are operatively coupled to the wafer stage by a ball and socket connection.
`
`For example, each of the at least three pneumatic cylinders of the TWINSCAN system are operatively coupled to
`
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`Case 6:20-cv-01216-ADA Document 41-24 Filed 10/06/21 Page 32 of 118
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`the wafer stage vi