Case 6:20-cv-01216-ADA Document 41-23 Filed 10/06/21 Page 1 of 12
`Case 6:20-cv-01216-ADA Document 41-23 Filed 10/06/21 Page 1 of 12
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`EXHIBIT 23
`EXHIBIT 23
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`Analysis of Infringement of U.S. Patent No. 6,660,651 by Western Digital Corporation
`(Based on Public Information Only)
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`Plaintiff Ocean Semiconductor LLC (“Ocean Semiconductor”), provides this preliminary and exemplary infringement analysis with respect to
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`infringement of U.S. Patent No. 6,660,651, entitled “ADJUSTABLE WAFER STAGE, AND A METHOD AND SYSTEM FOR PERFORMING
`PROCESS OPERATIONS USING SAME” (the “’651 patent”) by Western Digital Corporation (“WD”). The following chart illustrates an
`exemplary analysis regarding infringement by Defendant WD’s semiconductor products, systems, devices, components, integrated circuits, and
`products containing such circuits, fabricated or manufactured using ASML’s semiconductor fabrication or manufacturing equipment and/or platforms
`(e.g., ASML’s TWINSCAN system). Such products include, without limitation, automotive products (e.g., iNAND® AT EU312, iNAND® AT
`EM122, iNAND® AT EM132, Automotive AT LD332, AT 132 (e.g., grades 2 and 3), AT 122 (e.g., grades 2 and 3), Industrial Wide Temp IX
`QD332, Industrial Ext Temp IX QD332, Industrial Ext Temp IX QD334, Industrial Wide Temp IX QD342, Commercial CL SN720, Commercial CL
`SN520), connected home products (e.g., iNAND® CH EM123/133, CH LD313, CH LD513, CH QD313, CH QD513, CH XB 513, CH XB 313, WD
`AV-25, WD AV-GP 1000, CL SN720, CL SN520, PC SA530), industrial and IoT products (e.g., iNAND® IX EM132, iNAND® IX EM122,
`iNAND® IX EU312, Industrial IX LD342, Industrial IX LD332, Industrial IX QD342, Industrial IX QD332, Industrial IX QD334, Commercial CL
`SN720, Commercial CL SN520, Commercial PC SN730, Commercial X600, Commercial PC SA530), mobile products (e.g., MC EU521, MC
`EU511, MC EU311d, MC EM131/c, MC EM121/b, MC EM111/a, Commercial CL QD501, Commercial CL QD301, Commercial CL QD101), and
`surveillance products (e.g. CL EM132/122, IX EM122 Wide Temp, IX EM122 Extended Temp, WD PurpleTM SC QD101 Ultra Endurance
`microSDTM Card), flash memory (e.g., 3D flash and NAND flash), RISC-V SweRVCore Family (e.g., EH1 and EH2), and similar systems,
`products, devices, and integrated circuits (“’651 Infringing Instrumentalities”).
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`The analysis set forth below is based only upon information from publicly available resources regarding the ’651 Infringing Instrumentalities,
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`as WD has not yet provided any non-public information.
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`Unless otherwise noted, Ocean Semiconductor contends that WD directly infringes the ’651 patent in violation of 35 U.S.C. § 271(g) by
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`using, selling, and/or offering to sell in the United States, and/or importing into the United States, the ’651 Infringing Instrumentalities. The
`following exemplary analysis demonstrates that infringement. Unless otherwise noted, Ocean Semiconductor further contends that the evidence
`below supports a finding of indirect infringement under 35 U.S.C. § 271(b) in conjunction with other evidence of liability.
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`Unless otherwise noted, Ocean Semiconductor believes and contends that each element of each claim asserted herein is literally met through
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`WD’s provision or importation of the ’651 Infringing Instrumentalities. However, to the extent that WD attempts to allege that any asserted claim
`element is not literally met, Ocean Semiconductor believes and contends that such elements are met under the doctrine of equivalents. More
`specifically, in its investigation and analysis of the ’651 Infringing Instrumentalities, Ocean Semiconductor did not identify any substantial
`differences between the elements of the patent claims and the corresponding features of the ’651 Infringing Instrumentalities, as set forth herein. In
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`each instance, the identified feature of the ’651 Infringing Instrumentalities performs at least substantially the same function in substantially the same
`way to achieve substantially the same result as the corresponding claim element.
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`Ocean Semiconductor notes that the present claim chart and analysis are necessarily preliminary in that Ocean Semiconductor has not
`obtained substantial discovery from WD nor has WD disclosed any detailed analysis for its non-infringement position, if any. Further, Ocean
`Semiconductor does not have the benefit of claim construction or expert discovery. Ocean Semiconductor reserves the right to supplement and/or
`amend the positions taken in this preliminary and exemplary infringement analysis, including with respect to literal infringement and infringement
`under the doctrine of equivalents, if and when warranted by further information obtained by Ocean Semiconductor, including but not limited to
`information adduced through information exchanges between the parties, fact discovery, claim construction, expert discovery, and/or further analysis.
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`Infringement by the ’651 Accused Instrumentalities
`ASML’s TWINSCAN system provides a process chamber comprised of a wafer stage, the wafer stage having a
`surface that is adjustable.
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`For example, the TWINSCAN system performs the method of providing a process chamber:
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`USP No. 6,660,651
`19. A method,
`comprising: providing a
`process chamber
`comprised of a wafer
`stage, said wafer stage
`having a surface that is
`adjustable;
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`See ASML DUV Lithography Systems, available at https://www.asml.com/en/products/duv-lithography-
`systems/twinscan-nxt1980di (last visited Apr. 30 2019).
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`The process chamber can be used for wafer exposure during lithography:
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`See Perspective on Stage Dynamics and Control at 3.
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`The process chamber includes an adjustable wafer stage having a surface that is adjustable:
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`“In Figure 4, the table holding the wafer is called the mirror block because of the mirroring side surfaces, which
`allow interferometric position measurement (IFM).”
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`See Position Control at 31.
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`For example, the adjustable wafer stage or mirror block of the TWINSCAN system is shown below:
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`See Applications Products and Business Opportunity at 6.
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`ASML’s TWINSCAN system adjusts the surface of the wafer stage by actuating at least one of a plurality of
`pneumatic cylinders that are operatively coupled to said wafer stage to accomplish at least one of raising, lowering
`and varying a tilt of said surface of said wafer stage.
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`For example, the TWINSCAN system adjusts the surface of the wafer stage by raising, lower, or tilting via wafer
`leveling using vertical actuators (e.g., in the “z direction”):
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`“Vertical actuators, which are mounted between the air foot and mirror block, allow the mirror block to be moved
`in z direction, as well as in rotational directions around the x and y axes, called x and Ψ, respectively.”
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`See Position Control at 41; see also id. at 38 (“For wafer leveling, the actuators drive the mirror block with respect
`to the air foot, and hence vertical reaction forces can directly enter the silent, vibration-free, metro-frame world.
`Leveling now needs to be performed during scanning, making use of the wafer-height measurement by the level
`sensor.”).
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`As another example, the TWINSCAN system actuates one of the six Lorentz actuators that are mounted between
`the air foot and the wafer stage to accomplish at least one of raising, lowering and varying a tilt of the surface of
`the wafer stage:
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`adjusting said surface of
`said wafer stage by
`actuating at least one of
`a plurality of pneumatic
`cylinders that are
`operatively coupled to
`said wafer stage to
`accomplish at least one
`of raising, lowering and
`varying a tilt of said
`surface of said wafer
`stage;
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`“Vertical actuators, which are mounted between the air foot and mirror block, allow the mirror block to be moved
`in z direction, as well as in rotational directions around the x and y axes, called x and Ψ, respectively.”
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`See Position Control at 41.
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`Generally, the wafer stage is equipped with DOF Lorentz actuators (e.g., three DOF actuators for the horizontal
`directions and three DOF actuators for the vertical directions):
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`“The table also had vertical movement directions for the purpose of focusing the wafer in the image plane of the
`lens, requiring a measurement of the distance of the wafer to the lens by means of a level sensor system. The
`horizontal stage position was measured by an interferometer system. The stage was guided by means of
`mechanical bearings ‘rolling’ over the motor beams. With regard to controlling the stage, the horizontal
`controllers (3-DOF) acted independently from the vertical directions (also 3-DOF).”
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`See Perspective on Stage Dynamics and Control at 1.
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`As an example, for the x and y direction, the wafer table is adjusted by three Lorentz actuators such that the stage
`floats over a granite stone by means of an air bearing and the Lorentz actuators are connected to this granite stone:
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`See Position Control at 31.
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`In total, the TWINSCAN includes 6-DOF Lorentz actuators and 6-DOF stage control, in addition to offline
`leveling:
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`“In TWINSCANTM, a further perfection in the basic design was made by using balance masses, full 6-DOF
`Lorentz actuators and 6-DOF stage control, in addition to off-line levelling.”
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`See Perspective on Stage Dynamics and Control at 3.
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`As another example, the vertical directions of the wafer stage can be achieved using Lorentz actuators:
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`“To avoid vibrations entering the mirror block, a Lorentz actuator is now also used for vertical directions, providing
`isolation in these directions as well. Because the required vertical range is smaller than 1 mm, no separate long-stroke
`motor is required. A 6DOF Lorentz-actuated block is the result”
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`See Position Control at 40.
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` A
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` diagram showing the vertical connection that facilitates the vertical movement of the wafer stage is shown below:
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`See Position Control at 41 (annotated).
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`In one example, the wafer stage rotates around the center of the lens above it in the vertical directions using the
`actuators:
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`“The stage now rotates around the lens center instead of its center of mass. Especially in the vertical directions, the
`applicable rotations may show a high acceleration, depending on the vertical topology of the wafer surface.”
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`See Position Control at 42.
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`The wafer stage can also be tilted to help keep the wafer in focus:
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`“The reason for this lies in the scanning levelling: when the stage has to tilt around a horizontal axis to keep the wafer
`in focus, the stage tends to rotate around its center of mass, introducing a horizontal shift on wafer level.”
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`See Perspective on Stage Dynamics and Control at 2.
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`ASML’s TWINSCAN system positions a wafer on the wafer stage.
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`For example, the TWINSCAN system positions the wafer on the wafer stage:
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`“After stepping the wafer to a new position, the wafer stage is allowed to wait until its position has settled such
`that the remaining error is sufficiently low before switching on the illuminating light. The MA and MSD after the
`step motion indicate the usability of the system for imaging.”
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`See Position Control at 35.
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`The wafer is also loaded onto the wafer stage so that exposure can start:
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`“At the second stage, the wafer is loaded, and its surface is mapped in horizontal and vertical planes with respect
`to the stage itself. After the stage swap, the stage that is now positioned under the projection lens is aligned to the
`reticle in 6DOF by means of a through-the-lens optical system. With the wafer surface position known with
`respect to the stage and the stage position known with respect to the reticle, exposure can start.”
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`See Position Control at 40.
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`ASML’s TWINSCAN system performs a process operation on the wafer position on the wafer stage.
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`For example, the TWINSCAN system performs stepper imaging or double patterning as part of the step-and-scan
`in exposing a wafer:
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`“After stepping the wafer to a new position, the wafer stage is allowed to wait until its position has settled such
`that the remaining error is sufficiently low before switching on the illuminating light. The MA and MSD after the
`step motion indicate the usability of the system for imaging.”
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`See Position Control at 35.
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`positioning a wafer on
`said wafer stage; and
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`performing a process
`operation on said wafer
`positioned on said wafer
`stage.
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`Once the wafer is loaded, and its surface is mapped in horizontal and vertical planes with respect to the stage itself,
`the stage positioned under the projection lens is aligned to the reticle by means of a through-the-lens optical system.
`With the wafer surface position known with respect to the stage and the stage position known with respect to the
`reticle, exposure can start:
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`“Stage position measurement is now performed in all degrees of freedom by interferometers, with reference beams
`directed at the projection lens. This method provides a direct relative measurement of the position with respect to
`the lens. At the second stage, the wafer is loaded, and its surface is mapped in horizontal and vertical planes with
`respect to the stage itself. After the stage swap, the stage that is now positioned under the projection lens is aligned
`to the reticle in 6DOF by means of a through-the-lens optical system. With the wafer surface position known with
`respect to the stage and the stage position known with respect to the reticle, exposure can start.”
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`See Position Control at 40.
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