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`Case 6:20-cv-01216-ADA Document 41-12 Filed 10/06/21 Page 1 of 14
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`EXHIBIT 12
`EXHIBIT 12
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`Case 6:20-cv-01216-ADA Document 41-12 Filed 10/06/21 Page 2 of 14
`ee—”— STATEEAT
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`US006762133B1
`
`US 6,762,133 B1
`(10) Patent No:
`a2) United States Patent
`Rangarajan et al.
`(45) Date of Patent:
`Jul. 13, 2004
`
`
`(54) SYSTEM AND METHOD FOR CONTROL OF
`HARDMASK ETCH TO PREVENT PATTERN
`COLLAPSE OF ULTRA-THIN RESISTS
`
`(75)
`
`Inventors: Bharath Rangarajan, Santa Clara, CA
`(US); Ramkumar Subramanian, San
`Jose, CA (US); Khoi A. Phan, San
`Jose, CA (US)
`
`(73) Assignee: Advanced Micro Devices, Inc.,
`Sunnyvale, CA (US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`US.C. 154(b) by 302 days.
`
`(21) Appl. No.: 09/911,241
`2)
`Filed:
`1. 23. 2001
`(22)
`File
`Ju
`,
`(SL) Ute C0 eee ecececsesscsseeseeseeseeneeneeneens HO1L 4/302
`.... 438/745; 134/1.1; 430/313
`(52)
`
`(58) Field of Search oo... cece 438/745, 751,
`438/756, 757; 134/1.1, 1.2, 1.3; 430/313-315
`
`(56)
`
`References Cited
`
`*
`
`U.S. PATENT DOCUMENTS
`5,670,423 A
`9/1997 YOO viecsesseessssensereeeeees 437/192
`5,741,628 A *
`4/1998 Matsuo etal. occ. 430/323
`5,756,254 A *
`5/1998 Kihara et al.
`............ 430/270.1
`5,866,304 A *
`2/1999 Nakano et al... 430/325
`6,020,269 A
`2/2000 Wang etal... 438/717
`6,605,413 B1 *
`8/2003 Lyonsetal. 0.0.0... 430/314
`cited b
`.
`cme
`OY CXGEEINST
`Primary Examiner—Kin-Chan Chen
`(74) Attorney, Agent, or Firm—Amin & Turocy, LLP
`(57)
`ABSTRACT
`The present invention relates to systems and methods for
`mitigating pattern collapse in ultra-thin resist processing. In
`one embodiment, the present invention relates to etching
`extremely fine patterns into a hardmask immediately after
`developing an ultra-thin resist, wherein the resist
`is not
`dried.
`
`11 Claims, 5 Drawing Sheets
`
`yr'8
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`y'8
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`U.S. Patent
`
`Jul. 13, 2004
`
`Sheet 1 of 5
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`US 6,762,133 B1
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`FIG. 1
`
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`

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`U.S. Patent
`
`Jul. 13, 2004
`
`Sheet 2 of 5
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`US 6,762,133 B1
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`FIG. 3
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`U.S. Patent
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`Jul. 13, 2004
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`Sheet 3 of 5
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`US 6,762,133 B1
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`Case 6:20-cv-01216-ADA Document 41-12 Filed 10/06/21 Page 6 of 14
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`U.S. Patent
`
`Jul. 13, 2004
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`Sheet 4 of 5
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`US 6,762,133 B1
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`
`
`MEASUREMENT
`SYSTEM
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`
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`Ld
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`PROCESS
`
`CONTROL
`
`
`SYSTEM
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`32
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`38
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`34
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` PROCESS
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`CONDITION
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`SENSOR(S)
`
`FIG. 7
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`U.S. Patent
`
`Jul. 13, 2004
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`Sheet 5 of 5
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`US 6,762,133 B1
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`ONISNAdSIO
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`WALSAS
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`82
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`09
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`YAHLO
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`SYOSNAS
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`AlddNsS¥aMOd
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`08
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`AW1dSIG
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`OLWALSASTOMLNOOD
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`LNAWSYNSVAW
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`WALSAS
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`US 6,762,133 B1
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`1
`SYSTEM AND METHOD FOR CONTROL OF
`HARDMASK ETCH TO PREVENT PATTERN
`COLLAPSE OF ULTRA-THIN RESISTS
`
`2
`during deionized water rinsing. Improved lithography pro-
`cedures providing improved resolution and improvedresis-
`tance to pattern collapse are therefore desired.
`
`TECHNICAL FIELD
`
`invention generally relates to mitigating
`The present
`pattern collapse of ultra-thin resists. In particular, the present
`invention relates to an etch of a hardmask immediately after
`developing an ultra-thin resist, and control thereof.
`BACKGROUNDART
`
`In the semiconductor industry, there is a continuing trend
`toward higher device densities. To achieve these high
`densities, there has been and continues to be efforts toward
`scaling down the device dimensions on semiconductor
`wafers. In order to accomplish such high device packing
`density, smaller and smaller features sizes are required. This
`includes the width and spacing of interconnecting lines and
`the surface geometry such as corners and edges of various
`features. Since numerousinterconnecting lines are typically
`present on a semiconductor wafer, the trend toward higher
`device densities is a notable concern.
`
`SUMMARYOF THE INVENTION
`
`The present invention generally provides systems and
`methods that mitigate the problems associated with pattern
`collapse, improvecritical dimension control and/or improve
`resolution when using ultra-thin resists. Since it is possible
`to mitigate the problems associated with ultra-thin photore-
`sist pattern collapse,
`the present
`invention provides
`improved methods for processing layers underneath ultra-
`thin photoresists including metal layers, dielectric layers,
`and silicon layers. The methods of the present invention
`make it possible to consistently process underlying layers
`through trenches, holes and other openings on the order of
`about 0.18 4m or less in size. As a result,
`the present
`invention effectively addresses the concerns raised by the
`trend towards the miniaturization of semiconductor devices.
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`the present invention relates to a
`In one embodiment,
`semiconductor processing system containing a processing
`chamber coupled to a measurement system and a control
`system and operable to develop an ultra-thin resist and etch
`a hardmask; a supply of a developer for contact with the
`The requirement of small features, such as metal lines,
`ultra-thin resist; a supply of an etch solution; the measure-
`with close spacing between adjacent features requires high
`ment system for in situ monitoring of patterning the ultra-
`resolution photolithographic processes. In general, lithogra-
`thin resist and the hardmask and for providing a measure-
`phyrefers to processes for pattern transfer between various
`ment signal indicative of the measured patterning; and the
`media. It is a technique used for integrated circuit fabrication
`30
`control system for controlling treatment parameters within
`in whichasiliconslice, the wafer, is coated uniformly with
`the chamberincluding contact time of the etch solution with
`a radiation-sensitive film, the resist, and an exposing source
`the patterned resist and hardmask. The control system
`(such as optical light, X-rays, or an electron beam) illumi-
`adjusts the treatment parameters to control patterning based
`nates selected areas of the surface through an intervening
`on the measurement signal.
`master template, the photomask,for a particular pattern. The
`lithographic coating is generally a radiation-sensitized coat-
`In another embodiment, the present invention relates to a
`ing suitable for receiving a projected image of the subject
`method of processing an ultra-thin resist, involving depos-
`pattern. Once the image is projected,it is indelibly formed
`iting the ultra-thin resist over a hardmask layer that is over
`in the coating. The projected image maybeeither a negative
`a semiconductor substrate; irradiating the ultra-thin resist;
`or a positive of the subject pattern. Exposure of the coating
`developing the ultra-thin resist with a developer to form a
`through the photomask causes a chemical transformation in
`patterned resist, wherein the ultra-thin resist is not dried;
`the exposed areas of the coating thereby making the image
`optionally rinsing the patterned resist with water, and etch-
`area either more or less soluble (depending on the coating)
`ing the hardmask layer with an etch solution within about 1
`in a particular solvent developer. The more soluble areas are
`minute after developing to provide a patterned hardmask.
`removed in the developing process to leave the pattern
`The method may further include controlling treatment
`image in the coating as less soluble polymer.
`parameters using a control system and a measurement
`system.
`Projection lithography is a powerful and essential tool for
`microelectronics processing. However, lithography is not
`without limitations. Patterning features having dimensions
`of about 0.25 um, 0.18 um or less with acceptable resolution
`is difficult. This is because photoresist layers used in lithog-
`raphy typically have thicknesses on the order of 7,000 Aand
`higher. Such relatively thick photoresist layers are not con-
`ducive to making small patterned dimensions with good
`resolution.
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`Using relatively thin photoresists (such as less than about
`5,000 A) enables the patterning of smaller and smaller
`dimensions. However, insufficient resistance to pattern col-
`lapse during post-developmentrinse and dry cycles is asso-
`ciated with using thin photoresists. Insufficient resistance to
`pattern collapse is also associated with smaller and smaller
`pitches (of patterned photoresists). The relatively thin pat-
`terned photoresists simply do not withstand the physical
`strain imposed bythe post-developmentrinse and dry steps.
`For example, pattern collapse due to water rinse, dry cycles,
`and spinning action associated with such steps, result in poor
`pattern transfer. In many instances the relatively thin pat-
`terned photoresists are destroyed or partially destroyed
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`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1 illustrates a cross-sectional view of a semiconduc-
`tor structure processed accordingto one aspect of the present
`invention.
`FIG. 2 illustrates a cross-sectional view of a semiconduc-
`tor structure processed accordingto one aspect of the present
`invention.
`FIG. 3 illustrates a cross-sectional view of a semiconduc-
`tor structure processed according to another aspect of the
`present invention.
`FIG. 4 illustrates a cross-sectional view of a semiconduc-
`tor structure processed according to another aspect of the
`present invention.
`FIG. 5 illustrates a cross-sectional view of a semiconduc-
`tor structure processed according to yet another aspect of the
`present invention.
`FIG. 6 illustrates a cross-sectional view of a semiconduc-
`tor structure processed according to yet another aspect of the
`present invention.
`
`

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`US 6,762,133 B1
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`3
`FIG. 7 is a diagramatic block representation of a system
`in accordance with one aspect of the present invention.
`FIG. 8 is a functional block diagram of a a system in
`accordance with another aspect of the present invention.
`DISCLOSURE OF THE INVENTION
`
`The present invention involves systems and methods for
`etching extremely fine patterns into a hard mask while
`developing an ultra-thin resist
`to mitigate problems of
`pattern collapse. The present invention more specifically
`involves developing an irradiated ultra-thin resist and wet
`etching the underlying hardmask layer in the same step to
`enable high resolution patterning of the underlying hard-
`mask layer having features on the order of about 0.18 um or
`less, and even about 0.13 wm orless. Since the hardmask is
`patterned at substantially the same timethe ultra-thin resist
`is developed (that is, immediately thereafter), drying and
`rinsing the ultra-thin resist are not necessary, and thus the
`problems associated with drying and rinsing an ultra-thin
`resist, such as pattern collapse, are eliminated. In subsequent
`processing, the hardmask is much more durable as a mask
`than the ultra-thin resist. The present invention therefore
`promotes advancement in the trend toward higher device
`densities.
`
`As a result of the present invention, pattern collapse of
`ultra-thin resists due to at least one of water rinse, drying,
`and torsional spinning forces is improved. Mitigating and/or
`eliminating the problems associated with pattern collapse
`permits the more frequent use of ultra-thin resists in pro-
`cessing underlying layers with preciseness. Resolution and
`critical dimension control are also improved by the use of
`ultra-thin resists.
`
`A hardmask is initially provided over a semiconductor
`substrate to be processed using an ultra-thin resist. The
`semiconductor substrate may include any suitable semicon-
`ductor material
`(one or more layers of semiconductor
`materials), for example, a monocrystalline silicon substrate.
`Semiconductor substrates may include of one or more layers
`including substrate layers, diffusion regions, dielectric lay-
`ers such as oxides and nitrides, metal
`layers, devices,
`polysilicon layers, and the like (all of which are collectively
`termed semiconductor layers), which may further include
`various electrical devices. The top layer of the semiconduc-
`tor substrate serves as the underlying layer once the hard-
`mask and an ultra-thin resist layer is formed thereover.
`The hardmask is composed of a material that may be
`etched with a solution inside the developer cup. Examples of
`hardmask materials include oxides, nitrides, and metal con-
`taining materials. Oxide hardmasksinclude silicon dioxide,
`fluorine doped silicon glass (FSG), tetraethylorthosilicate
`(TEOS), phosphosilicate glass (PSG), borophosphosilicate
`glass (BPSG), borophosphotetraethylorthosilicate
`(BPTEOS), and the like. Nitride hardmasks includesilicon
`nitride and silicon oxynitride. Metal containing materials
`include titanium, titanium nitride, tungsten, tantalum, tan-
`talum nitride.
`
`Hardmasks in accordance with the present invention have
`a thickness of about 5,000 A or less. The hardmask is
`suitably thin to act as a mask for patterning small features.
`In one embodiment, the hardmask has a thickness of about
`100 A or more and about 5,000 A or less. In another
`embodiment, the hardmask has a thickness of about 200 A
`or more and about 3,000 A or
`less.
`In yet another
`embodiment, the hardmask has a thickness of about 300 A
`or more and about 2,000 A orless.
`An ultra-thin resist is provided over the hardmask. The
`ultra-thin resist is deposited over the semiconductor sub-
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`strate using any suitable technique. For example, an ultra-
`thin photoresist is deposited using conventional spin-coating
`or spin casting techniques.
`Ultra-thin resists in accordance with the present invention
`have a thickness of about 5,000 A or
`less.
`In one
`embodiment, the ultra-thin resist layer has a thickness of
`about 200 A or more and about 5,000 A orless. In another
`embodiment, the ultra-thin resist layer has a thickness of
`about 300 A or more and about 3,000 A orless. In yet
`another embodiment, the ultra-thin resist layer has a thick-
`ness of about 400 A or more and about 2,500 A orless.
`The ultra-thin resist layer has a thickness suitable for
`forming patterns or openings in the hardmaskthat are about
`0.18 um orless, or even about 0.15 um or less. As a result,
`processing the layer under the hardmaskis facilitated by the
`ability to fabricate small features. Processing the underlying
`layer includes one or more of etching,
`implantation,
`deposition, or other operations. Since the ultra-thin resist
`layer is relatively thin compared with I-line photoresists and
`other photoresists, improved critical dimension control is
`realized.
`
`Ultra-thin resists are typically processed using small
`wavelength radiation. As used herein, small wavelength
`radiation means electromagnetic radiation having a wave-
`length of about 250 nm orless, including e-beams and
`X-rays. In one embodiment, small wavelength radiation
`includes electromagnetic radiation having a wavelength of
`about 200 nm orless. In another embodiment, small wave-
`length radiation includes extreme UV electromagnetic radia-
`tion having a wavelength of about 160 nm orless. In yet
`another embodiment, small wavelength radiation includes
`extreme UVelectromagnetic radiation having a wavelength
`of about 15 nm orless, including e-beams and X-rays.
`Small wavelength radiation increases precision and thus
`the ability to improve critical dimension control and/or
`resolution. Specific examples of wavelengths to which the
`ultra-thin resists are sensitive (undergo chemical transfor-
`mation enabling subsequent development) include about
`248 nm, about 193 nm, about 157 nm, about 13 nm, about
`11 nm, about 1 nm, and e-beams. Specific sources of
`radiation include KrF excimerlasers having a wavelength of
`about 248 nm, a XeHg vapor lamp having a wavelength
`from about 200 nm to about 250 nm, mercury-xenon arc
`lampshaving a wavelength of about 248 nm, an ArF excimer
`laser having a wavelength of about 193 nm, an F, excimer
`laser having a wavelength of about 157 nm, extreme UV
`light having wavelengths of about 13.5 nm and/or about 11.4
`nm, and X-rays having a wavelength of about 1 nm.
`Positive or negative ultra-thin photoresists may be
`employed in the methods of the present invention. General
`examples of ultra-thin resists include those containing a
`partially t-butoxycarbonyloxy substituted poly-p-
`phydroxystyrene, melamine-formaldehyde polymers,
`polyvinylpyrrolidone, polymethylisoprenylketone,
`a
`novolak, a polyvinylphenol, polymers of hydroxystyrene
`and acrylate, methacrylate polymers or a mixture of acrylate
`polymers and methacrylate polymers. Further specific
`examples include poly(p-tert-butoxycarbonyloxy-a-
`methylstyrene), poly(p-tert-butoxycarbonyloxystyrene),
`poly(tert-butyl p-vinylbenzoate), poly(tert-butyl
`p-isopropenylphenyloxyacetate), and poly(tert-butyl
`methacrylate). Resists are commercially available from a
`number of sources,
`including Shipley Company, Kodak,
`Hunt, Arch Chemical, Clariant, Aquamer, JSR
`Microelectronics, Hoechst Celanese Corporation, and
`Brewer.
`
`

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`US 6,762,133 B1
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`5
`After the ultra-thin resist is deposited over the hardmask,
`the structure including the semiconductor substrate,
`hardmask, and ultra-thin resist is optionally heated. Heating
`serves to promote removal of excess solvent employed to
`deposit the ultra-thin resist over the hardmask.
`The ultra-thin resist layer is then selectively exposed to
`actinic radiation. In particular, the ultra-thin resist layer is
`exposed to a pattern of radiation having a relatively small
`wavelength (for example,less than 250 nm); thatis, selected
`portions of the ultra-thin resist layer are exposed to actinic
`radiation through a mask, leaving the ultra-thin resist layer
`with exposed and unexposed portions. Actinic radiation
`includesrelatively small wavelength less than 250 nm and
`e-beams. A numberof exemplary wavelengths are described
`above in connection with the ultra-thin resists.
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`invention, a patterned mask with fine features,
`present
`including a small pitch, can be readily formed.
`The present invention is now discussed in conjunction
`with the Figures. FIGS. 1-6 illustrate various embodiments
`of the present invention. The procedures described in the
`Figures may be used with any suitable semiconductor tech-
`nology including but not limited to NMOS, PMOS, CMOS,
`BICMOS,bipolar, multi-chip modules (MCM) and TI-IV
`semiconductors.
`
`In one embodiment, referring to FIG. 1, a semiconductor
`structure 10 including a semiconductor substrate 12 having
`a hardmask layer 14 thereover is provided. Semiconductor
`substrate 12 may include any suitable semiconductor mate-
`rial (one or more layers of semiconductor materials), for
`example, a monocrystalline silicon substrate. Semiconduc-
`tor substrate 12 may additionally include of one or more
`layers including substrate layers, diffusion regions, dielec-
`tric layers such as oxides and nitrides, devices, polysilicon
`layers, and the like. The hardmask layer 14 is silicon dioxide
`and has a thickness of about 1,000 A or
`less in this
`embodiment.
`
`Following an image-wise exposure to actinic radiation,
`the ultra-thin resist layer is developed and the hardmask is
`immediately etched to provide a patterned hardmask without
`rinsing, spinning, and drying the ultra-thin resist, thereby
`mitigating the problems associated with pattern collapse. In
`other words, the ultra-thin resist layer is developed and the
`hardmask is etched without drying the ultra-thin resist
`An ultra-thin photoresist layer 16 is then formed over the
`Immediately etching the hardmask meansthat the hardmash
`hardmask layer 14. The ultra-thin photoresist is deposited
`is etched with an etching solution within about 1 minute
`over the hardmask layer 14 using any suitable technique,
`after the ultra-thin resist
`layer is developed. In another
`such as conventional spin-coating or spin casting tech-
`embodiment, immediately etching the hardmask meansthat
`niques. The ultra-thin photoresist layer 16 also has a thick-
`the hardmashis etched with an etching solution within about
`ness of about 1,000 A orless. Sincethe ultra-thin photoresist
`30 secondsafter the ultra-thin resist layer is developed.
`layer 16 is relatively thin compared with I-line and other
`The ultra-thin resist layer may be optionally rinsed, for
`photoresists, improved resolution over I-line photoresists is
`example with deionized water, immediately after develop-
`realized. In this embodiment, the ultra-thin photoresist layer
`mentand just prior to etching the hardmask. However,if the
`16 is a positive type deep UV photoresist.
`ultra-thin resist layer is optionally rinsed, it is not dried. In
`The ultra-thin photoresist layer 16 of the semiconductor
`a preferred embodiment, a liquid (developer, optionalrinse,
`structure 10 is then selectively exposed to actinic radiation
`and etching solution)is in constant contact with the structure
`(shown by the arrows) through a lithography mask (not
`in a continuous, successive manner.
`shown). The ultra-thin photoresist layer 16 is selectively
`The selectively exposed ultra-thin resist layer is devel-
`exposed using electromagnetic radiation havingarelatively
`oped by contact with a suitable developer that removes
`small wavelength (for example, less than 250 nm). In this
`either the exposed or unexposed portions of the ultra-thin
`embodiment, electromagnetic radiation having a wavelength
`resist layer. The identity of the developer depends upon the
`of about 248 nm is employed. The ultra-thin photoresist
`specific chemical constitution of the ultra-thin resist layer.
`layer 16 is selectively exposed to radiation; that is, selected
`Typically, for example, an aqueous alkaline solution may be
`portions of the ultra-thin photoresist layer 16 are exposed to
`employed to remove unexposed portions of the ultra-thin
`radiation (corresponding to the regions directly underneath
`resist layer. Alternatively, one or more of dilute aqueousacid
`the openings in the lithography mask) while other portions
`solutions, hydroxide solutions, water, organic solvent solu-
`of the ultra-thin photoresist
`layer 16 are not exposed
`tions may be employed to remove selected portions of the
`(corresponding to the regions directly underneaththe lithog-
`ultra-thin resist layer.
`raphy mask).
`After contact with the developer, the structure or treated
`Referring to FIG. 2, the ultra-thin photoresist layer 16 of
`patterned resist
`is immediately subjected to an etching
`the semiconductor structure 10 is developed by contact with
`solution to remove portions of the hardmask exposed by
`a suitable developer that removes the exposed portions of
`development. As a result, the patterned ultra-thin resist is
`the ultra-thin photoresist layer 16 thereby exposing a portion
`removed and portions of the hardmaskis patterned.
`of the hardmask layer 14 and temporarily providing a
`patterned ultra-thin photoresist layer. In this embodiment, an
`The composition of the etching solution depends upon the
`aqueous tetrainethylamrnmonium hydroxide solution may
`identity of the hardmask material. As previously described,
`the hardmask materials include oxides, nitrides, and metal
`be employed to remove exposed portions of the ultra-thin
`photoresist
`layer 16. Within about 10 seconds after
`containing materials. For oxide hardmasks,
`the etching
`development, an aqueous HF solution is contacted with the
`solution is one ofa buffered oxide etch solution (BOE)or an
`structure 10 wherein exposed portions of the hardmask layer
`HFsolution. For nitride hardmasks,the etching solution is a
`14 are removed. The ultra-thin photoresist layer 16 is also
`phosphoric acid solution. And for metal containing
`removed by the acid solution.
`hardmasks, the etching solution is a peroxide solution, such
`as an aqueous H,O,solution.
`As a result of development and acid etching, a pattern is
`After the hardmaskis patterned, the structure is optionally
`formed in the hardmasklayer 14. Deionized water is depos-
`ited over the structure 10 (as it is spinning) and specifically
`rinsed with deionized water. Alternatively or additionally, an
`organic liquid or a stripper solution may be contacted with
`over the patterned hardmask layer 14 to remove anyresidual
`the structure to completely remove any portions of the
`developer, acid solution, and/or debris. The structure 10 is
`ultra-thin resist
`that may remain on the structure after
`then optionally subject to soft bake to drive off any water
`contact with the hardmasketching solution. As a result of the
`from the surface of the patterned hardmask layer 14. Since
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`Case 6:20-cv-01216-ADA Document 41-12 Filed 10/06/21 Page 11 of 14
`Case 6:20-cv-01216-ADA Document 41-12 Filed 10/06/21 Page 11 of 14
`
`US 6,762,133 B1
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`7
`the patterned ultra-thin photoresist layer 16 is not subjected
`to drying or baking, problems associated with pattern col-
`lapse are mitigated.
`In another embodiment, referring to FIG. 3, a semicon-
`ductor structure 18 including a semiconductor substrate 20
`having a hardmask layer 21 thereover is provided. Semi-
`conductor substrate 20 may include any suitable semicon-
`ductor material
`(one or more layers of semiconductor
`materials), for example, a monocrystalline silicon substrate.
`Semiconductor substrate 20 may additionally include of one
`or more layers including substrate layers, diffusion regions,
`dielectric layers such as oxides andnitrides, devices, poly-
`silicon layers, and the like. The hardmasklayer 21 is silicon
`nitride and has a thickness of about 750 A orless in this
`embodiment.
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`26 having a hardmask layer 27 thereover is provided.
`Semiconductor substrate 26 may include any suitable semi-
`conductor material (one or more layers of semiconductor
`materials), for example, a monocrystalline silicon substrate.
`Semiconductor substrate 26 may additionally include of one
`or more layers including substrate layers, diffusion regions,
`dielectric layers such as oxides and nitrides, devices, poly-
`silicon layers, and the like. The hardmask layer 27 is
`titanium nitride and has a thickness of about 1,200 Aorless
`in this embodiment.
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`An ultra-thin photoresist layer 28 is then formed over the
`hardmask layer 27. The ultra-thin photoresist is deposited
`over the hardmask layer 27 using any suitable technique,
`such as conventional spin-coating or spin casting tech-
`niques. The ultra-thin photoresist layer 28 also has a thick-
`An ultra-thin photoresist layer 22 is then formed over the
`ness of about 800 A orless. Since the ultra-thin photoresist
`hardmask layer 21. The ultra-thin photoresist is deposited
`layer 28 is relatively thin compared with I-line and other
`over the hardmask layer 21 using any suitable technique,
`photoresists, improved resolution over I-line photoresists is
`such as conventional spin-coating or spin casting tech-
`realized. In this embodiment, the ultra-thin photoresist layer
`niques. The ultra-thin photoresist layer 22 also has a thick-
`28 is a positive type photoresist.
`ness of about 1,500 A orless.Since the ultra-thin photoresist
`The ultra-thin photoresist layer 28 of the semiconductor
`layer 22 is relatively thin compared with I-line and other
`structure 25 is then selectively exposed to actinic radiation
`photoresists, improved resolution overI-line photoresists is
`(shown by the arrows) through a lithography mask (not
`realized. In this embodiment, the ultra-thin photoresist layer
`shown). The ultra-thin photoresist layer 28 is selectively
`25
`22 is a positive type photoresist.
`exposed using electromagnetic radiation havingarelatively
`The ultra-thin photoresist layer 22 of the semiconductor
`small wavelength (for example, less than 160 nm). In this
`structure 18 is then selectively exposed to actinic radiation
`embodiment, electromagnetic radiation having a wavelength
`(shown by the arrows) through a lithography mask (not
`of about 157 nm is employed. The ultra-thin photoresist
`shown). The ultra-thin photoresist layer 22 is selectively
`layer 28 is selectively exposed to radiation; that is, selected
`30
`exposed using electromagnetic radiation havingarelatively
`portions of the ultra-thin photoresist layer 28 are exposed to
`small wavelength (for example, less than 200 nm). In this
`radiation (corresponding to the regions directly underneath
`embodiment, electromagnetic radiation having a wavelength
`the openings in the lithography mask) while other portions
`of about 193 nm is employed. The ultra-thin photoresist
`of the ultra-thin photoresist
`layer 28 are not exposed
`layer 22 is selectively exposed to radiation; that is, selected
`(corresponding to the regions directly underneaththe lithog-
`portions of the ultra-thin photoresist layer 22 are exposed to
`raphy mask).
`radiation (corresponding to the regions directly underneath
`Referring to FIG. 6, the ultra-thin photoresist layer 28 of
`the openings in the lithography mask) while other portions
`the semiconductor structure 25 is developed by contact with
`of the ultra-thin photoresist
`layer 22 are not exposed
`a suitable developer that removes the exposed portions of
`(corresponding to the regions directly underneath the lithog-
`the ultra-thin photoresist layer 28 thereby exposing a portion
`raphy mask).
`of the hardmask layer 27 and temporarily providing a
`Referring to FIG. 4, the ultra-thin photoresist layer 22 of
`patterned ultra-thin photoresist layer. In-this embodiment,
`the semiconductor structure 18 is developed by contact with
`an aqueous tetramethylammonium solution may be
`a suitable developer that removes the exposed portions of
`employed to remove exposed portions of the ultra-thin
`the ultra-thin photoresist layer 16 thereby exposing a portion
`photoresist
`layer 28. Within about 20 seconds after
`of the hardmask layer 21 and temporarily providing a
`development, an aqueous hydrogen peroxide solution is
`patterned ultra-thin photoresist layer. In this embodiment, an
`contacted with the structure 25 wherein exposed portions of
`aqueous tetramethylammonium hydroxide solution may be
`the hardmask layer 27 are removed. The ultra-thin photo-
`employed to remove exposed portions of the ultra-thin
`resist layer 28 is also removed by the peroxide solution.
`photoresist layer 22. The pattened ultra-thin resist is con-
`tacted with deionized water for 5 seconds and then within
`As aresult of development and peroxide etching, a pattern
`is formed in the hardmask layer 27. Deionized water is
`about 5 seconds after development, an aqueous phosphoric
`acid solution is contacted with the structure 18 wherein
`deposited over the structure 25 and specifically over the
`patterned hardmask layer 27 to remove any residual
`exposed portions of the hardmask layer 21 are removed. The
`developer, peroxide solution, and/or debris. The structure 25
`ultra-thin photoresist layer 22 is also substantially removed
`is then optionally subject to soft bake to drive off any water
`by the acid solution.
`from the surface of the patterned hardmask layer 27. Since
`As a result of development and acid etching, a pattern is
`the patterned ultra-thin photoresist layer 28 is not subjected
`formed in the hardmasklayer 21. Deionized water is depos-
`to drying or baking, problems associated with pattern col-
`ited over the structure 10 (as it is spinning) and specifically
`lapse are mitigated.
`over the patterned hardmask layer 21 to remove any residual
`The present invention further relates to systemsfor in situ
`developer, acid solution, and/or debris. The structure 18 is
`developer etch of hardmasks. FIG. 7 illustrates a system 30
`then optionally subject to soft bake to drive off any water
`for in-situ developer etch of hardmasks in a semiconductor
`from the surface of the patterned hardmask layer 21. Since
`process, schematically indicated at 31. The process 31, for
`the patterned ultra-thin photoresist layer 22 is not subjected
`example,
`includes monitoring resist development and/or
`to drying or baking, problems associated with pattern col-
`hardmask etching.
`lapse are mitigated.
`In yet another embodiment, referring to FIG. 5, a semi-
`The system 30 also includes a