Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 1 of 41
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`SOLAS OLED LTD.,
`
`Plaintiff,
`
`v.
`
`GOOGLE LLC,
`
`Defendant.
`
`SOLAS OLED LTD.,
`
`Plaintiff,
`
`v.
`
`APPLE INC.,
`
`Defendant.
`
`SOLAS OLED LTD.,
`
`Plaintiff,
`
`v.
`
`HP INC.,
`
`Defendant.
`
`Case No. 6:19-cv-00515-ADA
`
`Case No. 6:19-cv-00537-ADA
`
`Case No. 6:19-cv-00631-ADA
`
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`DEFENDANTS’ AND INTERVENTOR’S RESPONSIVE CLAIM CONSTRUCTION
`BRIEF
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 2 of 41
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`TABLE OF CONTENTS
`
`Page
`
`I.
`
`II.
`
`U.S. PATENT NO. 7,446,338 (“’338 PATENT”) ............................................................ 1
`A.
`“transistor array substrate” (claim 1) ..................................................................... 1
`B.
`“project from a surface of the transistor array substrate” (claim 1) ....................... 5
`U.S. PATENT NO. 7,499,042 (“’042 PATENT”) ............................................................ 8
`A.
`“selection period” (Claim 1) .................................................................................. 8
`B.
`“sequentially selects said plurality of selection scan lines in each selection
`period” (Claim 1) ................................................................................................. 10
`“designating current” (Claim 1) ........................................................................... 12
`C.
`“current lines” (Claim 1) ...................................................................................... 15
`D.
`U.S. PATENT NO. 7,663,615 (“’615 PATENT”) .......................................................... 17
`A.
`“the operation” (Claim 11) ................................................................................... 17
`B.
`“precharge voltage” (Claim 11) ........................................................................... 20
`C.
`“writing control section” (Claim 11) ................................................................... 22
`D.
`“data lines” (Claim 11) ........................................................................................ 24
`IV. U.S. PATENT NO. 7,573,068 (“’068 PATENT”) .......................................................... 26
`A.
`“formed on said plurality of supply lines along said plurality of supply
`lines” (Claim 1) / “connected to said plurality of supply lines along said
`plurality of supply lines” (Claim 13) ................................................................... 26
`“signal lines” / “supply lines” (Claims 1, 13) ...................................................... 30
`“source” / “drain” (Claims 1, 13) ......................................................................... 32
`
`III.
`
`B.
`C.
`
`-i-
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 3 of 41
`
`TABLE OF AUTHORITIES
`
`Page(s)
`
`Cases
`Helmsderfer v. Bobrick Washroom Equip., Inc.,
`527 F.3d 1379 (Fed. Cir. 2008) .......................................................................................... 30, 32
`ICU Medical, Inc. v. Alaris Medical Systems, Inc.,
`558 F.3d 1368 (Fed. Cir. 2009) .............................................................................. 12, 16, 25, 32
`In re Downing,
`754 F. App’x 988 (Fed. Cir. 2018) ........................................................................................... 20
`Iridescent Networks, Inc. v. AT&T Mobility, LLC,
`933 F.3d 1345 (Fed. Cir. 2019) ................................................................................................ 22
`Phillips v. AWH Corp.,
`415 F.3d 1303 (Fed. Cir. 2005) .................................................................................... 1, 3, 7, 22
`Praxair, Inc. v. ATMI, Inc.,
`543 F.3d 1306 (Fed. Cir. 2008) ................................................................................................ 28
`Regents of University of Minnesota v. AGA Medical Corp.,
`717 F.3d 929 (Fed. Cir. 2013) ................................................................................ 12, 16, 25, 32
`SimpleAir, Inc. v. Sony Ericsson Mobile Commc’ns AB,
`820 F.3d 419 (Fed. Cir. 2016) .................................................................................................. 17
`Smartflash LLC v. Apple Inc.,
`77 F. Supp. 3d 535 (E.D. Tex. 2014) ........................................................................................ 20
`Smith v. ORBCOMM, Inc.,
`No. 2:14–CV–666, 2015 WL 5302815 (E.D. Tex. Sept. 10, 2015) ......................................... 20
`Solas OLED Ltd. v. Samsung Display Co.,
`2:19-cv-00152-JRG (E.D. Tex., April 15, 2020) .................................................................... 1, 2
`
`-ii-
`
`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 4 of 41
`TABLE OF EXHIBITS
`
`Ex. No. Publication
`AA06
`Solas Notice Of Agreement On Previously Disputed Claim Construction Terms,
`Solas OLED Ltd. v. Samsung Display Co., 2:19-cv-00152-JRG, Dkt. 98 (E.D. Tex.,
`April 15, 2020)
`Steven M. Kaplan, Wiley Electrical and Electronics Engineering Dictionary 237
`(John Wiley & Sons, Inc., 2004)
`Collins Dictionary Electronics 139 (HarperCollins, 2007)
`Erin McKean, The New Oxford American Dictionary 545 (Oxford University Press,
`2nd ed. 2005)
`
`DD08
`DD09
`
`DD07
`
`-iii-
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 5 of 41
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`Solas’s opening brief (“Solas Open. Br.”) takes a flawed approach to claim construction.
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`For many terms, instead of addressing the intrinsic evidence, Solas’s argument consists solely of
`
`repeated refrains that its construction reflects the plain and ordinary meaning and that Solas is not
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`aware of any redefinition or disclaimer. But many of the disputed terms are phrases specially
`
`coined in the patents and have no ordinary meaning outside of the patents. Worse, to support its
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`understanding of the ordinary meaning, Solas cites dictionary definitions rather than the intrinsic
`
`evidence, taking the very approach that the Federal Circuit rejected en banc in Phillips. E.g.,
`
`Phillips v. AWH Corp., 415 F.3d 1303, 1320-21 (Fed. Cir. 2005) (en banc). Precedent is clear that
`
`the ordinary meaning “of a claim term is its meaning to the ordinary artisan after reading the entire
`
`patent” and not “in a vacuum. Rather, we must look at the ordinary meaning in the context of the
`
`written description and the prosecution history.” Id. at 1313, 1321.
`
`Rather than address the intrinsic record, Solas spends most of its opening brief attacking
`
`Defendants’ constructions. But Solas’s attacks ignore the true, substantive differences between
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`the parties’ proposals, favoring instead superficial objections that apply to many of Solas’s own
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`proposals. And for several terms, Solas’s cursory arguments are undermined by the declaration of
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`its own expert, Mr. Richard Flasck (“Flasck Decl.”).
`
`I.
`
`U.S. Patent No. 7,446,338 (“’338 Patent”)
`
`A.
`
`“transistor array substrate” (claim 1)
`
`Plaintiff’s Proposal
`“layered structure upon which or within which
`a transistor array is fabricated”
`
`Defendants’ Proposal
` “a layered structure composed of a bottom
`insulating layer through a topmost layer on
`whose upper surface pixel electrodes are
`formed, which contains an array of transistors”
`
`Solas’s arguments against Defendants’ proposal mirror the arguments Solas originally
`
`made in its briefing and oral argument at the Markman hearing in Solas OLED Ltd. v. Samsung
`
`Display Co., 2:19-cv-00152-JRG (E.D. Tex). Yet unmentioned by Solas is that shortly after it
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`1
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 6 of 41
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`made these arguments in the Eastern District of Texas, Solas explicitly informed the Court that it
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`changed its position, and submitted a “Notice of Agreement” expressly agreeing to Defendants’
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`proposed construction of “transistor array substrate” as the proper construction for that term in
`
`the ’338 patent. Ex. AA06 (Solas OLED Ltd. v. Samsung Display Co.., 2:19-cv-00152-JRG, Dkt.
`
`98 (E.D. Tex., April 15, 2020)). Solas then represented to the PTAB, in responding to Samsung
`
`Display Co.’s IPR petition on the ’338 patent, that Solas had agreed to the Defendants’ proposed
`
`construction of “transistor array substrate” in the ’338 Patent. Defs. Open. Br., Ex. AA05 at 27–
`
`28. Judge Gilstrap ultimately did not accept Solas’s “late-breaking Notice of Agreement,” which
`
`Solas did not submit to the Court until two days before the Court issued its claim construction
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`opinion and Order. But Solas’s representations to the PTAB are new intrinsic evidence supporting
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`Defendants’ construction. Thus, there is a crucial difference between this proceeding and the
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`Eastern District of Texas matter, and important new evidence that supports Defendants’ proposed
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`construction.
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`Solas is hard-pressed to argue that Defendants’ construction is inappropriate, given that
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`Solas informed the Eastern District of Texas, and the PTAB, that Solas agrees to that construction.
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`Moreover, Solas offers no sound reason for turning its back on its prior agreement, and advancing
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`a position inconsistent with what it urged before the PTAB and represented to Judge Gilstrap was
`
`an appropriate construction of the ’338 Patent. Indeed, it is ironic that Solas devotes much of its
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`brief to chiding Defendants for purportedly seeking a “do-over” when Defendants are simply
`
`proposing the same construction that Solas itself agreed to and represented to the PTAB that it was
`
`agreeing to.
`
`As noted in Defendants’ opening brief (“Defs. Open. Br.,” Dkt. 73 in the Google action,
`
`No. 6:19-cv-00515-ADA), the Eastern District found that the specification’s references to a
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`2
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 7 of 41
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`transistor array substrate containing an array of transistors did not justify including the
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`requirement. See Defs. Open. Br., Ex. AA02 at 14. Defendants respectfully submit that the claim
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`language of the ’338 Patent is decisive and supports Defendants’ construction, as outlined in
`
`Defendants’ opening brief. Defs. Open. Br. at 2–5. None of Solas’s arguments to the contrary are
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`persuasive, and, in fact, many were expressly rejected as part of Judge Gilstrap’s Order.
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`Defendants’ proposed construction of the term “transistor array substrate” is the meaning
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`given to that term in the ’338 Patent. While Solas cites to dictionary definitions of “substrate” in
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`support of its construction, Solas does not cite to a single dictionary definition of the term at issue,
`
`“transistor array substrate.” Solas Open. Br. at 9. That is because, unlike the term “substrate,” the
`
`term “transistor array substrate” has no ordinary and customary meaning in the art, as recognized
`
`by Judge Gilstrap and Solas’s expert. Defs. Open. Br., Ex. AA02 (Claim Construction
`
`Memorandum and Order) at 10 (“Plaintiff’s expert has acknowledged that the term ‘transistor array
`
`substrate’ does not have a specific, well-established meaning in the relevant art.”). In fact, the
`
`’338 Patent explicitly describes an “insulating substrate 2”—the substrate described in Solas’s
`
`dictionary definitions—as being only one of numerous different layers that make up the ’338
`
`Patent’s “transistor array substrate.” ’338 at 10:42–47 (“The layered structure from the insulating
`
`substrate 2 to the planarization film 33 is called a transistor array substrate 50.”). While
`
`dictionaries may assist the Court in determining the meaning of particular terminology, extrinsic
`
`evidence like dictionaries is “less significant than the intrinsic record in determining the legally
`
`operative meaning of claim language.” Phillips, 415 F.3d at 1317 (internal quotation marks
`
`omitted). Here, the claim language is determinative. The “transistor array substrate” must
`
`“comprise a plurality of transistors,” and must consist of the layers formed under the pixel
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`3
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 8 of 41
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`electrodes, given that the pixel electrodes are “arrayed . . . on the surface transistor array
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`substrate.” ’338 at 24:15–25 (Emphasis added).
`
`Solas criticizes Defendants for relying on, in addition to the claim language, the
`
`embodiment shown in Figure 6. But the Figure 6 embodiment is consistent with the claim
`
`language described above, and is the figure that the patent used to describe the structure of the
`
`claimed inventions. Significantly, the specification does not disclose any “transistor array
`
`substrate” other than the “transistor array substrate 50” shown in Figure 6. Consistent with
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`Defendants’ construction, the ’338 Patent states that “[t]he layered structure from the insulating
`
`substrate 2 to the planarization film 33 is called a transistor array substrate 50.” ’338 at 10:45–47.
`
`Solas also errs in asserting that Defendants’ construction is somehow inconsistent with the
`
`specification in defining the top of the “transistor array substrate” in terms of its relationship to the
`
`pixel electrodes, as opposed to “insulating line 61.” Solas Open. Br. at 10–11. There is no
`
`inconsistency. Defendants’ construction comes directly from the claim language, which, as
`
`described above, expressly states that the pixel electrodes are formed on the surface of the
`
`transistor array substrate. See also ’338 at 11:50–52 (“The plurality of sub-pixel electrodes 20a
`
`are arrayed in a matrix on the upper surface of the transistor array substrate 50.”). The claim does
`
`not require the insulating layer, but specifies that the pixel electrodes are on the surface of the
`
`transistor array substrate. The fact that another structure such as insulating line 61 may also be on
`
`a portion of the transistor array substrate does not detract in any way from the fact that the pixel
`
`electrodes are on the surface of the transistor array substrate. Notably, when Solas made the same
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`flawed argument in the Eastern District, Judge Gilstrap found that “Plaintiff fail[ed] to justify
`
`precluding multiple structures from being formed on a transistor array substrate.” Defs. Open. Br.,
`
`Ex. AA02 (Claim Construction Memorandum and Order) at 12–13.
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`4
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 9 of 41
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`Similarly, as it did in the Eastern District, Solas erroneously argues that Defendants’
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`construction would exclude a “top emission type” embodiment of the ’338 Patent from the claims.
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`Solas Open. Br. at 11. But as Judge Gilstrap concluded, Solas’s argument has no merit:
`
`“Defendants’ proposed construction is . . . consistent with both the ‘bottom emission type’ and the
`
`‘top emission type.’” Defs. Open. Br., Ex. AA02 (Claim Construction Memorandum and Order)
`
`at 12. “If a reflecting film is thus present, then under Defendants’ proposed construction the
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`reflecting film would be part of the ‘transistor array substrate’ because the reflecting film would
`
`be the layer upon which the pixel electrodes are formed.” Id.
`
`Thus, consistent with the intrinsic evidence, as well as Solas’s prior agreement, “transistor
`
`array substrate” should be construed as “a layered structure composed of a bottom insulating layer
`
`through a topmost layer on whose upper surface pixel electrodes are formed, which contains an
`
`array of transistors”1
`
`B.
`
` “project from a surface of the transistor array substrate” (claim 1)
`
`Plaintiff’s Proposal
`“extend from an external surface of the
`transistor array substrate”2
`
`Defendants’ Proposal
` “extend above the upper surface of the
`transistor array substrate”
`
`The specification makes clear that the interconnections “project upward from the upper
`
`transistor array substrate, as Defendants propose. The ’338 Patent explains that “[t]he common
`
`interconnection 91 is . . . formed to . . . project upward from the surface of the planarization film
`
`1 To the extent Solas takes issue with Defendants’ construction including the term “insulating
`layer,” Solas Open. Br. at 9, to narrow the dispute, Defendants would be willing to alter their
`construction to “a layered structure composed of a bottom substrate layer through a topmost layer
`on whose upper surface pixel electrodes are formed, which contains an array of transistors.”
`2 Solas proposed this construction in its exchange of proposed claim constructions and included it
`in the box at the beginning of the section for this term in its opening brief. See Solas Open. Br. at
`12. However, in its brief, Solas urges the Court to “adopt the constructions that Judge Gilstrap
`held were correct” i.e. “extend beyond an outer surface of the transistor array substrate. See id.,
`Defs. Open. Br., Ex. AA02 (Claim Construction Memorandum and Order) at 12–13 at 18.
`
`5
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 10 of 41
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`33.” ’338 at 10:54-58 (emphasis added). The specification then further explains that “select
`
`interconnection 89 and feed interconnection 90 project upward from the upper surface of the
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`planarization film 33.” Id. at 11:36-41 (emphasis added). As the patent explains, the “surface” or
`
`“upper surface” of the planarization film 33 is the upper surface of the transistor array substrate.
`
`See, e.g., id. at 10:49-51 (“the surface of the planarization film 33, i.e., the surface of the transistor
`
`array substrate 50”) (emphasis added); 11:50-52 (“the upper surface of the planarization film 33,
`
`i.e., the upper surface of the transistor array substrate 50”). Figure 6 (annotated below) confirms
`
`this, showing the interconnections (89, 90, and 91 shown in red) all extend above the upper surface
`
`of the planarization film (33 shown in yellow) of the transistor array substrate 50:
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`While Judge Gilstrap largely adopted Defendants’ construction in the Eastern District of
`
`Texas litigation, he declined to include the “upper” portion of Defendants’ construction, stating
`
`that the term “upper” “lacks sufficiently clear meaning in the context of a ‘display panel’ as
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`claimed in . . . Claim 1.” Defs. Open. Br., Ex. AA02 (Claim Construction Memorandum and
`
`Order) at 18. Defendants respectfully disagree in that their proposed construction uses the same
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`language that the patent uses, which would be understood by persons skilled in the art and would
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`assist the jury by clarifying how the interconnections project from the transistor array substrate.
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`6
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 11 of 41
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`Solas’s briefing shows why the inclusion of “upper” in the construction is necessary. Solas
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`argues the specification’s references to interconnections that “project upward from the upper
`
`surface of the planarization film” and interconnections that “project upward from the surface of
`
`the planarization film” shows that “the specification does not always specify that interconnections
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`project from the upper surface.” Dkt. 74 at 12 (emphases added). Solas’s argument assumes that
`
`the interconnections, which the specification states are formed to “project upward,” can project
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`upward from a surface other than the upper surface of the transistor array substrate. But this is
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`contradicted by the very construction that Solas advances, which requires the interconnections to
`
`“extend beyond an outer surface of the transistor array substrate,” as an interconnection cannot
`
`project upward and extend beyond any outer surface other than the upper surface.
`
`Further, if the interconnections did not extend beyond the upper surface of the transistor
`
`array substrate, they would not fulfill a stated purpose of the projecting interconnections, which
`
`the ’338 Patent repeatedly explains is to “serve as partition walls to prevent leakage of an organic
`
`compound-containing solution.” See ’338 at 6:24-30, 6:38-42; see also Phillips, 415 F.3d at 1316
`
`(“The construction that stays true to the claim language and most naturally aligns with the patent's
`
`description of the invention will be, in the end, the correct construction.”). The interconnections
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`must extend past the upper surface of the transistor array substrate to serve as leakage-preventing
`
`partition walls, as the specification explains: “[t]he thick select interconnection 89, feed
`
`interconnection 90, and common interconnection 91 whose tops are much higher than that of the
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`insulating line 61 are formed between the sub-pixel electrodes 20a adjacent in the vertical direction
`
`to project [sic] respect to the surface of the transistor array substrate 50. Hence, the organic
`
`compound-containing solution applied to a sub-pixel electrode 20a is prevented from leaking to
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`the sub-pixel electrode 20a adjacent in the vertical direction.” Id. at 12:62-13:3 (emphases added).
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`7
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 12 of 41
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`As seen in Fig. 6 (annotated above), insulating line 61 is located along the upper surface of the
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`transistor array substrate. The interconnections extend above the upper surface of the transistor
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`array substrate, as Defendants propose, to perform this function, and could not do so if they
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`projected from the other external surfaces (i.e., the side or bottom surfaces).
`
`II.
`
`U.S. Patent No. 7,499,042 (“’042 Patent”)
`
`A.
`
`“selection period” (Claim 1)
`
`Solas’s Proposal
`“time period during which a plurality of
`pixel circuits is selected”
`
`HP’s Proposal
`“time duration in which a selected selection scan
`line is kept active”
`
`Solas’s opening brief shows that its attempt to define “selection period” without reference
`
`to a “selection scan line” is contrived, contrary to the specification’s express definition, and leads
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`to absurd results. Conversely, Solas raises no substantive disputes with HP’s construction. Solas,
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`for example, does not dispute that a “selection period” refers to the time a “selection scan line” is
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`active, or that the “selection scan line” must be kept active during this entire period. Instead, Solas
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`nitpicks over whether the words “duration” and “active” are ambiguous in HP’s construction.
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`As described in HP’s
`
`opening brief and illustrated
`
`in Figure 4 (annotated), the
`
`specification
`
`expressly
`
`defines “selection period” as
`
`the
`
`time when
`
`one
`
`corresponding
`
`“selection
`
`scan line” is selected and kept active (blue), while defining other inactive times as a “non-selection
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`period” (red) for that “selection scan line”. Defs. Open. Br. at 9-11; ’042 at 9:13-32, 9:49-57. At
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`any given time, only one “selection scan line” for one row of pixels in a display panel is selected.
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`8
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`

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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 13 of 41
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`Solas acknowledges that the meaning of “selection period” is tied to a “selection scan line.”
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`Solas Open. Br. at 17-18. In particular, Solas quotes the same, aforementioned definition of
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`“selection period” from the specification: “a period in which the selection scan driver 5 … selects
`
`the selection scan line Xi in the ith row is called a selection period TSE of the ith row.” Id. at 17
`
`(citing ’042 at 9:22-27). As Solas further acknowledges, each “selection scan line” is connected
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`to one associated row of pixel circuits. Id. (“In the second transistor 22 of each of the pixel circuits
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`Di,1 to Di,n in the ith row, a gate 22 g is connected to the selection scan line Xi in the ith row.”).
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`Yet, Solas still proposes to construe “selection period” without reference to a “selection scan line”
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`and to instead refer to any period when any “plurality of pixel circuits is selected.”
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`Solas’s proposal leads to the absurd outcome of allowing any time period to be a “selection
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`period.” This is because at any given time during the operation of a display panel, one row of
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`pixel circuits in the display panel is selected, meaning that “a plurality of pixel circuits is selected”
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`at all times. Put differently, Solas’s proposal puts no bounds at all on a “selection period” because
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`during the entire operation of a display panel, some “plurality of pixel circuits” is being selected.
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`HP’s proposal poses no such substantive problems, and Solas identifies none. Instead,
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`Solas objects to only the choice of wording in HP’s construction. First, Solas claims that the term
`
`“kept active” is confusing and not used in the intrinsic evidence. Solas Open. Br. at 17-18. But
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`Solas’s own arguments undermine its claimed confusion. It recognizes that a “selection scan line”
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`is “kept active” when “the “Von” voltage . . . is applied to the selection scan line.” Id. at 18. Thus,
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`Solas recognizes that “kept active” refers to when a “selection scan line” is in the “ON” state.3
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`Critically, Solas presents no dispute
`
`to
`
`the key, substantive requirement
`
`in HP’s
`
`3 HP is amenable to substituting “kept on” for “kept active” to address Solas’s objection.
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`9
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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 14 of 41
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`construction―namely that the “selection scan line” must be kept active (i.e., kept in the “ON”
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`state) during the entire “selection period”; the “selection scan line” cannot be turned off.
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`Second, Solas argues that HP’s construction uses redundant words because it states that the
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`“selection scan line” is both “selected” and “kept active.” Solas claims using both “selected” and
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`“active” is unnecessary because both signify the same thing. Id. HP’s construction, however, uses
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`“kept active” to clarify that a selected “selection scan line” must remain active during the
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`“selection period”―the selected selection scan line cannot be turned off or inactive during this
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`time. Again, Solas presents no substantive dispute. Solas, for example, never suggests that a
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`“selection scan line” can be turned off or inactive during a “selection period.” Any such suggestion
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`would contradict the specification, which uses a separate term, “non-selection period,” to describe
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`a time when a “selection scan line” is inactive. Defs. Open. Br. at 9-11; ’042 at 9:49-57.
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`Third and finally, Solas argues that the term “duration” in HP’s construction is
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`inappropriate because “duration” refers to a time that has no specified beginning point T1 and end
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`point T2. Solas Open. Br. at 18.4 But HP’s construction specifies which duration is discussed:
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`the duration when “a selection scan line is kept active.” This duration begins when a “selection
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`scan line” is selected (T1), and ends when it is de-selected (T2). Solas’s proposal, by contrast,
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`places no limit on when a “selection period” can begin or end because it does not specify which
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`“plurality of pixel circuits” is to be selected in this period as discussed above. Thus, whereas HP’s
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`construction gives “selection period” a meaning that comports fully with the intrinsic record, Solas
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`proposal gives the term no meaning at all.
`
`B.
`
`“sequentially selects said plurality of selection scan lines in each selection
`period” (Claim 1)
`
`Solas’s Proposal
`
`HP’s Proposal
`
`4 HP does not object to substitution of “period” for “duration,” if deemed appropriate by the Court.
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`10
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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 15 of 41
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`Plain and ordinary
`meaning
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`“selects said plurality of selection scan lines one per each of a plurality
`of non-overlapping selection periods”
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`As discussed in HP’s opening brief, the 12-word phrase at issue here requires construction
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`because it is a lengthy, technical phrase that lacks a plain and ordinary meaning outside the context
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`of the ’042 Patent. Defs. Open. Br. at 12-13. Hence, Solas is incorrect in asserting that the phrase’s
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`meaning can be derived from the dictionary definitions of just one of its twelve words,
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`“sequentially.” Solas Open. Br. at 19.
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`While incorrectly basing its construction on dictionary definitions of “sequentially,” Solas
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`disregards the intrinsic evidence, which confirms that “selection periods” for different “selection
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`scan lines” must be “non-overlapping” in time, as detailed in HP’s opening brief. Defs. Open. Br.
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`at 12-13. To reiterate, the specification states that “the selection periods TSE of the selection scan
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`lines X1 to Xm do not overlap
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`each other.” ’042 at 9:29-31.
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`This is because, as shown in
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`Figure 4 (annotated), selection
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`scan lines are selected one at a
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`time; when an ON voltage is
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`applied
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`to one
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`line, “the
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`selection scan driver 5 applies the OFF voltage VOFF to the other selection scan lines.” Id. at
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`9:26-29. Therefore the “selection period” TSE for any one selection scan line (blue) occurs only
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`during the non-selection periods TNSE of the other selection scan lines (red).
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`Contrary to Solas’s assertion, it is not the case that merely “an embodiment” discloses non-
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`overlapping selection periods, while other embodiments do not. Solas Open. Br. at 19. Rather,
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`every embodiment discloses non-overlapping selection periods while none discloses two or more
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`11
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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 16 of 41
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`periods at overlapping times, as permitted under Solas’s overbroad construction. On similar facts,
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`in Regents of University of Minnesota v. AGA Medical Corp., the Federal Circuit construed “first
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`and second disks” to create “separate[] . . . physically distinct disks” because the “specification
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`never teaches an embodiment constructed as a single piece. Quite the opposite: every single
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`embodiment disclosed in the . . . patent’s drawings and its written description is made up of two
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`separate disks.” 717 F.3d 929, 935-36 (Fed. Cir. 2013). Likewise, in ICU Medical, Inc. v. Alaris
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`Medical Systems, Inc., the Federal Circuit construed “spike” to require a “pointed tip” because
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`“[t]he specification never suggests that the spike can be anything other than pointed” and “each
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`figure depicts the spike as elongated and pointed.” 558 F.3d 1368, 1375-76 (Fed. Cir. 2009). Here,
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`every relevant figure and passage of the specification discloses non-overlapping selection periods.
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`Solas’s argument that the claim language “injects the possibility” of overlapping selection
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`periods is incorrect for the same reason. Solas Open. Br. at 20. There is no embodiment where
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`two (or more) selection scan lines can be selected at the same time, and Solas identifies none.
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`Moreover, such an embodiment would be absurd and fundamentally at odds with the operation
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`OLED circuits, which select only one selection scan line at a time. Defs. Open. Br. at 13-14.
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`C.
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`“designating current” (Claim 1)
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`Solas’s Proposal
`Plain and ordinary meaning, i.e.,
`current designating a value
`corresponding to an image signal
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`HP’s Proposal
`“current corresponding to an image signal having a
`specified current value that is held constant”
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`Solas’s claim that “‘designating current’ has a plain and ordinary meaning, understood by
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`a POSITA” is unsupported and incorrect. Solas Open. Br. at 20. To the contrary, “designating
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`current” is a term coined by the ’042 Patent and its meaning must therefore be derived from the
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`context of the intrinsic evidence. Here, the specification makes clear that a “designating current”
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`12
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`Case 6:19-cv-00537-ADA Document 49 Filed 07/16/20 Page 17 of 41
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`must have a constant current value5 that corresponds to an image signal. Defs. Open. Br. at 14-
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`15. Ignoring this express specification statement, Solas presents a slew of self-contradicting
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`arguments that misinterpret other specification passages out of context.
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`First, Solas argues that “the specification never describes the designating current as held
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`constant during the first reset portion” of a selection period and claims that ignoring this “reads
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`out a preferred embodiment.” Solas Open. Br. at 20-21. But Solas ignores that no “designating
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`current” even exists during the “first reset portion” of a selection period.
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`As context, each selection period is divided into two sub-periods: (1) a first sub-period,
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`known as the “reset period TR of the ith row,” where “the [data driving circuit] switches S1 to Sn
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`apply the reset voltage VR to the current lines Y1 to Yn” (’042 at 13:10-30); and (2) a second sub-
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`period where, a “designating current IDATA” is applied “after the reset period TR” (id. at 13:60-64).
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`The data driver is only able to supply one of these signals―either reset voltage or designating
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`current―at a time, as it contains a “switch Sj [that]. . . switches the state in which the current
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`source driver 3 supplies the tone designating current IDATA to the current line Yj, and the state in
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`