Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 1 of 40
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE WESTERN DISTRICT OF TEXAS
`WACO DIVISION
`
`SOLAS OLED LTD.,
`
`Plaintiff,
`
`v.
`
`GOOGLE LLC,
`
`Defendant.
`
`SOLAS OLED LTD.,
`
`Plaintiff,
`
`v.
`
`APPLE INC.,
`
`Defendant.
`
`SOLAS OLED LTD.,
`
`Plaintiff,
`
`v.
`
`HP INC.,
`
`Defendant.
`
`Case No. 6:19-cv-00515-ADA
`
`Case No. 6:19-cv-00537-ADA
`
`Case No. 6:19-cv-00631-ADA
`
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`DEFENDANTS’ AND INTERVENOR’S OPENING CLAIM CONSTRUCTION BRIEF
`
`

`

`I.
`
`II.
`
`III.
`
`IV.
`
`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 2 of 40
`
`TABLE OF CONTENTS
`
`Page
`
`U.S. PATENT NO. 7,446,338 (“’338 PATENT”) ............................................................ 1
`A.
`’338 Patent Background ......................................................................................... 1
`B.
`“transistor array substrate” (claim 1) ..................................................................... 2
`1.
`The transistors are contained in the transistor array substrate ................... 2
`2.
`The ’338 Patent defines which layers of an OLED display panel
`constitute the “transistor array substrate” .................................................. 3
`“project from a surface of the transistor array substrate” (claim 1) ....................... 5
`C.
`U.S. PATENT NO. 7,499,042 (“’042 PATENT”) ............................................................ 8
`A.
`’042 Patent Background ......................................................................................... 8
`B.
`“selection period” (Claim 1) .................................................................................. 9
`C.
`“sequentially selects said plurality of selection scan lines in each selection
`period” (Claim 1) ................................................................................................. 12
`“designating current” (Claim 1) ........................................................................... 14
`D.
`“current lines” (Claim 1) ...................................................................................... 15
`E.
`U.S. PATENT NO. 7,663,615 (“’615 PATENT”) .......................................................... 16
`A.
`’615 Patent Background ....................................................................................... 16
`B.
`“the operation” (Claim 11) ................................................................................... 17
`C.
`“precharge voltage” (Claim 11) ........................................................................... 19
`D.
`“writing control section” (Claim 11) ................................................................... 21
`E.
`“data lines” (Claim 11) ........................................................................................ 23
`U.S. PATENT NO. 7,573,068 (“’068 PATENT”) .......................................................... 24
`A.
`“formed on said plurality of supply lines along said plurality of supply
`lines” (Claim 1) / “connected to said plurality of supply lines along said
`plurality of supply lines” (Claim 13) ................................................................... 24
`“signal lines” / “supply lines” (Claims 1, 13) ...................................................... 29
`“source” / “drain” (Claims 1, 13) ......................................................................... 30
`
`B.
`C.
`
`-i-
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`

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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 3 of 40
`TABLE OF AUTHORITIES
`
`Page
`
`Cases
`Bell Atl. Network Servs., Inc. v. Covad Commc’ns Grp, Inc.,
`262 F.3d 1258 (Fed. Cir. 2001) ................................................................................................ 31
`Cellular Communications Equipment LLC v. AT&T, Inc.,
`No. 2:15-CV-576-RWS-RSP, 2016 WL 7364266 (E.D. Tex. Dec. 19, 2016) ......................... 17
`Genentech, Inc. v. Chiron Corp.,
`112 F.3d 495 (Fed. Cir. 1997) .................................................................................................... 2
`Glaxo Grp. Ltd. v. Ranbaxy Pharm., Inc.,
`262 F.3d 1333 (Fed. Cir. 2001) ................................................................................................ 11
`Halliburton Energy Serv., Inc. v. M-I LLC,
`514 F.3d 1244 (Fed. Cir. 2008) ................................................................................................ 17
`Helmsderfer v. Bobrick Washroom Equip., Inc.,
`527 F.3d 1379 (Fed. Cir. 2008) ................................................................................................ 29
`Image Processing Technologies, LLC v. Samsung Electronics Co.,
`No. 2:16-cv-505, 2017 WL 2672616 (E.D. Tex. June 21, 2017) ............................................. 18
`Novo Indus., L.P. v. Micro Molds Corp.,
`350 F.3d 1348 (Fed. Cir. 2003) ................................................................................................ 18
`Praxair, Inc. v. ATMI, Inc.,
`543 F.3d 1306 (Fed. Cir. 2008) ................................................................................................ 28
`Sinorgchem Co., Shandong v. Int’l Trade Comm’n,
`511 F.3d 1132 (Fed. Cir. 2007) .................................................................................................. 4
`Smartflash LLC v. Apple Inc.,
`77 F. Supp. 3d 535 (E.D. Tex. 2014) ........................................................................................ 19
`Smith v. ORBCOMM, Inc.,
`No. 2:14–CV–666, 2015 WL 5302815 (E.D. Tex. Sept. 10, 2015) ......................................... 19
`Teva Pharmaceuticals v. Sandoz,
`723 F.3d 1363 (Fed. Cir. 2013) ................................................................................................ 21
`Trustees of Bos. Univ. v. Everlight Elecs. Co.,
`896 F.3d 1357 (Fed. Cir. 2018) ................................................................................................ 27
`
`-ii-
`
`

`

`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 4 of 40
`TABLE OF EXHIBITS
`
`AA02
`
`AA03
`
`BB04
`
`DD01
`
`AA04
`AA05
`BB01
`BB02
`BB03
`
`Ex. No. Publication
`AA01
`Excerpt from Prosecution History of U.S. Patent No. 7,446,338 – February 25,
`2008 Amendment
`Claim Construction Memorandum and Order, Solas OLED Ltd. v. Samsung
`Display Co. Ltd., et al., 2:19-cv-00152-JRG, Dkt. 99 (Apr. 17, 2020, E.D. Tex.)
`Excerpts from Deposition of Richard A. Flasck, Solas OLED Ltd. v. Samsung
`Display Co. Ltd. et al., 2:19-cv-00152-JRG (Feb. 6, 2020, W.D. Tex.)
`Solas’s Proposed terms for Construction
`Patent Owner’s Preliminary Response, IPR2020-00320 (April 25, 2020, PTAB)
`Prosecution History of European Patent Application No. 1,372,136
`Prosecution History of U.S. Patent No. 7.499,042
`Jiun-Haw Lee et al., Introduction to Flat Panel Displays 50-52 (John Wiley &
`Sons 2008)
`Johnathan Halls, Short Course S-4: Fundamentals of OLEDs/PLEDs, S-4/101
`(Society for Information Display, May 18, 2008)
`Declaration of Richard A. Flasck in Support Of Solas’s Responsive Claim
`Construction Brief, Solas OLED Ltd. v. LG, Ltd., et al, 6:19-cv-00236-ADA
`(Apr. 3, 2020, W.D. Tex.)
`Solas’s Reply Claim Construction Brief, Solas OLED Ltd. v. LG, Ltd., et al, 6:19-
`cv-00236-ADA (Apr. 24, 2020, W.D. Tex.)
`Videoconference Deposition of Richard A. Flasck, Solas OLED Ltd. v. LG, Ltd.,
`et al, 6:19-cv-00236-ADA, Dkt._82 (Apr. 14, 2020, W.D. Tex.)
`Phillip A. Laplante, Comprehensive Dictionary of Electrical Engineering 213,
`643 (Taylor & Francis Group, 2nd ed. 2005)
`Stan Gibilisco, The Illustrated Dictionary of Electronics 179 (McGraw-Hill, 8th
`ed. 2001)
`A Dictionary of Science 738-39 (Oxford University Press, 2006)
`
`DD02
`
`DD03
`
`DD04
`
`DD05
`
`DD06
`
`-iii-
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`

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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 5 of 40
`
`The Defendants and Intervenor hereby submit their Opening Claim Construction Brief.
`
`I.
`
`U.S. Patent No. 7,446,338 (“’338 Patent”)
`
`A.
`
`’338 Patent Background
`
`The ’338 Patent is directed to active-matrix organic electroluminescent (AMOLED)
`
`display panels. See, e.g., ’338 at 1:17-21, 8:18-23. These are many-layered devices that consist
`
`of organic electroluminescent pixels and circuitry, which drive the pixels to produce particular
`
`colors and brightness. Figure 6 illustrates the layered structure of an exemplary display panel of
`
`the ’338 Patent, consisting of two main structures: (1) the red, green, and blue OLED pixels (Pr,
`
`Pg, and Pb), each made up of a pixel electrode 20a, an electroluminescent layer 20b, and a counter
`
`electrode 20c; and (2) the layers making up the “transistor array substrate” 50, id. at 10:42-47,
`
`which includes the transistors 21 and 23 that make up the active-matrix circuit for each pixel:
`
`In the original patent application, prosecution claim 1 was directed to the arrangement of
`
`elements in the layered structure, as exemplified by Figure 6. That claim, however, was rejected
`
`as anticipated by prior art. To overcome the rejection, the applicants amended claim 1 to recite
`
`the particular three-transistor pixel circuit structure recited by a dependent claim (prosecution
`
`claim 2), illustrated in Figure 2 of the ’338 Patent. Ex. AA01 at 2-3, 12. This three-transistor
`
`circuit uses a pull-out current, which the patent refers to as a write current, to set the brightness of
`
`1
`
`

`

`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 6 of 40
`
`each individual pixel. This current-controlled structure differed from circuits that used particular
`
`voltage signal levels applied to the gate of the driving transistor, rather than current, to control
`
`pixel brightness. See, e.g., ’338 at 1:21-41 (describing that in a prior art reference, “a voltage of
`
`level representing the luminance is applied to the gate of the driving transistor through a signal
`
`line.”). After the addition of this three-transistor circuit structure limitation, the claims of the ’338
`
`Patent were allowed.
`
`B.
`
` “transistor array substrate” (claim 1)
`
`Plaintiff’s Proposal
`“layered structure upon which or within which
`a transistor array is fabricated”
`
`Defendants’ Proposal
` “a layered structure composed of a bottom
`insulating layer through a topmost layer on
`whose upper surface pixel electrodes are
`formed, which contains an array of transistors”
`
`The term “transistor array substrate” has no customary meaning in the art. It is a term
`
`specific to the ’338 Patent, which the ’338 Patent defines as a layered structure composed of a
`
`bottom substrate layer through a topmost layer on whose upper surface electrodes are formed,
`
`which contains an array of transistors. See, e.g., ’338 at 10:45-47, cl. 1. Both the language of
`
`claim 1 and the specification support Defendants’ proposal. Solas’s construction, in contrast, is
`
`inconsistent with the claim language and the specification, and would leave the boundaries of the
`
`“transistor array substrate” indefinite.
`
`1.
`
`The transistors are contained in the transistor array substrate
`
`By the plain terms of the claim, the transistor array substrate must contain a plurality of
`
`transistors for each pixel (i.e., an array of transistors). The claim language recites “a transistor
`
`array substrate which includes a plurality of pixels and comprises a plurality of transistors for each
`
`pixel, each of the transistors including a gate, a gate insulating film, a source, and a drain.” ’338
`
`at 24:15-18 (emphasis added). The term “comprises” means “including but not limited to.” See,
`
`e.g., Genentech, Inc. v. Chiron Corp., 112 F.3d 495, 501 (Fed. Cir. 1997).
`
`2
`
`

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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 7 of 40
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`But as Solas’s expert in the Eastern District of Texas litigation admitted, Solas’s proposal
`
`(“layered structure upon which or within which a transistor array is fabricated”) would permit the
`
`transistor array substrate to contain no transistors. See Ex. AA03 (Flasck Depo.) at 64:17-65:14.
`
`That is contrary to the claim language.
`
`Moreover, the specification explains that the transistors are contained within the transistor
`
`array substrate. See, e.g., ’338 at 10:45-47. Thus, based on the plain claim language, and the
`
`specification’s disclosures, the transistor array substrate contains an array of transistors. Solas’s
`
`contrary proposal is inconsistent with the intrinsic evidence.1
`
`2.
`
`The ’338 Patent defines which layers of an OLED display panel
`constitute the “transistor array substrate”
`
`The claim language and the specification make clear that the “transistor array substrate” is
`
`a layered structure composed of a bottom substrate layer through a topmost layer on whose upper
`
`surface pixel electrodes are formed, as Defendants propose.
`
`The claim language strongly supports Defendants’ proposal. After reciting “a transistor
`
`array substrate,” claim 1 proceeds to recite (1) that the interconnections “project from a surface of
`
`the transistor array substrate” and (2) “the pixel electrodes being arrayed along the
`
`interconnections between the interconnections on the surface of the transistor array substrate.” As
`
`Solas admits, the claim language provides that the pixel electrodes are “on the surface of the
`
`transistor array substrate.” AA04 at 3. This means that the “transistor array substrate” constitutes
`
`the layers up to but not including the pixel electrodes, as Defendants propose.
`
`1 Defendants note that in the E.D. Tex. litigation, the Court found that the specification’s references
`to a transistor array substrate containing an array of transistors did not justify including the
`requirement. See Ex. AA02 (Dkt. 99 in Solas OLED Ltd. v. Samsung Display Co., et al, Case No.
`2:19-cv-152 (E.D. Tex. April 17, 2020) at 14. Defendants respectfully submit that the claim
`language is decisive that the transistor array substrate contains the transistors, as shown above.
`
`3
`
`

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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 8 of 40
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`Moreover, before the Patent Trial and Appeal Board, Solas itself agreed that “transistor
`
`array substrate” in the ’338 patent should be construed as “layered structure including a bottom
`
`insulating substrate through a topmost insulating layer on whose surface the pixel electrodes are
`
`formed,” as Defendants propose. Ex. AA05 at 27-28.
`
`Consistent with the claim language and Solas’s position before the PTAB, the specification
`
`discloses that the transistor array substrate constitutes the layers up to (but not including) the pixel
`
`electrode. The specification expressly states that “[t]he layered structure from the insulating
`
`substrate 2 to the planarization film 33 is called a transistor array substrate 50.” ’338 at 10:45-47
`
`(emphasis added). See, e.g., Sinorgchem Co., Shandong v. Int’l Trade Comm’n, 511 F.3d 1132,
`
`1136 (Fed. Cir. 2007) (“[T]he word ‘is’ ... may signify that a patentee is serving as its own
`
`lexicographer.”) (citation and internal quotation marks omitted).
`
`Next, the specification explains that “[t]he plurality of sub-pixel electrodes 20a are arrayed
`
`in a matrix on the upper surface of the planarization film 33, i.e., the upper surface of the transistor
`
`array substrate 50.”2 ’338 at 11:50-53 (emphasis added). See Edwards Lifesciences LLC v. Cook
`
`Inc., 582 F.3d 1322, 1334 (Fed. Cir. 2009) (“the specification’s use of ‘i.e.’ signals an intent to
`
`define the word to which it refers”). This passage reiterates that the surface on which the pixel
`
`electrodes are formed constitutes the upper surface of the transistor array substrate.
`
`All the layers beneath the pixel electrode are part of the transistor array substrate, as
`
`illustrated in Figure 6 of the patent and as described through the specification. See, e.g., ’338 at
`
`2 The Court in the E.D. Tex. litigation found that the fact that this portion of the specification
`referred to “transistor array substrate 50,” favored “finding that this disclosure refers to a specific
`structure in a particular disclosed embodiment rather than to the meaning of ‘transistor array
`substrate’ in general.” Ex. AA02 at 14. The specification, however, does not disclose any
`“transistor array substrate” other than the “transistor array substrate 50” nor suggests that one
`would have a different top surface. Further, as discussed above, the other claim language of claim
`1 itself strongly supports Defendants’ reading.
`
`4
`
`

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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 9 of 40
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`8:21-23 (“The display panel 1 is formed by stacking various kinds of layers on the insulating
`
`substrate 2 which is optically transparent.”); id. at 10:45-47 (“The layered structure from the
`
`insulating substrate 2 to the planarization film 33 is called a transistor array substrate 50.”).
`
`Solas’s construction—“layered structure upon which or within which a transistor array is
`
`fabricated”—would leave indeterminate which layers are part of the transistor array substrate and
`
`which are not. Indeed, Solas’s expert in the Eastern District of Texas litigation acknowledged in
`
`deposition that, under Solas’s proposal, multiple different combinations of layers in a single device
`
`could alternatively be considered to be a “transistor array substrate.” Ex. AA03 (Flasck Dep. Tr.)
`
`at 69:3-11, 104:4-105:3. Under Solas’s proposal, there would not even be a basis to include within
`
`the “transistor array substrate” layers that the specification expressly identifies as portions of the
`
`transistor array substrate. For instance, planarization layer 33 is neither beneath the array of
`
`transistors nor a layer that contains transistors, and would fall outside the scope of the claims under
`
`Solas’s construction. Yet, the ’338 patent is explicit that planarization layer 33 is part of the
`
`claimed “transistor array substrate.” ’338 at 11:50-53.
`
`Thus, consistent with all of the intrinsic evidence, “transistor array substrate” should be
`
`construed as “a layered structure composed of a bottom substrate layer through a topmost layer on
`
`whose upper surface pixel electrodes are formed, which contains an array of transistors.”
`
`C.
`
`“project from a surface of the transistor array substrate” (claim 1)
`
`Plaintiff’s Proposal
`“extend beyond an outer surface of the
`transistor array substrate”
`
`Defendants’ Proposal
` “extend above the upper surface of the
`transistor array substrate”
`
`The parties’ dispute over this term concerns the boundary of the transistor array substrate
`
`from which the interconnections project. The disclosures of the ’338 Patent uniformly establish
`
`5
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`

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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 10 of 40
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`that the interconnections extend above the upper surface of the transistor array substrate, and not
`
`from a side or bottom surface of the transistor array substrate.
`
`The specification explains that the interconnections project from the upper surface of the
`
`transistor array substrate. The specification explains “[t]he common interconnection 91 is formed
`
`by electroplating and is therefore formed to be much thicker than the signal line Y, scan line X,
`
`and supply line Z and project upward from the surface of the planarization film 33.” ’338 at 10:54-
`
`58 (emphasis added). The specification then explains that “[t]he thickness of the select
`
`interconnection 89 and feed interconnection 90 is larger than the total thickness of the protective
`
`insulating film 32 and planarization film 33 so that the select interconnection 89 and feed
`
`interconnection 90 project upward from the upper surface of the planarization film 33,” id. at
`
`11:36-41 (emphasis added), which is the upper surface of the transistor array substrate, see, e.g.,
`
`id. at 10:49-50 (“the upper surface of the planarization film 33, i.e., the upper surface of the
`
`transistor array substrate 50”) (emphasis added); 11:50-52 (same); 10:45-47.
`
`As shown in annotated Figure 6 below, the interconnections (89, 90, and 91 shown in red)
`
`all extend above the upper surface (33 shown in yellow) of the transistor array substrate:
`
`6
`
`

`

`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 11 of 40
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`Defendants’ proposal further aligns with a stated purpose of
`
`the projecting
`
`interconnections, which the ’338 patent repeatedly explains is to “serve as partition walls to
`
`prevent leakage of an organic compound-containing solution.” ’338 at 6:24-30; see also id. at
`
`6:38-42. To serve as these partition walls, the interconnections must extend past the upper surface
`
`of the transistor array substrate. This is precisely what the specification describes and its Figures
`
`illustrate. In language that parallels the claim language, the specification explains that projecting
`
`interconnections extend above the upper surface of the transistor array substrate to prevent leakage
`
`of the organic electroluminescent compound: “[t]he thick select interconnection 89, feed
`
`interconnection 90, and common interconnection 91 whose tops are much higher than that of the
`
`insulating line 61 are formed between the sub-pixel electrodes 20a adjacent in the vertical direction
`
`to project [sic] respect to the surface of the transistor array substrate 50. Hence, the organic
`
`compound-containing solution applied to a sub-pixel electrode 20a is prevented from leaking to
`
`the sub-pixel electrode 20a adjacent in the vertical direction.” Id. at 12:62-13:3 (emphases added).
`
`Although the Court in the Eastern District of Texas litigation declined to include the
`
`“upper” portion of Defendants’ construction, stating that the term “upper” “lacks sufficiently clear
`
`meaning in the context of a “display panel” as claimed in . . . Claim 1,” Ex. AA02 at 18, the ’338
`
`Patent makes the meaning of “upper” surface clear relative to the surrounding elements, see, e.g.,
`
`10:54-58 & 11:36-41 (referring specifically to the “upper surface”). The upper surface is the
`
`contact between the transistor array substrate and the pixel electrodes.
`
`7
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`

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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 12 of 40
`
`II.
`
`U.S. Patent No. 7,499,042 (“’042 Patent”)
`
`A.
`
`’042 Patent Background
`
`The ’042 Patent is directed to an OLED
`
`display panel shown in Figure 1 (annotated right).
`
`The panel includes a matrix of pixel circuits P1,1 to
`
`Pm,n (each circuit in blue), controlled by a selection
`
`scan driver (orange) and a data driving circuit (red).
`
`’042 at 4:19-43, 4:59-5:24. The scan driver connects
`
`to rows of pixels circuits through selection scan lines
`
`X1-Xm (orange), with each line connecting to one row.
`
`Id. The data driving circuit similarly connects to
`
`columns of pixel circuits through current lines Y1-Yn
`
`(red), with each line connecting to one column. Id.
`
`As depicted in Figure 4 (annotated), each selection scan line is turned on and selects a
`
`corresponding row of pixels in the “selection period” TSE (blue) for that row. Id. at 4:33-38, 9:20-
`
`26. The selection period is divided into two sub-periods: (1) a reset sub-period TR (green), when
`
`a “reset voltage” VR
`
`is
`
`applied to the pixels of that
`
`row, followed by (2) a second
`
`sub-period (yellow) when a
`
`“designating current” Idata is
`
`applied. Id. at 11:50-57,
`
`13:10-18. Following the selection period is a “non-selection period” TNSE (red), when the selection
`
`scan line is turned off and unselects that row of pixels. Id. at 10:19-27.
`
`8
`
`

`

`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 13 of 40
`
`B.
`
`“selection period” (Claim 1)
`
`Solas’s Proposal
`“time period during which a plurality of
`pixel circuits is selected”
`
`HP’s Proposal
`“time duration in which a selected selection scan
`line is kept active”
`
`HP’s construction follows from the patent’s definition of “selection period” to mean a time
`
`duration when a “selection scan line” is selected, meaning it is “active” or turned on. It also
`
`clarifies that the selected “selection scan line” is “kept” active because, otherwise, a “selection
`
`period” could encompass periods when a “selection scan line” is not kept active and is actually
`
`turned off and unselected. Yet, by not including any notion of keeping the selection active, Solas’s
`
`proposal advances just such an expansive and contradictory understanding of “selection period”
`
`as encompassing periods when a line or circuit is inactive and not selected. Solas’s proposal also
`
`contradicts the specification, which uses another term, “non-selection period,” to refer to periods
`
`when a “selection scan line” is inactive. Moreover, by not tying the “selection period” to any
`
`“selection scan line,” Solas’s proposal disregards that the specification expressly defines a
`
`“selection period” in relation to the “selection scan line” for a row of pixel circuits, rather than just
`
`any “plurality of pixel circuits.”
`
`HP’s construction follows from the specification’s definition of a “selection period” as a
`
`time duration during which a given “selection scan line” is turned “ON”: “[a] period in which the
`
`selection scan driver 5 applies the ON voltage VON to the selection scan line Xi in the ith row and
`
`thereby selects the selection scan line Xi in the ith row is called a selection period TSE of the ith
`
`row.” Id. at 9:13-32. The specification provides this definition in connection with Figure 4
`
`(annotated below), which shows that the “selection period” TSE for each selection scan line X is
`
`the time that the line is set to VON (blue). Id. As also shown in Figure 4, the “selection period”
`
`for each scan line X1-Xm is divided into two sub-periods, between which the selection scan line is
`
`9
`
`

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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 14 of 40
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`kept active. In the first sub-period, known as the reset period TR (green), “the selection scan driver
`
`5 applies the ON voltage VON to the selection scan line Xi.” Id. at 13:10-18. In the second
`
`sub-period, a tone designating current IDATA is applied to the current lines (yellow). Id. at 13:55-
`
`64. Notably, “after the reset period TR in the selection period TSE of the ith row, the selection scan
`
`driver 5 keeps applying the ON voltage VON to the selection scan line Xi.” Id. A “selection period”
`
`thus refers to when a “selection scan line” for a row of pixel circuits is active and turned on.
`
`The specification precludes the possibility that the “selection period” for a row of pixel
`
`circuits could encompass a time duration when a corresponding “selection scan line” is inactive or
`
`off. First, as described above, the specification states that the circuit “keeps applying the ON
`
`voltage VON to the selection scan line Xi” between the two sub-periods of the “selection period.”
`
`Id. Second, the specification defines the time when “selection scan line” is inactive or “OFF”
`
`using another term, a “non-selection period”: “a period in which the selection scan driver 5 applies
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`the OFF voltage VOFF to the selection scan line Xi in the ith row and thereby keeps the selection
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`scan line Xi in the ith row unselected is called a non-selection period TNSE of the ith row.” Id. at
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`10
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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 15 of 40
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`9:49-57. In Figure 4 (above), the non-selection period TNSE (red) of every selection scan line X1
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`to Xm corresponds to when that line is set to VOFF.
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`Further, statements made in prosecution of a related foreign counterpart patent are relevant
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`to construing claims of a U.S. patent. E.g., Glaxo Grp. Ltd. v. Ranbaxy Pharm., Inc., 262 F.3d
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`1333, 1337 (Fed. Cir. 2001). During prosecution of a European counterpart to the ’042 Patent,
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`European Patent No. 1,714,266 (“EP ’266”), the applicants argued that a “selection scan line” has
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`to be kept active during the entire “selection period” to distinguish discontinuous selection periods
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`in prior art European Patent Application No. 1,372,136 (“EP ’136”).3
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`See Ex. BB01 at
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`DEFS_CC_0510-0511. As shown in its Figure 4 (annotated below), in EP ’136, each selection
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`scan line, SC1(Y1) and SC1(Y2), is selected and active in two separate periods T1 and T2 (blue)
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`in each frame period (yellow). Based on this disclosure, the applicants argued that EP ’136 “carries
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`out the reset and the writing process in different selection periods, while the present invention
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`carries out these processes in the same selection period.” Id.; Ex. BB02 at DEFS_CC_0997.
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`The applicants contrasted EP ’136 with the ’042 Patent, where “each selection[] scan line[]
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`is selected once and not twice in a frame period,” which leads to “significantly reduced” “power
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`consumption.” Id. Thus, the applicants relied on their alleged invention having one “selection
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`period,” during which the “selection scan line” is kept active, to distinguish prior art having two
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`discontinuous selection periods separated by a period when the selection scan line is inactive.
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`3The applicants submitted EP ’136 in an Information Disclosure Statement to the PTO during the
`’042 Patent prosecution, acknowledging its relevance to the ’042 Patent. See Ex. BB02 at
`DEFS_CC_0975, 0977.
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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 16 of 40
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`Solas’s proposal of “time period during which a plurality of pixel circuits is selected” is
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`incorrect for several reasons. First, it severs any connection between the “selection period” and
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`“selection scan line.” But as excerpted above, the specification expressly defines the “selection
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`period” in relation to whether a corresponding “selection scan line” is active or turned on. ’042 at
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`9:20-36. Second, by severing the connection, Solas’s proposal is overbroad and ambiguous as to
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`which “plurality of pixel circuits is selected.” In each “selection period,” a “selection scan line”
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`and corresponding row of pixel circuits is active and selected. Solas’s proposal, however, allows
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`the selection of any pixel circuits, regardless of their arrangement. But there is no enabling
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`disclosure for selecting a column, diagonal line, or any random grouping of pixel circuits during
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`any “selection period.” Third, by not including any notion of keeping the selection active during
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`the “selection period,” Solas’s proposal encompasses periods when the “selection scan line” is at
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`least temporarily inactive or not selected. Solas’s proposal that a “selection period” could mean a
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`duration when a line or circuit is un-selected contradicts both the plain meaning of “selection
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`period” and the specification’s usage of “non-selection period” to refer to such a duration.
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`C.
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`“sequentially selects said plurality of selection scan lines in each selection
`period” (Claim 1)
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`Solas’s Proposal
`Plain and ordinary
`meaning
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`HP’s Proposal
`“selects said plurality of selection scan lines one per each of a plurality
`of non-overlapping selection periods”
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`As discussed in Section II.A (’042 Patent Background) and with respect to Figure 1, the
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`’042 Patent discloses rows of selection scan lines, with each row selected during a corresponding
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`“selection period.” HP proposes to construe this “sequentially . . .” term to clarify that the
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`“selection periods” for different “selection scan lines” must be “non-overlapping” in time. This
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`follows from express statements made in the specification and the fundamental operation of OLED
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`circuits. Solas’s “plain and ordinary meaning” proposal fails because, as an initial matter, the
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`Case 6:19-cv-00537-ADA Document 47 Filed 06/25/20 Page 17 of 40
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`disputed term is a lengthy, technical phrase lacking any plain and ordinary meaning. It also fails
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`to the extent Solas contends that “selection periods” for different selection scan lines can overlap.
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`The ’042 Patent specification is clear: “the selection periods TSE of the selection scan lines
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`X1 to Xm do not overlap each other.” ’042 at 9:29-31. The specification explains why this
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`statement is true. It states that each selection scan line is controlled by the same “selection scan
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`driver,” which the patent described as a “shift register” that “individually applies, to the selection
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`scan lines X1 to Xm, a high-
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`level (ON-level) ON voltage
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`VON,” as shown in Figure 4
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`(annotated). Id. at 9:13-19.
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`This figure also shows that
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`the “selection period” TSE
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`for any one selection scan
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`line (blue) occurs only during the non-selection periods TNSE of the other selection scan lines (red).
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`The specification confirms this, stating: “while applying the ON voltage VON to the selection scan
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`line Xi, the selection scan driver 5 applies the OFF voltage VOFF to the other selection scan lines
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`X1 to Xm (except for the selection scan line Xi).