Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 1 of 47
`
` Exhibit 3
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 2 of 47
`Case 6:19'CV'00537'ADA D"wml‘lllflllllfllllflllllllllllllll'fllfilllllflllllllilllllllflll’lll||||||||
`
`US007573068B2
`
`(12) United States Patent
`US 7,573,068 B2
`Shimoda et al.
`(45) Date of Patent:
`Aug. 11,2009
`
`(10) Patent No.:
`
`(54) TRANSISTOR ARRAY SUBSTRATE AND
`DISPLAY PANEL
`
`(75)
`
`Inventors: Satoru Shimoda, Fussa (JP); Tomoyuki
`Shirasaki, Higashiyamato (JP); Jun
`Ogura, Fussa (JP); Minoru Kumagai,
`Tokyo (JP)
`
`(73)
`
`Assignee:
`
`Casio Computer Co., Ltd., Tokyo (JP)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 769 days.
`
`(21)
`
`Appl. No.:
`
`11/232,368
`
`(22)
`
`Filed:
`
`Sep. 21, 2005
`
`(65)
`
`(30)
`
`Prior Publication Data
`
`US 2006/0098521 A1
`
`May 11, 2006
`
`Foreign Application Priority Data
`
`Sep. 21, 2004
`Sep. 21, 2004
`Sep. 16,2005
`
`(JP)
`(JP)
`(JP)
`
`............................. 2004—273532
`..... 2004-273580
`
`............................. 2005-269434
`
`Int. Cl.
`
`(51)
`
`(2006.01)
`H01L 33/00
`(2006.01)
`HOIL 27/32
`US. Cl.
`.................. 257/72; 257/208; 257/E33055
`Field of Classification Search ................... 257/59,
`257/72, 79, 81, 83, E33064, E33077, E27.131,
`257/E27.132, 208, E33055; 313/500, 505;
`349/42, 139, 149, 73, 74; 345/44, 45, 87792
`See application file for complete search history.
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`(52)
`(58)
`
`(56)
`
`6,864,639 B2
`6,933,533 B2
`7,317,429 B2
`2004/0108978 A1*
`
`3/2005 Ito
`8/2005 Yamazaki et a1.
`1/2008 Shirasaki et a1.
`6/2004 Matsueda et a1.
`
`............. 345/76
`
`FOREIGN PATENT DOCUMENTS
`
`CN
`JP
`
`1360350 A
`8-330600 A
`
`7/2002
`12/1996
`
`(Continued)
`OTHER PUBLICATIONS
`
`A Japanese Office Action (and English translation thereof) dated Apr.
`30, 2008, issued in a counterpart Japanese Application.
`
`Primary ExamineriDavienne Monbleau
`Assistant Examinerishweta Mulcare
`
`(74) Attorney, Agent, or FirmiFrishauf, Holtz, Goodman &
`Chick, PC.
`
`(57)
`
`ABSTRACT
`
`A transistor array substrate includes a plurality of driving
`transistors which are arrayed in a matrix on a substrate. The
`driving transistor has a gate, a source, a drain, and a gate
`insulating film inserted between the gate, and the source and
`drain. A plurality of signal lines are patterned together with
`the gates of the driving transistors and arrayed to run in a
`predetermined direction on the substrate. A plurality of sup-
`ply lines are patterned together with the sources and drains of
`the driving transistors and arrayed to cross the signal lines via
`the gate insulating film. The supply line is electrically con-
`nected to one of the source and the drain of the driving
`transistor. A plurality of feed interconnections are formed on
`the supply lines along the supply lines, respectively.
`
`6,762,564 B2
`
`7/2004 Noguchi et a1.
`
`17 Claims, 27 Drawing Sheets
`
`XI
`
`,
`2
`
`
`
`so
`E
`
`3,
`
`xYI
`
`
`
`1/91
`
`
`
`I:E
`17
`
`
`
`
`
`22
`
`22d
`229 l:/
`23d
`223
`a P239
`24
`235
`
`23
`
`21g
`
`l_A
`
`——
`21s / 21d
`21
`
`24A
`
`243
`
`A
`
`is
`20
`
`34
`PM
`
`20a E
`20::
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 3 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 3 of 47
`
`US 7,573,068 B2
`
`Page 2
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`
`2000349298 A
`2003-133079 A
`2003-195810 A
`
`12/2000
`5/2003
`7/2003
`
`2003-330387 A
`JP
`2004-101948 A
`JP
`W0 W0 2004/019314 A1
`
`11/2003
`4/2004
`3/2004
`
`* cited by examiner
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 4 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 4 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 1 0127
`
`US 7,573,068 B2
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 5 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 5 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 2 0f 27
`
`US 7,573,068 B2
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 6 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 6 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 3 0f 27
`
`US 7,573,068 B2
`
`
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 7 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 7 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 4 0f 27
`
`US 7,573,068 B2
`
`21d
`
`21s
`
`24B
`
`21
`
`24
`
`20a
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 8 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 8 of 47
`
`U.S. Patent
`
`Aug. 11,2009
`
`Sheet50f27
`
`US 7,573,068 B2
`
`!““
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`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 9 of 47
`
`US. Patent
`
`Au .11 2009
`
`Sheet6 0f27
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`w58._>
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`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 10 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 10 of 47
`
`U.S. Patent
`
`Aug. 11,2009
`
`Sheet7
`
`0f27
`
`US 7,573,068 B2
`
`
`
`(6
`
`O N
`
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`
`Nmm5umum
`
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`
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`§§‘\\ifA‘gwuufldwggflwgflmfiz.:/.m
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`
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`
`
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`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 11 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 11 of 47
`
`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 8 of 27
`
`US 7,573,068 B2
`
`/////
`
`A‘A
`
`om
`
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`
`
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`ydruwlpfflflfkl'.........h‘...b1.h1..u‘.li...i..‘.fifi.firfgrfi
`&&§R§A§§k
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`
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`_Nem<¢NmvmN‘‘<.3“V«w«33‘R»$§§§§
`
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`
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`
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`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 12 of 47
`
`
`
`gal/Wfi‘ifigiiigil’’Hflg“"i““““i“
`Fifi/fflfflfflfflw"
`
`FIG.9
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 13 of 47
`
`229
`
`
`I/”_.,./dSm1.1.222
`
`////////A
`
`
`
`FIG.1O
`
`'
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 14 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 14 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 11 0127
`
`US 7,573,068 B2
`
`94
`
`21d
`
`213
`
`21g
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 15 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 15 of 47
`
`U.S. Patent
`
`Aug. 11,2009
`
`Sheet120f27
`
`US 7,573,068 B2
`
`91a
`
`91 91 91 91 91 91 91
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`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 16 of 47
`Case 6:19-Cv-00537-ADA Document 1-3 Filed 09/12/19 Page 16 Of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 13 0127
`
`US 7,573,068 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi’1 TO Pi, n
`
`LIGHT EMISSION
`LIGHT EMISSION
`PERIOD OF
`PERIOD OF PIXEL
`PRECEDING FRAME!
`! CIRCUITS PL1TO Pi, n
`
`
`
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`
`AND SUPPLY LINE Zi
`PIXEL CIRCUIT Pi’j
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`
`LIGHT EMISSION
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT PM"
`
`VOLTAGE LEVEL
`OF SCAN LINE xm
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINE Zi+1
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT PMJ
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi+1,1 T0 Pi+1, n
`
`
`
`
`
`LIGHT EMISSION
`:
`PERIOD OF PIXEL
`ICIRCUITS Pi+1,1 T0 Pi+1,n
`
`LIGHT EMISSION
`
`FIG.13
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 17 of 47
`Case 6:19-CV-00537-ADA Document 1-3 Filed 09/12/19 Page 17 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 14 0127
`
`US 7,573,068 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi, 1 TO PI. n
`
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME
`LIGHT EMISSION
`OF PIXEL CIRCUITS
`PERIOD OF PIXEL
`
`IPi71TO Pi, n I CIRCUITS Pi’1TO Pi, n
`
`
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINES
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`
`21 To zm
`PIXEL CIRCUIT PLI
`
`,
`I
`
`I LIGHT
`EMISSION
`
`LIGHT
`EMISSION
`
`LIGHT
`EMISSION
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`
`OF PIXEL CIRCUIT Pi’j
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi.”
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT PM;
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT P5445]-
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi+1,1T0 PI+1,n
`I<—>I
`
`‘
`:
`I
`I LIGHT EMISSION
`i 35339305 PIXEI'IO
`‘
`1+1
`,‘f" 1
`”—4——
`
`LIGHT
`
`I
`EMISSION
`
`
`LIGHT EMISSION I
`anSESII‘I’B 95mg
`0F PIXEL CIRCUITS j
`PI+1,1 T0 Pi+1, n
`4
`
`FIG.14
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 18 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 18 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 15 0127
`
`US 7,573,068 B2
`
`Id [A]
`
`
`
`
`
`
`2
`
`3 ‘4 5
`
`6
`
`7
`
`8 9101112131415
`
`Vds[V]
`
`|ds_max
`
`__._.— lds_mid
`................ |e|
`
`_ .....— Vpo
`
`_......._ Vds=Vgs=Vpo+Vth
`
`FIG.15
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 19 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 19 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 16 of 27
`
`US 7,573,068 B2
`
`32-INCH PANEL
`
`MAXIMUM
`VOLTAGE
`DROP [v1
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`4p/S [S52/cm]
`
`3 610
`
`FIG.16
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 20 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 20 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 17 0127
`
`US 7,573,068 B2
`
`1.o><1o7
`
`
`
`
`
`
`32-INCH PANEL
`
`
`
`
`
`
`
`
`
`1.o><1o6
`
`
`
`
`
`
`
`
`CURRENT
`DENSITY
`[A/cmz]
`
`5
`
`1-0><10
`
`1.0x1o4
`
`
`
`
`
`
`
`--—------=-:—-:‘-------—-
`
`
`
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`=--------—----—;=-------
`
`
`
`
`
`
`o
`
`1.0x1o3
`
`
`
`250
`
`100
`
`150
`
`200
`
`SECTIONAL AREA 3 [m2]
`
`FIG.17
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 21 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 21 of 47
`
`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 18 0f 27
`
`US 7,573,068 B2
`
`MAXIMUM
`VOLTAGE
`DROP {v1
`
`40-INCH PANEL
`
`
`
`|||141llllll|||||
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`
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`
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`
`
`1
`
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`
`3
`
`4
`
`5
`
`6
`
`7
`
`8
`
`9
`
`1 0
`
`p/S [SB/cm]
`
`F=I(Ei.‘|13
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 22 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 22 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 19 of 27
`
`US 7,573,068 B2
`
`1 .0 x1 07 =========================
`
`40-INCH PANEL
`
`CURRENT
`DENSITY
`[A/cm2]
`
`5
`
`1-0X10
`
`
`
`‘_—-———
`-———-——
`-==========--“‘----
`---------------——__-
`
`1.0x", IIIIII_!!!iiI§!!!IIIIIIII
`
`0
`
`50
`
`100
`
`150
`
`200
`
`250
`
`SECTIONAL AREA S [umz]
`
`FIG.19
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 23 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 23 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 20 0f 27
`
`US 7,573,068 B2
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 24 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 24 of 47
`
`US. Patent
`
`Aug. 11,2009
`
`Sheet 21 0f 27
`
`US 7,573,068 B2
`
`C2
`
`Zi
`
`Y'
`
`22d
`/22
`
`229
`
`22s
`
`21 g
`
`C3
`
`FIG.21
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 25 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 25 of 47
`
`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 22 of 27
`
`US 7,573,068 B2
`
`\\\\\
`/fimnmvmummmwmummwhmmmmthhmwmmmwmkwmmmfirmwfim‘mmmmmmhMMMNmmmmm-mwm
`
`FIG.22
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 26 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 26 of 47
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`US. Patent
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`Aug. 11,2009
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`Sheet 23 0f 27
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`US 7,573,068 B2
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`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 27 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 27 of 47
`
`U.S. Patent
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`Aug. 11, 2009
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`Sheet 24 of 27
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`US 7,573,068 B2
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`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 28 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 28 of 47
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`U.S. Patent
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`Aug. 11, 2009
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`Sheet 25 of 27
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`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 29 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 29 of 47
`
`U.S. Patent
`
`Aug. 11, 2009
`
`Sheet 26 of 27
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`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 30 of 47
`Case 6:19-Cv-00537-ADA Document 1—3 Filed 09/12/19 Page 30 of 47
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`US. Patent
`
`Aug. 11,2009
`
`Sheet 27 0f 27
`
`US 7,573,068 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi, 1 TO Pi, n
`
`LIGHT EMISSION
`PERIOD OF
`.
`PRECEDING FRAME
`LIGHT EMISSION
`0F PIXEL CIRCUITS
`PERIOD OF PIXEL
`
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`
`VOLTAGE LEVEL
`OF SCAN LINE Xi
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`INTERCONNECTION 90
`AND SUPPLY LINES
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`TRANSISTOR 23 0F
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`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 31 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 31 of 47
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`US 7,573,068 B2
`
`1
`TRANSISTOR ARRAY SUBSTRATE AND
`DISPLAY PANEL
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is based upon and claims the benefit of
`priority from prior Japanese Patent Applications No. 2004-
`273532, filed Sep. 21, 2004; No. 2004-273580, filed Sep. 21,
`2004; and No. 2005-269434, filed Sep. 16, 2005, the entire
`contents of all of which are incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a transistor array substrate
`having a plurality of transistors and, more particularly, to a
`display panel using light-emitting elements which cause self
`emission when a current is supplied by the transistor array
`substrate.
`
`2. Description of the Related Art
`Organic electroluminescent display panels can roughly be
`classified into passive driving types and active matrix driving
`types. Organic electroluminescent display panels of active
`matrix driving type are more excellent than those of passive
`driving type because of high contrast and high resolution. In
`a conventional organic electroluminescent display panel of
`active matrix display type described in, e. g., Jpn. Pat. Appln.
`KOKAI Publication No. 8-330600, an organic electrolumi-
`nescent element (to be referred to as an organic EL element
`hereinafter), a driving transistor which supplies a current to
`the organic EL element when a voltage signal corresponding
`to image data is applied to the gate of the transistor, and a
`switching transistor which performs switching to supply the
`voltage signal corresponding to image data to the gate of the
`driving transistor are arranged for each pixel. In this display
`panel, when a predetermined scan line is selected, the switch-
`ing transistor is turned on. At this time, a voltage of level
`representing the luminance is applied to the gate of the driv-
`ing transistor through a signal line. Thus, the driving transis-
`tor is tumed on. A driving current having a magnitude corre-
`sponding to the level of the gate voltage is supplied from the
`power supply to the organic EL element through the source-
`to-drain path of the driving transistor. Consequently, the EL
`element emits light at a luminance corresponding to the mag-
`nitude of the current. During the period from the end of scan
`line selection to the next scan line selection, the level of the
`gate voltage ofthe driving transistor is continuously held even
`after the switching transistor is turned off. Hence, the organic
`EL element keeps emitting light at a luminance correspond-
`ing to the magnitude of the driving current corresponding to
`the voltage.
`To drive the organic electroluminescent display panel, a
`driving circuit is provided around the display panel to apply a
`voltage to the scan lines, signal lines, and power supply lines
`laid on the display panel.
`In the conventional organic electroluminescent display
`panel of active matrix driving type, interconnections such as
`a power supply line to supply a current to an organic EL
`element are patterned simultaneously in the thin-film transis-
`tor patterning step by using the material of a thin-film tran-
`sistor such as a switching transistor or driving transistor.
`More specifically, in manufacturing the display panel, a con-
`ductive thin film as a prospective electrode of a thin-film
`transistor is subjected to photolithography and etching to
`form the electrode of a thin-film transistor from the conduc-
`tive thin film. At the same time, an interconnection connected
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`to the electrode is also formed. For this reason, when the
`interconnection is formed from the conductive thin film, the
`thickness of the interconnection equals that of the thin-film
`transistor.
`
`The electrode ofthe thin-film transistor is designed assum-
`ing that it functions as a transistor. In other words, the elec-
`trode is not designed assuming that it supplies a current to a
`light-emitting element. Hence, the thin-film transistor is thin
`literally. If a current is supplied from the interconnection to a
`plurality of light-emitting elements, a voltage drop occurs, or
`the current flow through the interconnection delays due to the
`electrical resistance of the interconnection. To suppress the
`voltage drop or interconnection delay, the resistance of the
`interconnection is preferably low. If the resistance of the
`interconnection is reduced by making a metal layer serving as
`the source and drain of the transistor or a metal layer serving
`as the gate electrode thick, or patterning the metal layers
`considerably wide to sufficiently flow the current through the
`metal
`layers,
`the overlap area of the interconnection on
`another interconnection or conductor when viewed from the
`
`upper side increases, and a parasitic capacitance is generated
`between them. This retards the flow of the current. Altema-
`
`tively, in a so-called bottom emission structure which emits
`EL light from the transistor array substrate side, light emitted
`from the EL elements is shielded by the interconnections,
`resulting in a decrease in opening ratio, i.e., the ratio of the
`light emission area. If the gate electrode of the thin-film
`transistor is made thick to lower the resistance, a planariza-
`tion film (corresponding to a gate insulating film when the
`thin-film transistor has, e.g., an inverted stagger structure) to
`eliminate the step of the gate electrode must also be formed
`thick. This may lead to a large change in transistor character-
`istic. When the source and drain are formed thick, the etching
`accuracy of the source and drain degrades. This may also
`adversely affect the transistor characteristic.
`
`BRIEF SUMMARY OF THE INVENTION
`
`It is an object ofthe present invention to satisfactorily drive
`a light-emitting element while suppressing any voltage drop
`and signal delay.
`A transistor array substrate according to a first aspect ofthe
`present invention comprises:
`a substrate;
`a plurality of driving transistors which are arrayed in a
`matrix on the substrate, each of the driving transistors having
`a gate, a source, a drain, and a gate insulating film inserted
`between the gate, and the source and drain;
`a plurality of signal lines which are patterned together with
`the gates of the plurality of driving transistors and arrayed to
`run in a predetermined direction on the substrate;
`a plurality of supply lines which are patterned together
`with the sources and drains of the plurality of driving transis-
`tors and arrayed to cross the plurality of signal lines via the
`gate insulating film, each ofthe supply lines being electrically
`connected to one of the source and the drain of the driving
`transistor; and
`a plurality of feed interconnections which are formed on
`the plurality of supply lines along the plurality of supply lines,
`respectively.
`Preferably, a substrate according to claim 1, further com-
`prising a plurality of scan lines which are patterned together
`with the sources and drains of the plurality of driving transis-
`tors and arrayed to cross the plurality of supply lines via the
`gate insulating film.
`Preferably, a substrate according to claim 2, which further
`comprises a plurality of switch transistors which are arrayed
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 32 of 47
`Case 6:19-cv-00537-ADA Document 1—3 Filed 09/12/19 Page 32 of 47
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`US 7,573,068 B2
`
`3
`in a matrix on the substrate, each of the switch transistors
`having the gate insulating film inserted between a gate and a
`source and drain, and
`in which one ofthe source and drain of each ofthe plurality
`of switch transistors is electrically connected to the other of
`the source and drain of a corresponding one ofthe plurality of
`driving transistors,
`the gate of each of the plurality of switch transistors is
`electrically connected to the scan line through a contact hole
`formed in the gate insulating film, and
`the other of the source and drain of each of the plurality of
`switch transistors is electrically connected to the signal line
`through a contact hole formed in the gate insulating film.
`Preferably, a substrate according to claim 2, which further
`comprises a plurality of holding transistors which are arrayed
`in a matrix on the substrate, each of the holding transistors
`having the gate insulating film inserted between a gate and a
`source and drain, and
`in which one ofthe source and drain of each ofthe plurality
`ofholding transistors is electrically connected to the gate of a
`corresponding one of the plurality of driving transistors
`through a contact hole formed in the gate insulating film,
`the other of the source and drain of each of the plurality of
`holding transistors is electrically connected to one of the
`supply line and the scan line, and
`the gate of each of the plurality of holding transistors is
`electrically connected to the scan line through a contact hole
`formed in the gate insulating film.
`A display panel according to a second aspect of the present
`invention is a display panel comprising:
`a substrate;
`a plurality of driving transistors which are arrayed in a
`matrix on the substrate, each of the driving transistors having
`a gate, a source, a drain, and a gate insulating film inserted
`between the gate, and the source and drain;
`a plurality of signal lines which are patterned together with
`the gates of the plurality of driving transistors and arrayed to
`run in a predetermined direction on the substrate;
`a plurality of supply lines which are patterned together
`with the sources and drains of the plurality of driving transis-
`tors and arrayed to cross the plurality of signal lines via the
`gate insulating film, each ofthe supply lines being electrically
`connected to one of the source and the drain of the driving
`transistor; and
`a plurality of feed interconnections which are connected to
`the plurality of supply lines along the plurality of supply lines;
`a plurality of pixel electrodes each of which is electrically
`connected to the other of the source and the drain of each of
`
`the plurality of driving transistors;
`a plurality of light-emitting layers which are formed on the
`plurality of pixel electrodes, respectively; and
`a counter electrode which covers the plurality of light-
`emitting layers.
`Preferably, a panel according to claim 13, further compris-
`ing a plurality of scan lines which are patterned together with
`the sources and drains of the plurality of driving transistors
`and arrayed to cross the plurality of supply lines via the gate
`insulating film.
`According to this aspect, the signal lines are patterned
`together with the gates of the driving transistors. However,
`since the feed interconnections are stacked on the supply
`lines, the feed interconnections are formed separately for the
`drains, sources, and gates of the driving transistors. For this
`reason, the feed interconnection can be made thick without
`increasing its width, and the resistance of the feed intercon-
`nection can be reduced. Hence, even when a signal is output
`
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`to the driving transistor and pixel electrode through the feed
`interconnection, the voltage drop and signal delay can be
`suppressed.
`When the feed interconnections are to be formed by elec-
`troplating, the supply lines are formed on the signal lines.
`When the structure is dipped in a plating solution while a
`voltage is applied to the supply lines in the manufacturing
`step ofthe transistor array substrate and the display panel, the
`feed interconnections can be grown on the supply lines.
`According to this aspect, since the feed interconnections
`can be made thick, the resistance of the feed interconnections
`can be reduced. When the resistance of the feed interconnec-
`
`tions decreases, the signal delay and voltage drop can be
`suppressed.
`A display panel manufacturing method according to a dis-
`play panel manufacturing method according to a fourth
`aspect of the present invention comprises; patterning a plu-
`rality of pixel electrodes on a panel to be arrayed in a matrix;
`forming an interconnection made of metal between the pixel
`electrodes; coating a surface of the interconnection with a
`liquid repellent conductive layer; and forming an organic
`compound layer by applying an organic compound-contain-
`ing solution to the electrode.
`A thick interconnection can suppress the voltage drop and
`can also be used as a partition wall in forming an organic
`compound-containing solution. Since the liquid repellent
`conductive layer exhibits liquid repellency, an organic com-
`pound layer can satisfactorily be patterned. A liquid repellent
`conductive layer containing, e.g., a triazine compound can
`selectively be formed on a metal surface so as to exhibit liquid
`repellency but cannot be formed on the surface ofan insulator
`or a metal oxide to exhibit liquid repellency. In addition, the
`liquid repellent conductive layer is formed on the metal sur-
`face very thin. Hence, the electrical conductivity on the metal
`surface is not lost.
`
`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`
`FIG. 1 is a view showing the circuit arrangement of an EL
`display panel together with an insulating substrate;
`FIG. 2 is an equivalent circuit diagram of a pixel circuit of
`the EL display panel;
`FIG. 3 is a plan view showing the electrode of the pixel
`circuit of the EL display panel;
`FIG. 4 is a plan view showing the electrode of the pixel
`circuit of the EL display panel;
`FIG. 5 is a sectional view taken along a line V—V in FIG. 3;
`FIG. 6 is a sectional view taken along a line VI-VI in FIG.
`
`3;
`
`3;
`
`FIG. 7 is a sectional view taken along a line VII-VII in FIG.
`
`FIG. 8 is a sectional view taken along a line VIII-VIII in
`FIG. 3;
`FIG. 9 is a plan view showing a state wherein a gate layer
`is patterned;
`FIG. 10 is a plan view showing a state wherein a drain layer
`is patterned;
`FIG. 11 is a plan view showing a state wherein the drain
`layer is superposed on the patterned gate layer;
`FIG. 12 is a schematic plan view showing the layout of an
`organic EL layer of the EL display panel;
`FIG. 13 is a timing chart for explaining a driving method of
`the EL display panel;
`FIG. 14 is a timing chart for explaining another driving
`method of the EL display panel;
`
`

`

`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 33 of 47
`Case 6:19-cv-00537-ADA Document 1-3 Filed 09/12/19 Page 33 of 47
`
`US 7,573,068 B2
`
`5
`FIG. 15 is a graph showing the current vs. voltage charac-
`teristic of the driving transistor and organic EL element of
`each pixel circuit;
`FIG. 16 is a graph showing the correlation between the
`maximum voltage drop and the interconnection resistivity
`p/sectional area S of the feed interconnection and common
`interconnection of a 32-inch EL display panel;
`FIG. 17 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec-
`tion and common interconnection of the 32-inch EL display
`panel;
`FIG. 18 is a graph showing the correlation between the
`maximum voltage drop and the interconnection resistivity
`p/sectional area S of the feed interconnection and common
`interconnection of a 40-inch EL display panel 1;
`FIG. 19 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec-
`tion and common interconnection of the 40-inch EL display
`panel;
`FIG. 20 is a view showing the circuit arrangement of an EL
`display panel together with an insulating substrate;
`FIG. 21 is an equivalent circuit diagram of a pixel circuit of
`the EL display panel;
`FIG. 22 is a plan view showing the electrodes of pixel
`circuits Pl.,1. and Pia].+1 of the EL display panel;
`FIG. 23 is a sectional view taken along a plane perpendicu-
`lar to the channel width of a driving transistor;
`FIG. 24 is a sectional view taken along a line XXIV-XXIV
`in FIG. 22;
`FIG. 25 is a sectional view taken along a line XXV-XXV in
`FIG. 22;
`FIG. 26 is a schematic view showing the coating structure
`of a liquid repellent conductive film;
`FIG. 27 is a schematic plan view showing the layout of the
`organic EL layers of the EL display panel; and
`FIG. 28 is a timing chart for explaining the operation of the
`EL display panel.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`First Embodiment
`
`The best mode for carrying out the present invention will be
`described below with reference to the accompanying draw-
`ing. Various kinds of limitations which are technically pref-
`erable in carrying out the present invention are added to the
`embodiments to be described below. However, the spirit and
`scope ofthe present invention are not limited to the following
`embodiments and illustrated examples.
`
`[Overall Arrangement of EL Display Panel]
`FIG. 1 is a schematic view showing an EL display panel 1
`of active matrix driving type. As shown in FIG. 1, the EL
`display panel 1 comprises an insulating substrate 2, n (a
`plurality of) signal linesY1 to Y", m (a plurality of) scan lines
`X 1 to Xm, m (a plurality of) supply lines Z 1 to Zm, (m><n) pixel
`circuits PM to Pman, a plurality of feed interconnections 90,
`and common interconnections 91. The insulating substrate 2
`is optica