Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 1 of 29
`
` Exhibit 2
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 2 of 29
`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 2 of 29
`
`US007446338B2
`
`(12) United States Patent
`Shirasaki et a].
`
`(10) Patent N0.:
`(45) Date of Patent:
`
`US 7,446,338 132
`Nov. 4, 2008
`
`(54) DISPLAY PANEL
`
`(75)
`
`Inventors: Tomoyuki Shirasaki, Higashiyamato
`(JP); Tsuyoshi Ozaki, Fuchu (JP); Jun
`Ogura, Fussa (JP)
`
`(73)
`
`Assignee: Casio Computer Co., Ltd., Tokyo (JP)
`
`2003/0146693 A1
`
`8/2003 Ishihara et al.
`
`2003/0151355 A1
`
`8/2003 Hosokawa
`
`2003/0168992 A1
`2003/0193056 A1
`2004/0003939 A1
`
`9/2003 Noguchi et a1.
`10/2003 Takayarna et a1.
`1/2004 Nishi et al.
`
`2004/0160170 A1
`
`8/2004 Sato et al.
`
`2004/0165003 A1
`
`8/2004 Shirasaki
`
`2004/0256617 A1
`
`12/2004 Yamada et a1.
`
`(’k)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 86 days.
`
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`(21)
`
`Appl. N0.: 11/235,579
`
`(22)
`
`Ffled:
`
`Sep.26,2005
`
`CN
`
`1434668 A
`
`8/2003
`
`(Continued)
`
`OTHER PUBLICATIONS
`
`(65)
`
`Prior Publication Data
`
`US 2006/0066535 A1
`
`Mar. 30, 2006
`
`Related U.S. Appl. No. 11/235,605, filed Sep. 26, 2005; Inventors:
`Satoru Shimoda et a1; Title: Display Panel.
`
`(30)
`
`Foreign Application Priority Data
`
`Sep.29,2004
`
`(JP)
`
`............................. 2004-283 824
`
`(51)
`
`Int. Cl.
`HOIL 29/04
`
`(2006.01)
`
`(52) US. Cl.
`
`.............................. 257/72; 257/40; 257/79
`
`(58) Field of Classification Search ................... 257/40,
`257/72, 79
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`5,684,365 A
`6,297,589 B1
`6,717,357 B2
`6,839,057 B2
`7,358,529 B2
`
`11/1997 Tang et a1.
`10/2001 Miyaguchi et a1.
`4/2004 Okuyarna et a1.
`1/2005 Iguchi
`4/2008 Childs et 3.1.
`
`7,402,948 B2
`
`7/2008 Yamazakj et a1.
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`2003/ 0047730 A1
`
`3/2003 Konuma
`
`2003/0137325 A1
`
`7/2003 Yamazaki et a1.
`
`4
`r—H
`
`4
`’__‘
`
`(Continued)
`
`Primary Examiner—Long Pham
`(74) Attorney, Agent, or Firm—Frishauf, Holtz, Goodman &
`Chick, PC.
`
`(57)
`
`ABSTRACT
`
`A display panel includes a transistor array substrate which
`has a plurality of pixels and is formed by providing a plurality
`of transistors for each pixel, each of the transistor having a
`gate, a gate insulating film, a source, and a drain. A plurality
`of interconnections are formed to project to a surface of the
`transistor array substrate and arrayed in parallel to each other.
`A plurality of pixel electrodes are provided for each pixel and
`arrayed between the interconnections on the surface of the
`transistor array substrate along the interconnections. Each of
`a plurality of light-emitting layers is formed on each pixel
`electrode. A counter electrode is stacked on the light-emitting
`layer.
`
`22 Claims, 13 Drawing Sheets
`
`Yg Yb Yr
`
`90
`
`Yg Yb Yr
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`20
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`W 238 239 03
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`Pb
`w
`.111] x
`—'—--'-----l--.----"---'-'~
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`‘1.“x‘11m““‘1‘m‘“a
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`\"A‘ll’4ru'A'ml'l/w.“
`135,);it?»wmw%\\\\\m“.W)3fi,\\..-
`mg"x1141
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`
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`......
`
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`
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`32
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`21
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`X
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 3 of 29
`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 3 of 29
`
`US 7,446,338 B2
`
`Page 2
`
`US. PATENT DOCUMENTS
`
`2005/0062409 A1
`2005/0073264 A1
`2005/0088086 A1
`2005/0258741 A1
`2006/0066219 A1
`
`3/2005 Yamazaki et a1.
`4/2005 Matsumoto
`4/2005 Park et a1.
`11/2005 Kim et a1.
`3/2006 Shimoda et a1.
`
`FOREIGN PATENT DOCUMENTS
`
`KR
`
`KR
`TW
`TW
`Tw
`TW
`WO
`
`WO
`
`2002-0000875 A
`
`10-2004-0051611 A
`591574 A
`521336 A
`584324 A
`594628 A
`WO 03/079441 A1
`
`2004/019314 Al
`
`1/2002
`
`6/2004
`5/2002
`2/2003
`4/2004
`6/2004
`9/2003
`
`3/2004
`
`CN
`EP
`EP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`JP
`
`1437177 A
`1 331 666 A2
`1 349 208 Al
`8-330600 A
`2002-1950053 A
`2002-3 52963 A
`2003-076327 A
`2003-186420 A
`2003 -288994 A
`2003 -3 17971 A
`2004-258172 A
`
`8/2003
`7/2003
`10/2003
`12/1996
`7/2001
`12/2002
`3/2003
`7/2003
`10/2003
`11/2003
`9/2004
`
`OTHER PUBLICATIONS
`Japanese Office Action (and English translation thereof) dated Apr.
`30, 2008, issued in a counterpart Japanese Application.
`Chinese Office Action (and English translation thereof) dated Jun. 6,
`2008, issued in a counterpart Chinese Application.
`Chinese Office Action (and English translation thereof) dated Jun. 6,
`2008, issued in related U.S. Appl. No. 11/235,605 in counterpart
`Chinese Application No. 2005800156930.
`Japanese Office Action (and English translation thereof) dated Jun.
`10, 2008, issued in related U.S. App1.No. 11/235,605 in counterpart
`Japanese Application No. 2004-283963.
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 4 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 1 of 13
`
`US 7,446,338 B2
`
`4
`
`Y9 Yb Yr
`
`90
`
`2
`
`4
`
`Yg Yb Yr
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 5 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 2 of 13
`
`US 7,446,338 B2
`
`QXi
`
`89
`
`22d
`
`223
`
`23d
`
`24
`
`23s
`
`
`
`91
`
`FIG.2
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 6 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 3 0f 13
`
`US 7,446,338 B2
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 7 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 4 of 13
`
`US 7,446,338 B2
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 8 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 5 0f 13
`
`US 7,446,338 B2
`
`
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 9 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 6 of 13
`
`US 7,446,338 B2
`
`P
`
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`
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`
`
`
`
`i‘fii‘k,ERE§§.E.!Rfih-'§A:
`__‘3“,3’u“«n‘3“m“‘7’,.mm.rx{7.7_“
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`
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`
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`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 10 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 7 of 13
`
`US 7,446,338 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi31 TO Pi, n
`
`
`
`
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME!
`
`LIGHT EMISSION
`PERIOD OF PIXEL
`I CIRCUITS PL 1 TO Pi, n
`
`VOLTAGE LEVEL
`OF SCAN LINE Xi
`
`VH
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`
`AND SUPPLY LINE Zi
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT PM
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT PL]-
`
`VOLTAGE LEVEL
`.OF SCAN LINE Xm
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINE Zi+1
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT PM]
`
`LIGHT EMISSION
`
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi+1,1 T0 Pi+1,n
`
`
`
`LIGHT EMISSION
`i
`PERIOD OF PIXEL
`!C|RCUITS P;+1,1 TO Pi+1,n
`
`LIGHT EMISSION
`
`FIG.7
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 11 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 8 of 13
`
`US 7,446,338 B2
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi.1TO Pi. n
`
`LIGHT EMISSION
`PERIOD OF
`PRECEDING FRAME
`OF PIXEL CIRCUITS
`Pi’1 TO Pi, n
`
`LIGHT EMISSION PERIOD OF
`GIVEN FRAME OF PIXEL
`
`CIRCUITS Pi,1 TO Pi, n
`
`VOLTAGE LEVEL
`OF SCAN LINE xi
`
`VOLTAGE LEVEL OF FEED
`INTERCONNECTION 90
`AND SUPPLY LINES
`
`VH
`
`PIXEL CIRCUIT PLI
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`
`:
`I
`
`! LIGHT
`EMISSION
`
`LIGHT
`EMISSION
`
`LIGHT
`EMISSION
`
`SELECTION PERIOD
`OF PIXEL CIRCUITS
`Pi+1, 1 TO pi+1, n
`H
`
`'
`
`'
`.
`
`I:
`
`LIGHT EMISSION
`
`IIEIENESEW
`.
`XEL
`lcmcuns Pi+1 1To
`i
`Pm n
`’
`.r<—————-’
`
`LIGHT
`EM‘SS'ON
`
`i
`-
`PRECEOING FRAME!
`OF PIXEL CIRCUITS i
`Pi+1,1 T0 Pi+1,n
`:
`‘——>l
`I
`I
`
`FIG.8
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`OF PIXEL CIRCUIT PM
`
`VOLTAGE LEVEL
`OF SCAN LINE x.“
`
`VOLTAGE LEVEL OF
`TRANSISTOR 23 OF
`PIXEL CIRCUIT PM.
`
`CURRENT VALUE OF
`ORGANIC EL ELEMENT 20
`0F PIXEL CIRCUIT PM,-
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 12 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 9 of 13
`
`US 7,446,338 B2
`
`VP1 VPZ' VP2
`
`VP3 vpa'
`
`7.0x1 0'6
`
`ts.o><10'6
`
`Id [A]
`
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`‘
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`4.o><10'6
`7
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`
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`
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`
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`
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`
`—u—..— Vpo
`
`_......._ Vds=vgs:Vpo+Vth
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 13 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 10 0f 13
`
`US 7,446,338 B2
`
`32-INCH PANEL
`
`:3IIIIIIIIIIlllllIIIIIIIIIIIIIIIIIIIIIIIIIIII"Ill"
`IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII'll-'llllll
`IllllMIIIIIIiiiiiiiiiiiiiiiiillllll
`
`I
`
`7
`
`3
`
`9
`
`10
`
`MAXIMUM
`
`VOLTAGE
`DROP [V]
`
`4
`
`6
`
`p18 [Q/crn]
`
`FIG.10
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 14 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 11 0f 13
`
`US 7,446,338 B2
`
`1 ,0x107 _________________________
`
`32-INCH PANEL
`
`W105 IIIIIIIIIIIIIIIIIIIIIIIII
`
`CURRENT
`DENSITY
`[A/cmz]
`
`mull-Illlllllllllllllllll
`“IIIIIIIIIIIIIIIIIIIIIIII
`l‘IIIIIIIIIIIIIIIIIIIIIIII
`1-0X105 =a=======================
`=H==E=============E=====
`
`--L‘---------------------
`Ilm-Il-I-I-Il-I-I-I-I-I-I
`lulu-IIIIIIIIIIIIIIIIIIII
`IIIIEIIIIIIIIIIIIIIIIIIII
`V
`IIIIIII.!!IIIIIIIIIIIIIII
`1-0)“ 04 ===========:_--===========
`
`_fl—----n-----;_,----------
`----------------—‘::"-------
`
`I-I-I-I-I-I- ---------
`
`1.0><1030
`
`100
`
`SECTIONAL AREA 3 [mam
`
`150
`
`250
`
`FIG.11
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 15 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 12 0f 13
`
`US 7,446,338 B2
`
`40-INCH PANEL
`
`VOLTAGE
`
`MAXIMUM
`DROP[V]
`
`:5IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIlllm“IIIIIII
`:IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIll"...
`“I'll
`IIIIIIIIIIIILIIIIIII'IIIIIIIIIIIIIIIIIIIIIIIIIIIII
`LOI'III'"'"IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
`IIIIII
`
`‘al'll
`
`4p/S [SE/cm]6
`
`FIG.12
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 16 of 29
`
`US. Patent
`
`NOV. 4, 2008
`
`Sheet 13 0f 13
`
`US 7,446,338 B2
`
`40-INCH PANEL
`
`111111116 IIIIIIIIIIIIIIIIIIIIIIIII
`
`-—------‘fi----_-—--—- --u-
`l-------------------------
`
`DENSITY
`[A/cm2]
`
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`IIIIIIIIIIIIIIIIIIIIIIIII
`1 15 IEIIIIIIIIIIIIIIIIIIIllll
`-
`==I=========§=============
`==§=====n==-=============
`--.n-------------------_-
`III-N-I-Il-I-Ii-l-I-ll-II
`III-IaqulnIII-IIIIIIIIIII
`IIIIIIIELIIIIIIIIIIIIIIIII
`“I
`
`11111114 IIIIIIIIIIIII!!!IIIIIIIII
`
`——_———_————————-—_:*-—-_———_
`--_-‘------—-—----h—_fl—‘---
`--_--------_---------—u—_'___
`
`111 IIIIIOIIIIIIIIIIIIIIIIIIII50
`
`100
`
`150
`
`200
`
`SECTIONAL AREA 5 [m2]
`
`FIG.13
`
`

`

`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 17 of 29
`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 17 of 29
`
`US 7,446,338 B2
`
`2
`
`words, the electrode is not designed assuming that it supplies
`a current to a light-emitting element. Hence, the thin-film
`transistor is thin literally. If a current is supplied from the
`interconnection to a plurality of light-emitting elements, a
`voltage drop occurs, or the current flow through the intercon-
`nection delays due to the electrical resistance of the intercon-
`nection. To suppress the voltage drop or interconnection
`delay, the resistance of the interconnection is preferably low.
`If the resistance of the interconnection is reduced by making
`a metal layer serving as the source and drain electrodes ofthe
`transistor or a metal layer serving as the gate electrode thick,
`or patterning the metal layers considerably wide to suffi-
`ciently flow the current through the metal layers, the overlap
`area of the interconnection on another interconnection or
`
`conductor when viewed from the upper side increases, and a
`parasitic capacitance is generated between them. This retards
`the flow of the current. Alternatively, in a so-called bottom
`emission structure which emits EL light from the transistor
`array substrate side, light emitted from the EL elements is
`shielded by the interconnections, resulting in a decrease in
`opening ratio, i.e., the ratio of the light emission area. If the
`gate electrode ofthe thin-film transistor is made thick to lower
`the resistance, a planarization film (corresponding to a gate
`insulating film when the thin-film transistor has, e.g., an
`inverted stagger structure) to eliminate the step of the gate
`electrode must also be formed thick. This may lead to a large
`change in transistor characteristic. When the source and drain
`electrodes are formed thick, the etching accuracy of the
`source and drain electrodes degrades. This may also
`adversely affect the transistor characteristic.
`
`BRIEF SUMMARY OF THE INVENTION
`
`It is an object of the present invention to satisfactorily drive
`a light-emitting element while suppressing any voltage drop
`and signal delay.
`A display panel according to a first aspect of the present
`invention comprises: a transistor array substrate which has a
`plurality of pixels and is formed by providing a plurality of
`transistors for each pixel, each of the transistor having a gate,
`a gate insulating film, a source, and a drain;
`a plurality of interconnections which are formed to project
`to a surface of the transistor array substrate and arrayed in
`parallel to each other;
`a plurality of pixel electrodes which are provided for each
`pixel and arrayed between the interconnections on the surface
`of the transistor array substrate along the interconnections;
`a plurality of light-emitting layers each of which is formed
`on each pixel electrode; and
`a counter electrode which is stacked on the light-emitting
`layer.
`A display panel according to a second aspect of the present
`invention comprises: a plurality of pixel electrodes;
`a plurality of light-emitting layers which are provided for
`said plurality of pixel electrodes, respectively;
`a counter electrodes which is provided for said plurality of
`light-emitting layers respectively;
`a plurality of driving transistors which are connected to
`said plurality of pixel electrodes, respectively;
`a plurality of switch transistors each of which supplies a
`write current between a source and drain of a corresponding
`one of said plurality of driving transistors;
`a plurality of holding transistors each of which holds a
`voltage between the source and a gate of a corresponding one
`of said plurality of driving transistors;
`a plurality of feed interconnections which are formed from
`a conductive layer different from a layer serving as sources,
`
`1
`
`DISPLAY PANEL
`
`CROSS-REFERENCE TO RELATED
`
`APPLICATIONS
`
`This application is based upon and claims the benefit of
`priority from prior Japanese Patent Application No. 2004-
`283824, filed Sep. 29, 2004, the entire contents of which are
`incorporated herein by reference.
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`
`The present invention relates to a display panel using a
`light-emitting element.
`2. Description of the Related Art
`Organic electroluminescent display panels can roughly be
`classified into passive driving types and active matrix driving
`types. Organic electroluminescent display panels of active
`matrix driving type are more excellent than those of passive
`driving type because of high contrast and high resolution. In
`a conventional organic electroluminescent display panel of
`active matrix display type described in, e. g., Jpn. Pat. Appln.
`KOKAI Publication No. 8-330600, an organic electrolumi-
`nescent element (to be referred to as an organic EL element
`hereinafter), a driving transistor which supplies a current to
`the organic EL element when a voltage signal corresponding
`to image data is applied to the gate, and a switching transistor
`which performs switching to supply the voltage signal corre-
`sponding to image data to the gate of the driving transistor are
`arranged for each pixel. In this organic electroluminescent
`display panel, when a scan line is selected, the switching
`transistor is turned on. At this time, a voltage of level repre-
`senting the luminance is applied to the gate of the driving
`transistor through a signal
`line. The driving transistor is
`turned on. A driving current having a magnitude correspond-
`ing to the level of the gate voltage is supplied from the power
`supply to the organic EL element through the drain-to-source
`path of the driving transistor. The organic EL element emits
`light at a luminance corresponding to the magnitude of the
`current. In the period from the end of scan line selection to the
`next scan line selection, the level of the gate voltage of the
`driving transistor is continuously held even after the switch-
`ing transistor is turned off. Hence, the organic EL element
`emits light at a luminance corresponding to the magnitude of
`the driving current corresponding to the voltage.
`To drive the organic electroluminescent display panel, a
`driving circuit is provided around it to apply a voltage to the
`scan lines, signal lines, and power supply lines laid on the
`organic electroluminescent display panel.
`In the conventional organic electroluminescent display
`panel of active matrix driving type, interconnections such as
`a power supply line to supply a current to an organic EL
`element are patterned simultaneously in the thin-film transis-
`tor patterning step by using the material of a thin-film tran-
`sistor such as a switching transistor or driving transistor.
`More specifically, in manufacturing the organic electrolumi-
`nescent display panel, a conductive thin film as a prospective
`electrode of a thin-film transistor is subjected to photolithog-
`raphy and etching to form the electrode of a thin-film transis-
`tor from the conductive thin film. At the same time, an inter-
`connection connected to the electrode is also formed. For this
`
`reason, when the interconnection is formed from the conduc-
`tive thin film, the thickness of the interconnection equals that
`of the thin-film transistor.
`
`However,
`the electrode of the thin-film transistor is
`designed assuming that it functions as a transistor. In other
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`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 18 of 29
`Case 6:19-cv-00537-ADA Document 1-2 Filed 09/12/19 Page 18 of 29
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`US 7,446,338 B2
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`BRIEF DESCRIPTION OF THE SEVERAL
`VIEWS OF THE DRAWING
`
`FIG. 1 is a plan view showing four pixels of a display panel
`
`5
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`1;
`
`drains, and gates of said plurality of driving transistors, said
`plurality of switch transistors, and said plurality of holding
`transistors and connected to the drains of said plurality of
`driving transistors;
`a plurality of select interconnections each of which selects
`FIG. 2 is an equivalent circuit diagram of a sub-pixel P of
`the switch transistor; and
`the display panel 1;
`a plurality of common interconnections each of which is
`FIG. 3 is a plan view showing the electrodes of a red
`connected to the counter electrode.
`sub-pixel Pr;
`A display panel according to a third aspect of the present
`FIG. 4 is a plan view showing the electrodes of a green
`invention comprises: a plurality of pixel electrodes;
`sub-pixel Pg;
`a light-emitting layer which is provided for each of said
`FIG. 5 is a plan view showing the electrodes of a blue
`plurality of pixel electrodes;
`sub -pixel Pb;
`a counter electrode which is provided for the light-emitting
`FIG. 6 is a sectional view taken along a line VI-VI in FIGS.
`layer;
`a driving transistor which is connected to each of said 15 3 to 5;
`plurality 0f pixel electrode;
`FIG. 7 is a timing chart for explaining a driving method of
`a switch transistor which supplies a write current between
`the display panel 1;
`a source and drain 0f the driving transistor;
`FIG. 8 is a timing chart for explaining another driving
`a holding transistor which holds a voltage between the
`method of the display panel 1;
`source and gate ofthe driving transistor;
`FIG. 9 is a graph showing the current vs. voltage charac-
`a select interconnection which selects the switch transistor;
`teri stic Ofa driving transistor 23 and organic EL element 20 Of
`a common interconnection which is formed from a con-
`each sub-pixel;
`ductive layer different from a layer serving as sources and
`FIG. 10 is a graph showing the correlation between the
`drains and a layer serving as gates ofthe driving transistor, the
`maximum voltage drop and the interconnection resistivity
`switch transistor, and the holding transistor and connected to 25 p/sectional area S of a feed interconnection 90 and common
`the counter electrode; and
`interconnection 91 of a 32-inch display panel 1;
`a feed interconnection which is formed from a conductive
`FIG. 11 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec-
`tion 90 and common interconnection 91 of the 32-inch dis-
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`layer different from the layer serving as the sources, drains,
`and gates of the driving transistor, the switch transistor, and
`the holding transistor and connected to the drain ofthe driving 30
`transistor and is thicker than the common interconnection.
`
`play panel 1;
`FIG. 12 is a graph showing the correlation between the
`maximum voltage drop and the interconnection resistivity
`p/sectional area S ofthe feed interconnection 90 and common
`interconnection 91 of a 40-inch display panel 1; and
`FIG. 13 is a graph showing the correlation between the
`sectional area and the current density of the feed interconnec-
`tion 90 and common interconnection 91 of the 40-inch dis-
`
`play panel 1.
`
`DETAILED DESCRIPTION OF THE INVENTION
`
`The best mode for carrying out the present invention will be
`described below with reference to the accompanying draw-
`ings. Various kinds of limitations which are technically pref-
`erable in carrying out the present invention are added to the
`embodiments to be described below. However, the spirit and
`scope ofthe present invention are not limited to the following
`embodiments and illustrated examples. In the following
`description, the term ccelectrolumi11escence” will be abbrevi-
`50 ated as EL
`
`A display panel according to a fourth aspect of the present
`invention comprises: a transistor array substrate which is
`formed by providing a plurality of transistors for each pixel,
`each transistor having a gate, a gate insulating film, and a 35
`source/drain;
`a plurality of pixel electrodes which are provided in a
`plurality of rows on the transistor array substrate;
`a first light-emitting layer which is provided on each of said
`plurality ofpixel electrodes ofa first row to emit light ofa first 40
`color;
`a second light-emitting layer which is provided on each of
`said plurality of pixel electrodes of a second row to emit light
`of a second color;
`a third light-emitting layer which is provided on each of 45
`said plurality of pixel electrodes of a third row to emit light of
`a third color;
`1. h
`h fi
`.d d
`hi h'
`d
`1
`rst 1g t'
`a counter e ectro e W C
`1s prow e ont e
`emitting layer, the second light-emitting layer, and the third
`11ght-emlttlng layer;
`a select interconnection which has a top higher than first
`[Planar Layout of Display Panel]
`light-emitting layer, the second light-emitting layer, and the
`FIG. 1 is a schematic plan view showing adjacent four of a
`third light-emitting layer and selects at least one of said plu-
`plurality of pixels 3 provided on an insulating substrate 2 of a
`rality of transistors;
`a common interconnection which has a top higher than first 55 display panel 1 which is operated by the active matrix driving
`light-emitting layer, the second light-emitting layer, and the
`method. In the display panel 1, as for the pixels in the column
`third light-emitting layer and is connected to the counter
`direction, a plurality of red sub-pixels Pr are arrayed in the
`electrode; and
`horizontal direction (row direction). A plurality of green sub-
`a feed interconnection which has a top higher than first
`pixels Pg are arrayed in the horizontal direction.Aplurality of
`light-emitting layer, the second light-emitting layer, and the 60 blue sub -pixels Pb are arrayed in the horizontal direction. As
`third light-emitting layer and is connected to said plurality of
`for the sequence in the vertical direction (column direction),
`pixel electrodes of said plurality of transistors.
`the red sub-pixel Pr, green sub -pixel Pg, and blue sub-pixel Pb
`According to the present invention, since the interconnec-
`are repeatedly arrayed in this order. The l-dot red sub-pixel
`tions can be made thick, the resistance of the interconnections
`Pr, l-dot green sub -pixel Pg, and l-dot blue sub-pixel Pb are
`can be reduced. When the resistance of the interconnections 65 combined to form one pixel 3. Such pixels 3 are arrayed in a
`decreases, the signal delay and voltage drop can be sup-
`matrix. In the following description, an arbitrary one of the
`pressed.
`red sub-pixel Pr, green sub-pixel Pg, and blue sub-pixel Pb is
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`US 7,446,338 B2
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`represented by a sub -pixel P. The description of the sub-pixel
`P applies to all the red sub-pixel Pr, green sub-pixel Pg, and
`blue sub-pixel Pb.
`Three signal lines Yr, Yg, and Yb running in the vertical
`direction form one set. The combination of the three signal
`lines Yr, Yg, andYb is called a signal line group 4. In each
`signal line group 4, the three signal lines Yr, Yg, andYb are
`arranged Close to each other. The interval between the adja-
`cent signal line groups 4 is wider than that between the adja-
`cent signal lines Yr, Yg, andYb in each signal line group 4.
`One signal line group 4 is provided in correspondence with
`one column of pixels 3 in the vertical direction. That is, the
`sub-pixels Pr, Pg, and Pb in one column arrayed in the vertical
`direction are connected to the signal lines Yr, Yg, andYb of
`one signal line group 4, respectively.
`The first signal line Yr supplies a signal to all the red
`sub-pixels Pr of the column of pixels 3 in the vertical direc-
`tion. The second signal line Yg supplies a signal to all the
`green sub-pixels Pg of the column of pixels 3 in the vertical
`direction. The third signal lineYb supplies a signal to all the
`blue sub-pixels Pb of the column of pixels 3 in the vertical
`direction.
`
`A plurality of scan lines X run in the horizontal direction.
`A plurality of supply lines Z, a plurality of select intercon-
`nections 89, a plurality of feed interconnections 90, and a
`plurality of common interconnections 91 are provided in
`parallel to the scan lines X. One scan line X, one supply line
`Z, one feed interconnection 90, one select interconnection 89,
`and one common interconnection 91 are provided in corre-
`spondence with one line of pixels 3 in the horizontal direc-
`tion. More specifically, the common interconnection 91 is
`arranged between the red sub -pixel Pr and the green sub -pixel
`Pg which are adjacent in the vertical direction. The scan line
`X and select interconnection 89 are arranged between the
`green sub-pixel Pg and the blue sub-pixel Pb which are adja-
`cent in the vertical direction. The supply line Z and feed
`interconnection 90 are arranged between the blue sub-pixel
`Pb and the red sub -pixel Pr of the adjacent pixel 3. The select
`interconnections 89 and feed interconnections 90 have the
`
`same thickness.
`
`The scan line X supplies a signal to all the sub-pixels Pr, Pg,
`and Pb of the pixels 3 of one line arrayed in the horizontal
`direction. The supply line Z also supplies a signal to all the
`sub-pixels Pr, Pg, and Pb of the pixels 3 of one line arrayed in
`the horizontal direction.
`
`When viewed from the upper side, the select interconnec-
`tion 89 overlaps the scan line X in the running direction and is
`thus electrically connected to the scan line X. The feed inter-
`connection 90 overlaps the supply line Z in the running direc-
`tion and is thus electrically connected to the supply line Z.
`The color of each the sub-pixels Pr, Pg, and Pb is deter-
`mined by the color of light emitted from an organic EL
`element 20 (FIG. 2) (to be described later). The position of
`each of the sub-pixels Pr, Pg, and Pb, which is represented by
`a rectangle long in the horizontal direction in FIG. 1, indicates
`the position of a sub-pixel electrode 20a (in FIG. 2) serving as
`an anode of the organic EL element 20. More specifically,
`when the entire display panel 1 is viewed from the upper side,
`the plurality of sub-pixel electrodes 20a are arrayed in a
`matrix. The l-dot sub-pixel P is determined by one sub -pixel
`electrode 20a. Hence, the plurality of sub-pixel electrodes
`20a are arrayed in the horizontal direction between the feed
`interconnection 90 and the adjacent common interconnection
`91. Said plurality of sub-pixel electrodes 20a are arrayed in
`the horizontal direction between the common interconnection
`
`91 and the adjacent select interconnection 89. Said plurality
`of sub-pixel electrodes 20a are arrayed in the horizontal
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`direction between the select interconnection 89 and the adja-
`cent feed interconnection 90. When an insulating film which
`is sufficiently thick so no parasitic capacitance is generated is
`inserted between the signal line group 4 and the electrode or
`interconnection located above the signal line group 4, the
`signal line group 4 may overlap the sub-pixel electrode 20a
`connected to it when viewed from the upper side. In addition,
`the signal line group 4 may overlap the sub-pixel electrode
`20a of one sub-pixel adjacent to the sub-pixel connected to
`the signal line group 4 when viewed from the upper side.
`When the display panel 1 has a bottom emission structure, the
`signal line group 4 preferably does not overlap the sub-pixel
`electrode 20a when viewed from the upper side.
`
`When In and n are integers (mi2, n22), m pixels 3 are
`arrayed in the vertical direction, and 11 pixels 3 are arrayed in
`the horizontal direction, the sub-pixel electrodes 20a equal in
`number to the sub -pixels of one column, i.e., (3xm) sub-pixel
`electrodes 200: are arrayed in the vertical direction. The sub-
`pixel electrodes 20a equal in number to the sub-pixels of one
`row, i.e., n sub-pixel electrodes 20a are arrayed in the hori-
`zontal direction. In this case,
`11 signal line groups 4 are
`arranged, and m scan lines X, m supply lines Z, m select
`interconnections 89, m feed interconnections 90, and m com-
`mon interconnections 91 are arranged. The total number of
`select interconnections 89, feed interconnections 90, and
`common interconnections 91, which also serve as partition
`walls to prevent leakage of an organic compound-containing
`solution as a perspective organic EL layer 20b of the organic
`EL element 20 (to be described later) from the sub-pixels of
`one row, is (3xm). To partition the organic compound-con-
`taining solution in all rows for the sub -pixels of each row, the
`total number of select interconnections 89, feed interconnec-
`tions 90, and common interconnections 91 must be (3xm+l).
`To do this, a (3xm+l)th partition dummy interconnection
`having the same height and same length as the common
`interconnection 91 is arranged in the row direction in parallel
`to the select interconnections 89, feed interconnections 90,
`and common interconnections 91. The select interconnec-
`
`tions 89, feed interconnections 90, and common interconnec-
`tions 91 are used as partition walls, their top portions are
`higher than the organic EL layer 2019 and the liquid level ofthe
`organic compound-containing solution.
`
`[Circuit Arrangement of Sub-Pixel]
`
`The circuit arrangement of the first to third sub -pixels Pr,
`Pg, and Pb will be described next with reference to the equiva-
`lent circuit diagram in FIG. 2. All the sub-pixels Pr, Pg, and Pb
`have the same arrangement. The organic EL element 20, first
`to third N—channel amorphous silicon thin-film transistors (to
`be simply referred to as transistors hereinafter) 21, 22, and 23,
`and a capacitor 24 are provided for the l-dot sub-pixel PM.
`The first transistor 21 will be referred to as the switch tran-
`
`sistor 21, the second transistor 22 will be referred to as the
`holding transistor 22, and the third transistor 23 will be
`referred to as the driving transistor 23 hereinafter. In FIG. 2
`and the following description, the signal line Y for the red
`sub -pixel Pr represents the signal line Yr in FIG. 1, the signal
`lineY for the green sub-pixel Pg represents the sign