Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 1 of 20
`1:22-CV-425
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Claim 1
`A graphics processing
`circuit, comprising:
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`To the extent that the preamble is limiting, the NXP processors meet this limitation.
`
`The NXP processors perform graphics processing. To illustrate:
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.1, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com).
`
`The NXP processors include one or more Graphics Processing Unit (GPU) subsystems that include one or
`more GPUs. To illustrate:
`
`Id., § 16.1.1. To illustrate further:
`
`—1—
`
`
`1:22-CV-425
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Claim 1
`A graphics processing
`circuit, comprising:
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`To the extent that the preamble is limiting, the NXP processors meet this limitation.
`
`The NXP processors perform graphics processing. To illustrate:
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 1.1.1, Document No.: IMX8QMRM, Rev 0,
`9/2021 (downloaded from nxp.com).
`
`The NXP processors include one or more Graphics Processing Unit (GPU) subsystems that include one or
`more GPUs. To illustrate:
`
`Id., § 16.1.1. To illustrate further:
`
`—1—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 2 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Claim 1
`
`
`Id.
`
`
`
`
`—2—
`
`
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 3 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`On information and belief, the NXP processors meet this limitation.
`
`For instance, the NXP processors perform “massively parallel data processing” across “multiple compute
`engines,” and “each compute unit has its own arithmetic logic units (ALUs) . . . that can perform
`computations.”
`
`
`Claim 1
`at least two graphics
`pipelines on a same
`chip operative to
`process data in a
`corresponding set of
`tiles of a repeating tile
`pattern corresponding
`to screen locations,
`
`
`i.MX Graphic User’s Guide, § 5.1.1, Document No. IMXGRAPHICUG, Rev. 0, 05/2018, available at
`https://www.nxp.com/docs/en/user-guide/i.MX_AA_Graphics_User's_Guide.pdf.
`
`To illustrate further, NXP’s user guides show the Vivante OpenCL data pipeline used in its GPUs and
`NXP’s public demonstrations of its processors depicts the use of multiple graphics pipelines on a chip:
`
`
`
`
`
`
`
`—3—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 4 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Claim 1
`
`
`Id., § 5.2.1. To illustrate further, the NXP processors exhibit “massive data parallelism” and “tile
`rasterization”:
`
`
`
`
`
`
`—4—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 5 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Claim 1
`
`
`R. Malewski, i.MX 8 Graphics Architecture, FTF-DES-N1940, FTF 2016 Technology Forum (May 18,
`2016), https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/ftf2016/88/1/FTF-DES-
`N1940%20i.MX%208%20Graphics%20Architecture.pdf. The presence of multiple shaders, rendering
`engines, textures engines, and pixel engines indicates the presence of multiple pipelines.
`
`On information and belief, the pipelines are operative to process data in a corresponding set of tiles of a
`repeating tile pattern corresponding to screen locations. As shown in the figure above, the NXP processors
`use “tile rasterization,” which is believed to refer to a rasterizer that rasterizes graphics on a per-tile basis
`and with the tiles comprising a repeating tile pattern corresponding to screen locations. Documentation for
`the processor also includes additional references to tiles.
`
`
`
`
`
`—5—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 6 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`
`Claim 1
`
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 15.7.1.2.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com). To illustrate further:
`
`
`
`
`
`Id., § 15.7.1.2.5. To illustrate further:
`
`
`—6—
`
`
`
`
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 7 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Claim 1
`
`
`Id., § 15.7.1.2.7.1. To illustrate further, NXP public demonstrations of the related i.MX 6 processors
`suggests those processors also use tile-based rendering:
`
`
`
`
`
`
`—7—
`
`
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 8 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`i.MX 6 Series Portfolio Overview dated August 2013, available at
`https://www.nxp.com/docs/en/supporting-information/DWF13_AMF_CON_T0060.pdf.
`On information and belief, the NXP processors meet this limitation.
`
`The NXP processors exhibit “tile rasterization”:
`
`
`Claim 1
`
`a respective one of the
`at least two graphics
`pipelines operative to
`process data in a
`dedicated tile; and
`
`
`R. Malewski, i.MX 8 Graphics Architecture, FTF-DES-N1940, FTF 2016 Technology Forum (May 18,
`2016), https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/ftf2016/88/1/FTF-DES-
`N1940%20i.MX%208%20Graphics%20Architecture.pdf.
`
`
`
`
`
`—8—
`
`
`
`Claim 1
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 9 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`On information and belief, a respective one of the at least two graphics pipelines operative to process data
`in a dedicated tile. As shown in the figure above, the NXP processors use “tile rasterization,” which on
`information and belief refers to a rasterizer that processes data in a dedicated tile. Documentation for the
`processor also includes additional references to tiles. To illustrate further:
`
`
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 15.7.1.2.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com). To illustrate further:
`
`
`
`
`
`
`—9—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 10 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Claim 1
`
`
`Id., § 15.7.1.2.5. To illustrate further:
`
`
`
`
`
`Id., § 15.7.1.2.7.1. To illustrate further, NXP public demonstrations of the related i.MX 6 processors
`suggests those processors also use tile-based rendering and on information and believe process data in a
`dedicated tile:
`
`
`
`
`
`—10—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 11 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`
`Claim 1
`
`
`i.MX 6 Series Portfolio Overview dated August 2013, available at
`https://www.nxp.com/docs/en/supporting-information/DWF13_AMF_CON_T0060.pdf.
`
`
`
`
`
`—11—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 12 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`On information and belief, the NXP processors meet this limitation.
`
`Each GPU includes a memory controller. To illustrate:
`
`
`Claim 1
`a memory controller
`on the chip in
`communication with
`the at least two
`graphics pipelines,
`operative to transfer
`pixel data between
`each of a first pipeline
`and a second pipeline
`and a memory shared
`among the at least two
`graphics pipelines;
`
`
`i.MX 8QuadMax Applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0, 9/2021
`(downloaded from nxp.com).
`
`
`
`
`
`—12—
`
`
`
`Claim 1
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 13 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`The memory controller is defined as an “[i]nternal memory management unit that controls the block-to-
`host memory request interface”:
`
`
`
`Id., § 16.4.1.1.
`
`On information and belief, the memory controller is operative to transfer pixel data between each of the
`shader cores and a memory shared by at least two shader cores. For example, the display subsystem can
`pre-fetch display data before the display data needs the data. The display subsystem obtains pixel data
`from “GPU buffers.” To illustrate:
`
`
`
`
`
`
`—13—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 14 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Claim 1
`
`
`Id., § 15.7.1.2.5. On information and belief, the GPU buffers are shared by the shader cores and are
`managed by the memory controller.
`
`As another example, the GPU can in some cases store pixel data in global memory. To illustrate:
`
`
`
`
`
`
`—14—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 15 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Claim 1
`
`
`i.MX Graphic User’s Guide, § 5.1.2.3, Document No. IMXGRAPHICUG, Rev. 0, 05/2018, available at
`https://www.nxp.com/docs/en/user-guide/i.MX_AA_Graphics_User’s_Guide.pdf.
`
`On information and belief, the global memory is shared by the shader cores. Indeed, by definition, global
`memory is available to the entire system. NXP’s documents show that each “compute device” has a global
`memory space, meaning this memory space is shared by all shader cores on the GPU. As shown in Fig. 16-
`3, above, the memory controller controls communication with the system bus and the global memory.
`
`
`
`
`
`
`—15—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 16 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`Claim 1
`
`
`i.MX 8QuadMax applications Processor Reference Manual, Document No.: IMX8QMRM, Rev 0, 9/2021
`(downloaded from nxp.com).
`
`
`
`—16—
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 17 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`On information and belief, the NXP processors meet this limitation.
`
`The NXP processors exhibit “tile rasterization”:
`
`
`Claim 1
`wherein the repeating
`tile pattern includes a
`horizontally and
`vertically repeating
`pattern of square
`regions.
`
`
`R. Malewski, i.MX 8 Graphics Architecture, FTF-DES-N1940, FTF 2016 Technology Forum (May 18,
`2016), https://community.nxp.com/pwmxy87654/attachments/pwmxy87654/ftf2016/88/1/FTF-DES-
`N1940%20i.MX%208%20Graphics%20Architecture.pdf.
`
`
`
`
`
`
`
`—17—
`
`
`
`Claim 1
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 18 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`On information and belief, tile rasterization involves a repeating tile pattern with a horizontally and
`vertically repeating pattern of square regions. To illustrate further:
`
`
`
`i.MX 8QuadMax Applications Processor Reference Manual, § 15.7.1.2.4, Document No.: IMX8QMRM,
`Rev 0, 9/2021 (downloaded from nxp.com). To illustrate further:
`
`
`
`
`
`Id., § 15.7.1.2.5. To illustrate further:
`
`—18—
`
`
`
`
`
`
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 19 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`
`Claim 1
`
`
`Id., § 15.7.1.2.7.1. To illustrate further, NXP public demonstrations of the related i.MX 6 processors
`suggests those processors also use tile-based rendering and on information and believe process data in a
`dedicated tile:
`
`
`
`
`
`
`—19—
`
`
`
`
`
`Claim 1
`
`Case 1:22-cv-00425-RP Document 1-2 Filed 05/05/22 Page 20 of 20
`
`EXHIBIT B
`U.S. Patent No. 8,933,945
`
`Exemplary Accused Product: NXP i.MX 8QuadMax Applications Processor
`
`i.MX 6 Series Portfolio Overview dated August 2013, available at
`https://www.nxp.com/docs/en/supporting-information/DWF13_AMF_CON_T0060.pdf.
`
`—20—
`
`
`
`
`
`
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
