Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 1 of 36 PageID #: 2085
`
`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
`
`Civil Action No. 2:15-CV-341-JRG-RSP
`
`LEAD CASE
`
`JURY TRIAL DEMANDED
`
`
`
`RAYTHEON COMPANY,
`
`Plaintiff,
`
`v.
`
`SAMSUNG ELECTRONICS CO., LTD., ET AL.,
`
`Defendants.
`
`)
`)
`)
`)
`)
`)
`)
`)
`)
`)
`)
`
`
`
`DEFENDANTS’ RESPONSIVE CLAIM CONSTRUCTION BRIEF
`
`
`
`
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 2 of 36 PageID #: 2086
`
`TABLE OF CONTENTS
`
`Page
`
`I.
`
`II.
`
`INTRODUCTION .............................................................................................................. 1
`
`THE LEGAL STANDARD FOR CLAIM CONSTRUCTION ......................................... 1
`
`III.
`
`INTRODUCTION TO THE CLAIMED TECHNOLOGY ................................................ 2
`
`IV.
`
`ARGUMENT ...................................................................................................................... 4
`
`A.
`
`B.
`
`C.
`
`Order of the Recited Steps ...................................................................................... 5
`
`“First Substrate” .................................................................................................... 10
`
`“Etch-Stop Layer,” “Etchable Layer” and “Etching Away the Etchable
`Layer . . . Down to the Etch-Stop Layer” ............................................................. 13
`
`D.
`
`“Wafer” ................................................................................................................. 18
`
`1.
`2.
`
`The Sony Defendants’, OmniVision’s and Apple’s Argument ................ 18
`Samsung’s Argument ................................................................................ 21
`
`“Overlying” ........................................................................................................... 22
`
`“Microelectronic Circuit Element” ....................................................................... 24
`
`“Attaching” ........................................................................................................... 25
`
`“Second Substrate” ............................................................................................... 26
`
`“The Step of Attaching Includes the Step of Making an Electrical
`Contact…” ............................................................................................................ 28
`
`E.
`
`F.
`
`G.
`
`H.
`
`I.
`
`CONCLUSION ................................................................................................................. 29
`
`V.
`
`
`
`
`-i-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 3 of 36 PageID #: 2087
`
`TABLE OF AUTHORITIES
`
`CASES
`
`Page(s)
`
`Abbott Labs. v. Syntron Bioresearch, Inc., 334 F.3d 1343 (Fed. Cir. 2003) .................................17
`
`Absolute Software, Inv. v. Stealth Signal, Inc., 659 F. 3d 1121 (Fed. Cir. 2011) ..........................21
`
`Altiris, Inc. v. Symantec Corp. 318 F.3d 1363 (Fed. Cir. 2003) ..................................................5, 6
`
`Amgen Inc. v. Hoechst Marion Roussel, Inc., 314 F.3d 1313 (Fed. Cir. 2003) ...............................1
`
`Apple Inc. v. Motorola, Inc., 757 F.3d 1286 (Fed. Cir. 2014) .................................................6, 7, 8
`
`Blue Calypso, Inc. v. Groupon, Inc., 93 F. Supp. 3d 575 (E.D. Tex. June 14, 2015) ....................27
`
`CardSoft, LLC v. VeriFone, Inc., 807 F.3d 1346 (Fed. Cir. 2015) ................................................20
`
`Inline Plastics Corp. v. Easypak, LLC, 799 F.3d 1364 (Fed. Cir. 2015) .......................................27
`
`Mantech Envtl. Corp. v. Hudson Envtl. Servs., Inc., 152 F.3d 1368 (Fed. Cir.
`1998) ....................................................................................................................................5
`
`Markman v. Westview Instruments, Inc., 52 F.3d 967 (Fed. Cir. 1995) (en banc),
`aff'd, 517 U.S. 370 (1996) ................................................................................................1, 2
`
`Merck & Co., Inc. v. Teva Pharms. USA, Inc., 395 F.3d 1364 (Fed. Cir. 2005) ...................1, 2, 17
`
`Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en banc) .......................................1, 2, 27
`
`Salazar v. Proctor & Gamble Co., 414 F.3d 1342 (Fed. Cir. 2005) ................................................2
`
`Sinorgchem Co., Shandong v. International Trade Com’n, 511 F.3d 1132 (Fed.
`Cir. 2008) ...........................................................................................................................21
`
`Syncpoint Imaging, LLC v. Nintendo of America Inc., Case No. 2:15-cv-00247,
`slip op. (E.D. Tex. Jan 5, 2016) ...........................................................................................8
`
`Verizon Servs. Corp. v. Vonage Holdings Corp., 503 F.3d 1295 (Fed. Cir. 2007) .......................21
`
`
`
`
`
`-ii-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 4 of 36 PageID #: 2088
`
`I.
`
`INTRODUCTION
`
`Defendants Sony Kabushiki Kaisha, Sony Corporation of America, Sony Semiconductor
`
`Corporation, Sony EMCS Corporation, Sony Electronics Inc., Sony Mobile Communications
`
`Inc., Sony Mobile Communications AB, Sony Mobile Communications (USA) Inc. (collectively,
`
`the “Sony Defendants”), OmniVision Technologies, Inc. (“OmniVision”), Apple Inc. (“Apple”),
`
`Samsung Electronics Co., Ltd., Samsung Electronics America, Inc., Samsung Semiconductor,
`
`Inc., and Samsung Telecommunications America, LLC (collectively, the “Samsung
`
`Defendants”) submit this brief in support of their proposed constructions of claim terms from
`
`U.S. Patent No. 5,591,678 (the “’678 Patent”).
`
`II.
`
`THE LEGAL STANDARD FOR CLAIM CONSTRUCTION
`
`The claims of a patent define the invention, and courts generally give claims their
`
`ordinary and customary meaning, measured as of the patent’s effective filing date. Phillips v.
`
`AWH Corp., 415 F.3d 1303, 1312-13 (Fed. Cir. 2005) (en banc). Claims should be interpreted in
`
`the same manner for infringement and validity determinations. Amgen Inc. v. Hoechst Marion
`
`Roussel, Inc., 314 F.3d 1313, 1330 (Fed. Cir. 2003). To determine the meaning of claims, courts
`
`start by considering intrinsic evidence: the language of the claim itself, the specification, and the
`
`patent’s prosecution history. Markman v. Westview Instruments, Inc., 52 F.3d 967, 979 (Fed.
`
`Cir. 1995) (en banc), aff'd, 517 U.S. 370 (1996).
`
`The claims themselves provide substantial guidance in determining the meaning of
`
`particular claim terms. Phillips, 415 F.3d at 1314. Claim terms must be examined in the context
`
`of the claims in which they are used and other claims in the patent, both asserted and unasserted.
`
`Id. “A claim construction that gives meaning to all the terms of the claim is preferred over one
`
`that does not do so.” Merck & Co., Inc. v. Teva Pharms. USA, Inc., 395 F.3d 1364, 1372 (Fed.
`
`
`
`-1-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 5 of 36 PageID #: 2089
`
`Cir. 2005). Thus, courts should avoid claim constructions that render superfluous one or more
`
`claim terms. Id.
`
`The claims must be read in the context of the specification of which they are a part.
`
`Phillips, 415 F.3d at 1315. The specification “is the single best guide to the meaning of a
`
`disputed term” and, as such, usually is dispositive of a claim’s meaning. Id. at 1321. The
`
`specification may reveal, either expressly or impliedly, a special definition given to a claim term
`
`by the patentee, in which case the special definition governs. Id. at 1316.
`
`Courts also look to the prosecution history of a patent to shed light on the meaning of its
`
`claims. Id. at 1317; Markman, 52 F.3d at 980. Although not dispositive, statements made during
`
`prosecution can serve as evidence of how the ordinarily skilled artisan would have interpreted a
`
`disputed claim term. Salazar v. Proctor & Gamble Co., 414 F.3d 1342, 1347 (Fed. Cir. 2005).
`
`In most situations, courts need only analyze intrinsic evidence to resolve ambiguity in a
`
`disputed claim term. But courts may admit and rely on extrinsic evidence when doing so would
`
`help educate the court regarding the field of the invention or help the court determine what a
`
`person of ordinary skill would understand claim terms to mean. Phillips, 415 F.3d at 1319. The
`
`Federal Circuit has cautioned, however, that “extrinsic evidence in general [is] less reliable than
`
`the patent and its prosecution history,” and therefore cannot contradict the meaning suggested by
`
`the intrinsic evidence. Id. at 1318, 1324.
`
`III.
`
`INTRODUCTION TO THE CLAIMED TECHNOLOGY
`
`The ’678 patent is directed to manufacturing techniques for semiconductor devices.
`
`Specifically, it describes a manufacturing technique that stacks two-dimensional microelectronic
`
`circuits in a third dimension. Ex. 1, ’678 Patent, Col. 1:66-2:2. The patent explains that
`
`conventional manufacturing operations build circuit elements at or near an exposed surface of
`
`the wafer layer of a substrate. Id. Stacking could not be performed with traditional substrate
`
`
`
`-2-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 6 of 36 PageID #: 2090
`
`structures because the structures were too thick to make openings, called “vias,” through the
`
`substrates to make electrical connections among the stacked circuits. Id., Cols. 2:59-3:5.
`
`Additionally, the substrates could not be removed because the circuit elements themselves could
`
`not be handled in thin form. Id. The patent proposes to manufacture circuit elements on a first
`
`substrate with a three-layer structure, which allows circuit elements to be transferred from the
`
`first substrate to a second substrate to achieve three-dimensional stacking. Id., Col. 2:5-10.
`
`Importantly, the three-dimensional
`
`microelectronic devices are prepared using
`
`well-established, inexpensive processing
`
`techniques for two-dimensional circuits. Id.
`
`The patent proposes a manufacturing
`
`process as illustrated in FIG. 1, shown here.
`
`The first step in the process, labeled 20,
`
`furnishes a three-layer substrate 40, which
`
`includes an etchable layer 42 (blue), an etch-
`
`stop layer 44 (green) and a wafer layer 46
`
`(yellow). The second step, labeled 22, forms a
`
`The ‘678 Patent, FIG. 1 (annotated)
`
`microelectronic circuit element 50 (purple) in the wafer layer 46. As shown, the microelectronic
`
`circuit element 50 is formed in the exposed side of the wafer layer 46, the surface that faces
`
`away from the etch-stop layer 44. Id., Col. 4:37-52. The microelectronic circuit element 50 may
`
`be of any type and may include many layers of metals, semiconductors, insulators and the like; it
`
`may include active devices or passive structure. Id.
`
`
`
`-3-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 7 of 36 PageID #: 2091
`
`The third step, labeled 24, attaches a second substrate 58 (orange) to the microelectronic
`
`circuit element 50 and the first substrate 40. The second substrate 58 covers the exposed surface
`
`of the wafer layer 46 and the circuit element 50. The second substrate 58 can be attached in any
`
`manner so long as it does not damage the pre-existing circuit element 50. Id., Col. 5:30-33.
`
`Optionally, the second substrate 58 may include its own circuit elements, and electrical
`
`connections may be created between the microelectronic circuit elements of the first and second
`
`substrates 40, 58 when the second substrate 58 is attached to the first substrate 40. Id., Col. 3:6-
`
`12.
`
`Once the circuit element 50 is supported by the second substrate 58, the etchable layer 42
`
`of the first substrate 40 may be removed, as shown in step 26 (the fourth step in the process). Id.,
`
`Col. 3:12-14. The etchable layer 42 is etched away down to the etch-stop layer 44, which
`
`exposes the etch-stop layer 44. Id., Col. 6:4-5. An etchant is chosen to attack the etch-stop layer
`
`44 at a much lower rate than the etchable layer 42, thereby stopping the etching process. Id.,
`
`Col. 3:15-18.
`
`Figure 1 illustrates other operations in steps 28 and 30 that are not recited in the asserted
`
`claims. In step 28, backside electrical connections 56 may be formed through the etch-stop layer
`
`44. These backside connections 56 connect to the wafer layer 46 from a different side than the
`
`exposed side in which the microelectronic circuit element 50 was formed, back in step 22. Id.,
`
`Col. 6:10-43. In step 30, the device is completed.
`
`IV. ARGUMENT
`
`Raytheon’s proposed constructions, if applied, would divert the claims away from the
`
`patent’s most basic teachings and the claims’ plain meanings. In Raytheon’s view, “layers” are
`
`not layers, layers “overlying” each other are not separate, and “etch-stops” do not stop etching.
`
`Raytheon’s proposals do not apply plain meaning constructions.
`
`
`
`-4-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 8 of 36 PageID #: 2092
`
`The patent’s teachings are straightforward: A microelectronic circuit element is formed
`
`on a special, three-layer first substrate for use in three-dimensional stacking. The
`
`microelectronic circuit element is formed in the top layer, the “wafer,” and then the first
`
`substrate is attached to a second substrate. The second substrate supports the microelectronic
`
`circuit element while the bottom layer of the first substrate, an “etchable layer,” is removed. The
`
`etchable layer is etched down to an intermediate layer: an “etch -stop layer” that has a much
`
`lower etch rate and eventually stops the etching process. Then the wafer layer (and, if desired,
`
`the etch-stop layer) is processed for stacking. The claims’ language tracks these basic teachings.
`
`It should not be interpreted in any other manner.
`
`Below, the Defendants review the disputed terms and demonstrate why, based on the
`
`terms’ usage within the asserted claims, the Defendants’ constructions are correct.
`
`A.
`
`Order of the Recited Steps
`
`DEFENDANTS’ PROPOSAL
`
`RAYTHEON’S PROPOSAL
`
`The steps of independent claims 1 and 13 must
`be performed in the order in which they are
`recited
`
`No construction necessary. Plain and ordinary
`meaning.
`
`term requires
`this
`the Court believes
`If
`construction, the Court should construe that
`each step is started before the step of etching
`
`
`
`The parties dispute whether the recited steps must be performed in the order in which
`
`they are recited in the claim: Defendants say yes, Raytheon says not really. The Federal Circuit
`
`set forth a two-part test to determine whether an order of steps is required. Altiris, Inc. v.
`
`Symantec Corp. 318 F.3d 1363, 1369-70 (Fed. Cir. 2003). First, courts look “to the claim
`
`language to determine if, as a matter of logic or grammar, [the steps] must be performed in the
`
`order written.” Id. at 1369; see also Mantech Envtl. Corp. v. Hudson Envtl. Servs., Inc., 152 F.3d
`
`1368, 1375-76 (Fed. Cir. 1998). If the logic and grammar do not dictate an order, courts then
`
`
`
`-5-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 9 of 36 PageID #: 2093
`
`“look to the rest of the specification to determine whether it directly or implicitly requires such a
`
`narrow construction.” Altiris, 318 F.3d at 1370 (internal quotations omitted). Here both inquiries
`
`demonstrate that the recited steps must be performed in order.
`
`The claims’ plain language demonstrates that the steps must be performed in their recited
`
`order. The language of each step describes a process that builds upon the structure developed by
`
`the immediately preceding step. For example, the furnishing step must precede the forming step
`
`because the forming step refers to structures that are established by the furnishing step. Ex.
`
`1,’678 Patent, Col. 8:7-9. The claims expressly require the microelectronic circuit element to be
`
`formed “in the exposed side of the wafer of the first substrate,” which is “opposite to the side
`
`overlying the etch-stop layer.” Id., Col. 8:10-12. The forming step cannot occur unless the
`
`furnishing step already has been performed such that the wafer layer and the etch-stop layer
`
`already exist. And, because the “exposed side of the wafer” will not be exposed once the
`
`attaching step is performed, the forming step must precede the attaching step. Id., Col. 8:10-14.
`
`Thus, the claims’ language describes an ordered sequence of operations. See Apple Inc. v.
`
`Motorola, Inc., 757 F.3d 1286, 1309 (Fed. Cir. 2014) (a claim’s reference to elements formed by
`
`predecessor steps—“’the’ codes”—naturally suggests the codes are fully formed before a
`
`subsequent multiplying step is performed).
`
`Raytheon’s expert, Dr. Buckman, recognized that the claim language imposes a logical
`
`order:
`
`Q. Okay. But a person of ordinary skill reading the ’678 patent would understand the
`result of the furnishing a first substrate step in claim 1, the method claim, would
`be what is illustrated at stage 20 of figure 1, correct?
`
`
`A. A person of ordinary skill in the art would understand that the -- reading that first
`element of claim 1, that it would generally look like what’s depicted in 20. It
`might or might not have a little v or a little hole 48 in a particular spot, but it
`would have the three layers.”
`
`
`
`-6-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 10 of 36 PageID #: 2094
`
`
`Ex. 2, Buckman Dep., 40:10-21 (emphasis added).
`
`Q. And so that wafer layer in the first substrate must exist prior to the
`forming of the microelectronic circuit element of the second step of claim
`1, correct?
`
`A. The wafer layer would have to at least exist. There might conceivably be
`situations where the formation of the circuit could include something
`that’s not in the layer. That would still preserve the basic order of the
`steps.
`
`Id., at 43:6-17 (emphasis added).
`
`Q. A person of ordinary skill in the art would understand that when the
`second substrate is attached to the first substrate, there no longer would be
`an exposed side of the wafer, correct?
`
`A. Once it’s attached, there is no longer an exposed side of the wafer.
`
`Id., at 53:22-54:17 (emphasis added). Thus, the claims’ express language describes an order in
`
`which these steps must be performed. See Ex. 1, ‘678 Patent, Cols. 8:5-16; 9:14-27. See also,
`
`Apple, 757 F.3d. at 1309.
`
`Figure 1 of the specification (p. 4 above), which shows an ordered series of steps,
`
`confirms this construction. The patent teaches that Figure 1 “is a diagrammatic process flow
`
`diagram for the approach of the invention, with the structure at each stage of fabrication
`
`indicated schematically.” Id., Col. 3:48-50 (emphasis added). This process flow, with
`
`unidirectional arrows connecting each stage to the next stage, shows that the stages of the
`
`invention are performed in the exact same order as the recited steps of claims 1 and 13 (e.g.,
`
`“furnish”  “form”  “attach”  “remove etchable layer”). See also Ex. 2, Buckman Dep., at
`
`31:15-18 (“A person of ordinary skill in the art is going to understand that the -- that the arrows
`
`represent a general indication of the order in which these steps are at least undertaken.”). The
`
`importance of order is further emphasized throughout the specification, as the following excerpts
`
`demonstrate:
`
`
`
`-7-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 11 of 36 PageID #: 2095
`
`The present invention provides an approach for fabricating microelectronic
`devices that permits three-dimensional manipulations and fabrication steps
`with two-dimensional devices already deposited upon a wafer substrate. Ex.
`1, ‘678 Patent, Col. 2:6-9 (emphasis added).
`
`Referring to FIG. 1, the present invention is practiced by first providing a first
`substrate 40, numeral 20. The first substrate 40 includes an etchable layer 42,
`an etch-stop layer 44 grown upon and overlying the etchable layer 42, and a
`wafer layer 46 bonded to and overlying the etch-stop layer 44. Id., Col. 3:64-
`4:2 (emphasis added).
`
`In the present approach, after initial circuit element fabrication on a first
`substrate structure, the electrical circuit element is transferred to a second
`substrate structure. Id., Col. 3:6-8 (emphasis added).
`
`The second substrate 58 is attached by any appropriate technique, which must
`be chosen so that the attachment procedure does not damage the pre-
`existing structure such as the microelectronic circuit element 50. Id., Col.
`5:29-32 (emphasis added).
`
`With the circuit element thus supported, the etchable portion of the first
`substrate is removed by etching, down to the etch-stop layer. Id., Col. 3:12-14
`(emphasis added).
`
`Thus, the specification demonstrates that the order of operations is a necessary feature of the
`
`patent. Apple, 757 F.3d. at 1309-10.
`
`Raytheon fails to address the intrinsic evidence cited above that describes an order of
`
`operations among the method steps. Rather, Raytheon supports its construction largely with the
`
`ipse dixit of its expert; but this cannot be used to contradict the teachings of the patent itself. See
`
`Syncpoint Imaging, LLC v. Nintendo of America Inc., Case No. 2:15-cv-00247 (E.D. Tex. Jan 5,
`
`2016) (citing Phillips, 415 F.3d at 1318 for the proposition that “conclusory, unsupported expert
`
`assertions as to a term’s definition are unhelpful to a court”).
`
`Raytheon’s proposal, that the steps “be started” in order but not necessarily finished in
`
`order, would allow the claims to cover processes that conflict directly with the language of the
`
`claims and that are not contemplated by the ’678 patent. For example, Raytheon’s construction
`
`may be an attempt to cover a scenario where microelectronic circuit elements are formed in a
`
`
`
`-8-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 12 of 36 PageID #: 2096
`
`substrate that does not have the three-layer structure required by the claims, and one of the
`
`required layers such as an etch-stop is created after the substrate is attached to a second substrate.
`
`The claim language does not permit this to occur, as noted earlier. Because the claims require
`
`that the microelectronic circuit element be formed on the “exposed” side of the wafer layer that
`
`is “opposite” to the side “overlying” the etch-stop layer, the etch-stop layer must be in place first.
`
`Ex. 1,’678 Patent, Col. 8:10-12. Raytheon’s construction also defies the patent’s teaching that
`
`well-established, inexpensive manufacturing techniques, which operate at the surface of
`
`structures and not the interior of structures, are to be used. Id., Cols. 1:14-17, 2:9-14. These
`
`surface-oriented techniques no longer can operate at the surface of a wafer if, for example, that
`
`surface has already been attached to something else—here, the second substrate.
`
`Moreover, the patent has no teaching that would enable someone to form the claims’
`
`features—for example, the etch-stop layers or microelectronic circuit elements—in the interior of
`
`any structure. Although Dr. Buckman speculated at his deposition that there were “possible
`
`techniques, like ion implantation” that might form buried structures, Ex. 2, Buckman Dep.,
`
`46:17-47:4 (emphasis added), he did not suggest that any such techniques were known to those
`
`of skill in 1993 (Raytheon's asserted priority date). More importantly, he made no attempt to
`
`reconcile his conjecture with the patent’s teachings that well-known, surface oriented
`
`manufacturing techniques are to be used. Ex. 1, ‘678 Patent, Cols. 1:14-17, 2:9-14.
`
`The Court should reject Raytheon’s construction and should instead apply the logic
`
`present in the claim language, which describes the method steps being performed in the order in
`
`which they are recited.
`
`
`
`-9-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 13 of 36 PageID #: 2097
`
`B.
`
` “First Substrate”
`
`DEFENDANTS’ PROPOSAL
`
`RAYTHEON’S PROPOSAL
`
`A structure that initially has at least three
`distinct material layers.
`
`A first solid support material.
`
`
`
`The parties do not dispute that the first substrate has three layers: an etchable layer, an
`
`etch-stop layer, and a wafer. See, Ex. 1, ’678 Patent, Col. 8:7-9; Raytheon’s Opening Claim
`
`Construction Br. 6 (“Raytheon Br.”). But the parties do dispute: (1) whether these layers must
`
`be present initially before microelectronic circuit elements are formed, and (2) whether these
`
`layers must be distinct from each other. Based on the term’s usage within the claims, a proper
`
`construction of “first substrate” includes these properties.
`
`On the first dispute, both independent claims recite that the first substrate has an etchable
`
`layer, an etch-stop layer overlying the etchable layer, and a wafer overlying the etch-stop layer.
`
`As discussed above, the claims also describe the relative orientation of these layers in the
`
`furnished substrate as reference points for the latter method steps. For example, claim 1 recites
`
`that the microelectronic circuit element is formed “in [an] exposed side of the wafer . . .
`
`opposite to the side overlying the etch-stop layer.” Claim 13 similarly refers to forming a
`
`microelectronic circuit element in a “front surface” of the wafer, where the front surface is
`
`defined as a “surface not contacting the silicon dioxide [etch-stop] layer.” Id., Col. 9:16-22.
`
`Further, both claims refer to etching the etchable layer “down to the etch-stop layer.” Id., Col.
`
`8:15-16; 9:25-27. These recitations demonstrate that when the first substrate is initially
`
`furnished it includes the three layers.
`
`The specification also confirms that the first substrate, when it is first furnished, must
`
`have at least three distinct material layers. The specification expressly states that the “present
`
`invention is practiced by first providing a first substrate 40, numeral 20.” Ex. 1, ’678 Patent,
`
`
`
`-10-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 14 of 36 PageID #: 2098
`
`Cols. 3:64-65 (emphasis added). See also 2:43-48 (“In a preferred approach to practicing the
`
`invention, a method of fabricating a microelectronic device comprises the steps of furnishing a
`
`first substrate having a silicon etchable layer, a silicon dioxide etch-stop layer overlying the
`
`silicon layer, and a single-crystal silicon wafer overlying the etch-stop layer.”). The first
`
`substrate 40 identified in numeral 20 is expressly shown and defined as having three distinct
`
`layers (etchable layer 42, etch-stop layer 44 and wafer layer 46). Id., Cols. 3:64-4:1, Fig. 1
`
`(numeral 20). As discussed earlier, furnishing a first substrate must be the first step in the
`
`fabrication process; the latter modifications to the first substrate cannot occur unless the substrate
`
`first is present with all of its constituent layers.
`
`The patent explains the first substrate can be furnished in several ways. In one case, the
`
`three-layer substrate can be purchased commercially. Alternatively, the first substrate can be
`
`fabricated by forming a silicon dioxide etch-stop layer 44 on a piece of bulk silicon 42, then
`
`bonding or growing a wafer layer 46 on top of the etch-stop layer 44. Id., Col. 4:2-37. In all
`
`cases, however, the first substrate is furnished with its component layers before microelectronic
`
`circuit elements are formed. The patent contains no teaching of any technique that would permit
`
`someone of skill to furnish these layers after or even during performance of the subsequent steps.
`
`And Raytheon has provided no evidence (other than conclusory opinions from its experts) to
`
`demonstrate that it was feasible to do so at the time the patent was filed.
`
`The prosecution history also supports that the first substrate must have the three recited
`
`layers. During prosecution, the Patent Office initially rejected the application because it found
`
`that a prior art reference called Riseman had a first substrate. In response, the patentee declared
`
`that Riseman did not have such a substrate:
`
`Riseman, U.S. Patent No. 4,169,000, differs from the present invention in a
`very fundamental aspect. In the present invention, the microelectronic circuit
`
`
`
`-11-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 15 of 36 PageID #: 2099
`
`is initially formed on a first substrate which has an etchable layer, an etch-
`stop layer and a wafer, the microelectronic circuit being formed in the
`exposed side of the wafer, that is, the side of the wafer opposite to the side
`which overlies the etch-stop layer. In contrast, in Riseman, the
`microelectronic circuit is formed in a substrate 10 which does not have the
`construction specified in the present invention, i.e., the etchable layer, an
`etch-stop layer and a wafer overlying the etch-stop layer.”
`
`See Ex. 3, June 6, 1994 Amendment, at RAY00000069 (emphasis added). Thus, the patentee
`
`advocated that the first substrate has three distinct material layers recited in the claims in order to
`
`overcome the prior art and obtain the ’678 patent.
`
`Raytheon ignores the claim language cited above, the specification, and the prosecution
`
`history when it argues against Defendants’ construction. Further, Raytheon fails to explain how,
`
`in 1993, a person of ordinary skill in the art would know how to form the first substrates’
`
`features, particularly an interior etch stop layer, after or during performance of the claims’ latter
`
`manufacturing steps. Accordingly, the Court should reject Raytheon’s proposal.
`
`On the second dispute, the claim language indicates these layers are distinct from each
`
`other. The claims refer to them as distinct elements—“etchable layer,” “etch-stop layer” and
`
`“wafer”—using language that indicates they have distinct roles in the claimed process. The
`
`wafer provides a structure for forming microelectronic circuit elements, the etch-stop layer stops
`
`an etching process, and the etchable layer is etched away. Moreover, the claim language assigns
`
`these elements distinct locations within the first substrate by describing these layers as
`
`“overlying” each other.
`
`The specification confirms this construction. First, the patent shows the etchable layer 42
`
`(blue), the etch-stop layer 44 (green), and the wafer 46 (yellow) as distinct layers:
`
`
`
`-12-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 16 of 36 PageID #: 2100
`
`The ’678 Patent, FIG. 1, steps 20-26 (annotated)
`
`
`
`The layers are provided at distinct spatial locations within the first substrate, again, with an
`
`“overlying” relationship. Ex. 1, ’678 Patent, Cols. 3:65-4:1. They are made of distinct materials:
`
`The etchable layer is silicon, the etch-stop layer is silicon dioxide, and the wafer is single crystal
`
`silicon. Id., Col. 4:3-15. And because the layers are distinct materials, an etchant can be
`
`selected “that readily etches the etchable layer but has a much lower etching rate for the etch-
`
`stop layer.” Id., Col. 3:16-18. The use of distinct layers and different materials is the foundation
`
`of the invention disclosed by the ’678 patent. Thus, the plain meaning construction set forth by
`
`the Defendants is consistent with the specifications.
`
`Raytheon’s failure to recognize the layers as distinct from each other is based on a failure
`
`to read the “first substrate” in the proper context within the claims. Raytheon also fails to
`
`acknowledge that the claims assign different roles to each of the layers, which further supports a
`
`construction that they are distinct.
`
`Thus, the Court should construe the term “first substrate” to mean “a structure that
`
`initially has at least three distinct material layers.”
`
`C.
`
`“Etch-Stop Layer,” “Etchable Layer” and “Etching Away the Etchable
`Layer . . . Down to the Etch-Stop Layer”
`
`The related terms “etch-stop layer,” “etchable layer,” and “etching away the etchable
`
`layer . . . down to the etch-stop layer” are discussed together.
`
`
`
`-13-
`
`
`
`

`
`Case 2:15-cv-00341-JRG-RSP Document 112 Filed 01/29/16 Page 17 of 36 PageID #: 2101
`
`DEFENDANTS’ PROPOSAL
`
`RAYTHEON’S PROPOSAL
`
`“ETCH-STOP LAYER”
`
`A layer of the first substrate, distinct from the
`etchable layer and the wafer, which stops the
`etching process by virtue of it having a lower
`etch rate than the etchable layer.
`
`
`
`A portion of the first substrate that is etched
`less readily, relati