Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 1 of 14 PageID #: 1482
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`IN THE UNITED STATES DISTRICT COURT
`FOR THE EASTERN DISTRICT OF TEXAS
`MARSHALL DIVISION
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`PLAINTIFF PARTHENON UNIFIED MEMORY ARCHITECTURE LLC’S
`REPLY CLAIM CONSTRUCTION BRIEF
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`Case No. 2:15-cv-225-JRG-RSP
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`§
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`§
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`PARTHENON UNIFIED MEMORY
`ARCHITECTURE LLC,
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`Plaintiff,
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`v.
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`ZTE CORP., ZTE USA, INC. and
`ZTE (TX), INC.,
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`Defendants.
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`

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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 2 of 14 PageID #: 1483
`Case 2:l5—cv—OO225—JRG—RSP Document 64 Filed 10/05/15 Page 2 of 14 Page|D #: 1483
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`TABLE OF CONTENTS
`TABLE OF CONTENTS
`Introduction ......................................................................................................................... 1
`Introduction ....................................................................................................................... .. 1
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`Terms for Construction ....................................................................................................... 1
`Terms for Construction ..................................................................................................... .. 1
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`I.
`I.
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`II.
`II.
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`A.
`A.
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`B.
`B.
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`C.
`C.
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`D.
`D.
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`E.
`E.
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`F.
`F.
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`G.
`G.
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`H.
`H.
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`I.
`I.
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`“bus” ....................................................................................................................... 1
`“bus” ..................................................................................................................... .. 1
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`“memory bus” ......................................................................................................... 4
`“memory bus” ....................................................................................................... .. 4
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`“in real time” and related terms .............................................................................. 5
`“in real time” and related terms ............................................................................ .. 5
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`“fast bus” ................................................................................................................. 6
`“fast bus” ............................................................................................................... .. 6
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`“coupled,” “coupleable” and “coupling” ................................................................ 6
`“coupled,” “coupleable” and “coupling” .............................................................. .. 6
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`“directly supplied” and “directly supplies” ............................................................. 7
`“directly supplied” and “directly supplies” ........................................................... .. 7
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`“arbiter” terms ......................................................................................................... 8
`“arbiter” terms ....................................................................................................... .. 8
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`“control circuit” ...................................................................................................... 9
`“control circuit” .................................................................................................... .. 9
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`“monolithically integrated into” and “integrated into” ......................................... 10
`“monolithically integrated into” and “integrated into” ....................................... .. 10
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 3 of 14 PageID #: 1484
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`I.
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`INTRODUCTION
`PUMA’s proposed constructions are rooted in both the intrinsic and extrinsic evidence and
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`are consistent with the previous claim construction order signed by Judge Leonard Davis relating
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`to the asserted patents. Together, PUMA’s constructions strive to promote clarity and avoid jury
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`confusion while giving effect to the claim language’s full scope. In contrast, ZTE’s constructions
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`work against those interests by incorporating terms that appear nowhere in the asserted patents.
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`For the reasons below, ZTE’s constructions should be rejected.1
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`II.
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`TERMS FOR CONSTRUCTION
`“bus”
`A.
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`Term
`“bus”
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`PUMA’s Proposal
`No construction necessary.
`Alternatively: “a signal line or a set
`of associated signal lines to which a
`number of devices are coupled and
`over which information may be
`transferred between them”
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`Defendants’ New Proposal
`“a signal line or set of associated
`signal lines to which a number of
`devices are connected and over
`which information may be
`transferred by only one device at a
`time”
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`In response to PUMA’s Opening Brief, ZTE has removed the word “directly” from its
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`proposed construction, and the parties’ only remaining dispute is over ZTE’s proposed requirement
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`that “information may be transferred by only one device at a time.”
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`ZTE’s construction is problematic because it would read out common bus technologies like
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`split-transaction buses and the Mercury Raceway bus. With respect to split-transaction buses, ZTE
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`is admits that multiple devices can use a split-transaction bus at the same time to transfer
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`1 For many of the disputed terms, PUMA notes that ZTE explicitly incorporates by reference the
`briefing and arguments made by the defendants in related Case Nos. 2:14-cv-690 and/or 2:14-cv-
`902 in lieu of ZTE submitting its own briefing. Out of concern for the local rules and this Court’s
`page limits, PUMA has endeavored to confine its own responses to this Reply Brief. However, to
`the extent the Court considers briefing and arguments that have been incorporated by reference,
`PUMA respectfully incorporates by reference its own corresponding briefing and arguments.
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 4 of 14 PageID #: 1485
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`information: “while the request is being worked on, other devices can transmit on the bus.” See
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`ZTE Responsive Brief, Dkt. 60 at 9. As a result, ZTE’s construction would read out split-
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`transaction buses. However, ZTE attempts to escape this conclusion by differentiating between
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`“request” transactions and “response” transactions and suggesting that a split-transaction bus can
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`only handle one of each type of transaction at a given time. Even if true, though, ZTE’s
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`construction does not reflect this distinction, and the concept of “request” transactions and
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`“response” transactions are not discussed in the asserted patents. As a result, ZTE’s interpretation
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`of its own proposed construction would only add to the risk of Jury confusion.
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`Moreover, ZTE’s attempt to distinguish split-transaction buses does not apply to the
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`Mercury Raceway bus: even ZTE admits that its proposed construction would read out this type
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`of bus. See ZTE Responsive Brief, Dkt. 60 at 10 (stating that “PUMA is correct that the term ‘bus’
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`as used in the patents-in-suit would not read on Mercury Raceway”). Normally, such an admission
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`would be the end of the dispute. The patents use the term “bus” broadly and the patentees did not
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`restrict or disclaim any particular type of bus. As a result, ZTE’s attempt to carve out a non-
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`infringement defense by restricting the term “bus” to only certain types of buses should be rejected.
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`In response, ZTE argues that the Mercury Raceway bus is not a bus. However, persons of
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`ordinary skill in the art disagree with ZTE. The exhibits submitted by PUMA repeatedly refer to
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`the Mercury Raceway bus as a bus. See Dkt. 56, Ex. N at 203 (noting that “some currently
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`available choices for a data bus” include the “RACEway (Mercury Computer)”); Dkt. 56, Ex. M
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`at 31 (stating that “[t]he Mercury Raceway bus is an important part of the IFP architecture” and
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`that “[t]he P2 connector is also used to propagate the Raceway bus from board to board”). Because
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`ZTE cannot refute those exhibits, ZTE instead focuses entirely on just one of PUMA’s exhibits.
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`However, Exhibit O does not say that the Raceway bus is not a bus, and the portion quoted by
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 5 of 14 PageID #: 1486
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`ZTE actually supports PUMA’s position. The document states that the Mercury Interlink modules
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`transform the topology from “a single transaction bus to a scalable real-time fabric.” In other
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`words, the document is distinguishing between two types of buses: “single transaction buses” and
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`“real-time fabrics.” Otherwise, under ZTE’s argument, the phrase “single transaction” would be
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`entirely redundant because all buses would presumably be “single transaction” buses.
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`Indeed, the technical documents from Qualcomm that are central to this case refer to a
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`fabric as a type of bus. As mentioned in PUMA’s Opening Brief, the defendants in related Case
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`No. 2:14-cv-902 represented to the Court during the claim construction hearing that a fabric was
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`distinct from a bus. In response, PUMA informed the Court that even Qualcomm’s own
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`documentation refers to fabrics as buses. See, e.g., Dkt. 56, Ex. X at 67 (noting that there are
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`“three buses that span the entire MSM device” and listing the “system fabric,” the “applications
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`fabric” and the “system fast peripheral bus.”) (shown at the hearing).
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`PUMA raises this evidence for the simple purpose of assuring the Court that persons of
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`ordinary skill in the art have always understood the term “bus” to be broad and inclusive. From
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`the Mercury Raceway bus to Qualcomm’s system fabric and applications fabric, persons of
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`ordinary skill in the art have not restricted the term “bus” in the manner urged by ZTE. Instead,
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`the concept of a “bus” has always included various bus technologies like split-transaction buses
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`and the Mercury raceway bus. Because ZTE’s construction would unduly restrict this term, the
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`Court should reject it and adopt PUMA’s proposed construction.
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 6 of 14 PageID #: 1487
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`B.
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`“memory bus”
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`Term
`“memory bus”
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`PUMA’s Proposal
`“a signal line or a set of associated
`signal lines to which a number of
`devices, including a memory, are
`coupled and over which information
`may be transferred”
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`Defendants’ Proposal
`“a bus that connects directly with a
`memory”
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`Given the common understanding of the term “bus,” a person of ordinary skill in the art
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`would understand that a “memory bus” is a bus that is coupled to a memory. As discussed in
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`PUMA’s Opening Brief, ZTE’s position that the memory is connected “directly” to the bus would
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`read out common buses that include intervening components or interfaces and should be rejected.
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`PUMA also disagrees with ZTE’s purported reasons for demanding a construction. In the
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`earlier claim construction proceeding involving the HTC and LG defendants, HTC and LG falsely
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`insinuated to this Court that PUMA was attempting to combine an ISA bus and a PCI bus to form
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`one bus. In response, PUMA immediately and affirmatively disclaimed any such argument as a
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`red herring. Similarly, ZTE now suggests that PUMA is trying to argue that “every bus” in a
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`computer is a “memory bus.” Again, this is not true. If a bus in a computer system is not used to
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`send data to or from a memory, PUMA recognizes that it would not logically be a memory bus.
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`However, to the extent ZTE intends to argue that a particular bus is not a memory bus—even if
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`the bus is used to send data to or from a memory—because of some intervening switch or interface,
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`PUMA contends that such an argument is not supported by the intrinsic evidence or the
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`understanding of a person of ordinary skill in the art. As a result, the Court should adopt PUMA’s
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`proposed construction for the term “memory bus.”
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`C.
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`“in real time” and related terms
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`Term
`“in real time”
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`PUMA’s Proposal
`“fast enough to keep up with an
`input data stream”
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`Defendants’ New Proposal
`Indefinite.
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`ZTE has dropped its proposed alternative construction of the term “real time.” Instead,
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`ZTE now rests solely on its argument that the term is indefinite. However, two different courts in
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`this District—including this Court—have already found the term “real time” as used in the asserted
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`patents to be definite and construed it in the manner proposed by PUMA.
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`ZTE does not make its own arguments in support of its position and instead incorporates
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`by reference the arguments made by Samsung in related Case No. 2:14-cv-902. For the same
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`reasons raised by PUMA in that sequence of briefing, ZTE’s argument is incorrect.
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`First, Samsung did not dispute that the term “real time” can have a definite meaning and
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`did not dispute that the core language of PUMA’s proposed construction is proper. Indeed, at the
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`earlier claim construction hearing, Samsung did not focus on its indefiniteness argument and
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`appeared to concede that at least some form of construction would be proper. Instead, Samsung’s
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`main complaint focused on the impact of latency. However, whether a system is “fast enough to
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`keep up with an input data stream” already subsumes concepts like bandwidth, latency and any
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`other issue that would negatively impact the amount of data that could be transmitted.
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`Second, Samsung’s original indefiniteness argument came from a misreading of the
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`prosecution history. Contrary to Samsung’s argument, the patentees did not distinguish Gulick by
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`narrowing the ordinary scope of “real time.” Instead, the patentees distinguished Gulick on the
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`basis that the PCI bus—as used in the specific context of Gulick—was insufficient for real time
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`performance. See Dkt. 56, Ex. J at ¶ 26. This misunderstanding is readily apparent from Figure
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`1 of Gulick. As shown below, Gulick includes a PCI bus (shown in blue) in addition to a real-
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 8 of 14 PageID #: 1489
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`time bus (shown in red). See Dkt. 56, Ex. R, Fig. 1 (coloring added). Thus, Gulick itself represents
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`that the PCI bus it was using was insufficient to guarantee real time performance for its purposes,
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`which explains why an actual real time bus was required. Because ZTE relies wholely on
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`Samsung’s briefing, ZTE’s indefinitness argument should be rejected for the same reason.
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`D.
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`“fast bus”
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`Term
`“fast bus”
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`PUMA’s Proposal
`“bus with a bandwidth equal to or
`greater than the required
`bandwidth to operate in real time”
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`Defendants’ Proposal
`“bus with a bandwidth greater than
`the bandwidth required for the
`decoder to operate in real time”
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`PUMA’s construction of “fast bus” is the same definition that the patentee provided in the
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`asserted patents: “A fast bus 70 is any bus whose bandwidth is equal to or greater than the required
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`bandwidth.” Dkt. 56, Ex. B at 8:1–2 (emphasis added). Accordingly, PUMA submits that the
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`Court should adopt this construction.
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`E.
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`“coupled,” “coupleable” and “coupling”
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`Term
`a. “coupled”
`b. “coupleable”
`c. “coupling”
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`PUMA’s Proposal
`a. “directly or indirectly connected”
`b. “directly or indirectly connectable”
`c. “directly or indirectly connecting”
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`Defendants’ New Proposal
`“attached, resulting in an
`arrangement that includes no
`more than one bus”
`Alternatively: indefinite.
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`As explained in PUMA’s Opening Brief, the term “coupled” is commonly understood and
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`has routinely been construed by district courts to mean directly or indirectly connected. This
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`construction comports exactly with how the patentees used the term in the asserted patents, which
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`contain numerous examples of components being directly or indirectly coupled together.
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`In contrast, ZTE’s briefing incorporates by reference the same argument raised by HTC
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`and LG in related Case No. 2:14-cv-690. Relying entirely on that briefing, ZTE suggests that the
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`term “coupled” should be construed to mean “attached, resulting in an arrangement that includes
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`no more than one bus.” However, for the same reasons argued by PUMA in the related HTC/LG
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`matter, this construction directly conflicts with the examples and figures of the asserted patents.
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`For example, the ’789 Patent states that “Fig. 1c [reproduced below] shows a computer 25
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`containing a decoder 10, a main memory 168 and other typical components such as a modem
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`199, and graphics accelerator 188. The decoder 10 and the rest of the components are coupled
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`to the core logic chipset 190 through a bus 170.” Dkt. 56, Ex. A at 2:49–53 (emphasis added).
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`Looking at Figure 1c below, the modem 199 (shown in added blue) is “coupled” to the core logic
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`chipset 190 (shown in added red) through ISA bus 198 (shown in added green) and PCI bus 170
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`(shown in added purple), resulting in an “arrangement” that includes two buses. As a result, ZTE’s
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`construction conflicts with the specification and is improper.2
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`F.
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`“directly supplied” and “directly supplies”
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`Term
`“directly supplied/supplies”
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`PUMA’s Proposal
`“supplied/supplies without
`being stored in main memory
`for purposes of decoding
`subsequent images”
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`Defendants’ Proposal
`“supplied/supplies without
`intervening components”
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`2 ZTE suggests that if the Court construes the term “coupled” to mean a direct or indirect
`connection, that the term must be indefinite. However, ZTE does not provide any substantive
`argument in support of this position, and PUMA notes that such a construction is commonly
`applied by persons of ordinary skill in the art. As a result, ZTE has not shown that the term would
`not be understood with “reasonable certainty” by those skilled in the art.
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 10 of 14 PageID #: 1491
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`The term “directly supplied” concerns the system’s use of decompressed frames in the
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`context of video decoding and does not require the absence of “intervening components.” ZTE
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`does not submit its own arguments and instead incorporates by reference the arguments made in
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`the Samsung case. However, under ZTE’s construction, the embodiment illustrated in Figure 3 of
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`the ’194 Patent would be read out because of the intervening core logic chipset. Any frames
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`supplied from the Decoder/Encoder 80 (shown in blue) to the Display 182 (shown in red) would
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`necessarily need to pass through the intervening Core Logic Chipset 190 (shown in green). As a
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`result, ZTE’s construction is incorrect and should be rejected.
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`G.
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`“arbiter” terms
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`Term
`a. “arbiter”
`b. “arbitration
`circuit”
`c. “memory arbiter”
`d. “arbiter circuit”
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`PUMA’s Proposal
`“circuitry that uses a priority
`scheme to determine which
`requesting device will gain access”
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`Defendants’ Proposal
`“circuitry that uses a priority
`scheme to determine which
`requesting device will gain direct
`access”
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 11 of 14 PageID #: 1492
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`The term “arbiter” was previously construed by Judge Davis in the earlier litigation
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`involving STMicro and Motorola as “a device that use[s] a priority scheme to determine which
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`requesting device will gain access to the memory.” STMicroelectronics, 327 F. Supp. 2d at 710.
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`STMicro and Motorola, both sophisticated semiconductor corporations, jointly submitted the
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`above construction, and the term is used throughout the patents in this same manner. ZTE’s only
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`argument in response is that a “circuit is not an ‘arbiter’ with respect to two devices and a bus if
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`the data to be transmitted must traverse several other buses.” However, this statement does not
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`appear anywhere in the intrinsic evidence, and ZTE has declined to provide any explanation in
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`support of this argument. As a result, the Court should reject ZTE’s proposed construction.
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`H.
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`“control circuit”
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`Term
`“control circuit”
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`PUMA’s Proposal
`No construction necessary.
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`Defendants’ Proposal
`“an electronic control device that
`is separate from the CPU or
`processor and that interacts with
`the operating system”
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`As argued in PUMA’s Opening Brief, the Court does not need to construe “control circuit”
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`because the term is defined by the surrounding claim language. Again, ZTE declines to make its
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`own argument and instead incorporates by reference arguments made in the Samsung case.
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`However, ZTE’s added requirement that the control circuit be “separate” from the CPU ignores
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`the fact that multiple components “can be monolithically integrated as a single chip.” Dkt. 56, Ex.
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`I at 5:10–13 (stating that the “microcontroller 120, DMA engine 124, video decoding circuit 126,
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`audio decoding circuit 128, and memory 129 can be monolithically integrated as a single chip
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`130 for use with or in the computer system 100”). Because the claims only require that the control
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`circuit be “coupled to” the processor, which can be the case even if the components are
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`monolithically integrated as a single chip, ZTE’s construction should be rejected.
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 12 of 14 PageID #: 1493
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`I.
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`“monolithically integrated into” and “integrated into”
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`Term
`“monolithically integrated
`into” / “integrated into”
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`PUMA’s Proposal
`“formed on a single
`semiconductor chip with”
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`Defendants’ Proposal
`“formed within”
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`“monolithically integrated
`with” / “integrated with”
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`“formed on a single
`semiconductor chip with”
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`“formed within”
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`As discussed in PUMA’s Opening Brief, the term “monolithic” originates from the Greek
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`words monos ‘single’ and lithos ‘stone’ and refers to the fact that monolithically integrated
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`components are formed on a single semiconductor crystal or chip. As with the other terms, ZTE
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`declines to brief the issue itself and instead incorporates by reference the arguments made in the
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`Samsung case. Interestingly, however, ZTE seems to disagree with Samsung as to whether the
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`words “into” and “with” should result in different constructions of the above terms. For example,
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`Samsung argued that the construction “formed within” was appropriate for the version of the claim
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`term using “into” because the claims “explicitly differentiate between integrating components with
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`the decoder/encoder, and integrating components into the decoder/encoder.” See Case No. 2:14-
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`cv-902, Dkt. 86 at 31 (emphasis in original).
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`Although PUMA believes that its proposed construction is appropriate for both versions of
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`the “monolithically integrated” terms, PUMA respectfully submits that its construction is at least
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`proper for the terms “monolithically integrated with” and “integrated with.”
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 13 of 14 PageID #: 1494
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`Dated: October 5, 2015
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`Respectfully submitted,
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`/s/ Demetrios Anaipakos
`Demetrios Anaipakos
`Texas Bar No. 00793258
`danaipakos@azalaw.com
`Amir Alavi
`Texas Bar No. 00793239
`aalavi@azalaw.com
`Michael McBride
`Texas Bar No. 24065700
`mmcbride@azalaw.com
`Alisa A. Lipski
`Texas Bar No. 24041345
`alipski@azalaw.com
`Justin Chen
`Texas Bar No. 24074204
`jchen@azalaw.com
`AHMAD, ZAVITSANOS, ANAIPAKOS,
`ALAVI & MENSING P.C.
`1221 McKinney Street, Suite 3460
`Houston, TX 77010
`Telephone: 713-655-1101
`Facsimile: 713-655-0062
`
`T. John Ward, Jr.
`Texas Bar No. 00794818
`jw@wsfirm.com
`WARD & SMITH LAW FIRM
`P.O. Box 1231
`Longview, TX 75606-1231
`Telephone: 909-757-6400
`Facsimile: 909-757-2323
`
`ATTORNEYS FOR PLAINTIFF
`PARTHENON UNIFIED MEMORY
`ARCHITECTURE LLC
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`Case 2:15-cv-00225-JRG-RSP Document 64 Filed 10/05/15 Page 14 of 14 PageID #: 1495
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`CERTIFICATE OF SERVICE
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`The undersigned hereby certifies that all counsel of record who are deemed to have
`consented to electronic service are being served with a copy of this document via the Court’s
`CM/ECF system per Local Rule CV-5(a)(3) on October 5, 2015.
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`/s/ Michael McBride
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