Third Party Submission for Application USSN 14/259,011
`
`Patent No.:
`
`Inventor:
`
`Application No.:
`
`Filed:
`
`Document 1
`
`US Patent 8,238,116
`
`Eggerding et al.
`
`12/061,150
`
`April 2, 2008
`
`Application Publication Date:
`
`October 16, 2008
`
`Issue Date:
`
`August 7, 2012
`
`Concise Description:
`
`Document 1 was published as an application and as a patent prior to the earliest
`
`possible priority date of June 14, 2013 for the subject Application USSN 14/259,011.
`
`The subject Application USSN 14/259,011 is entitled "Multilayer Ceramic
`
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`
`a particular capacitor arrangement which results in a reverse geometry capacitor having
`
`relatively low inductance.
`
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`132
`
`z
`
`131
`
`.22
`
`111
`
`I‘m -,
`. 7 ....'.‘W'.‘ ‘
`y '..'.'A'...' ‘3
`‘I...’.‘r:'.___.___ ’.
`'I'...".."
`y I, " '
`
`’ I....'m.
`
`, mm;
`7 Inn-v..." A
`.I'lllu'Iu'il :
`
`FIG. 4
`
`1
`
`f6
`
`0
`
`Exhibit 2001
`
`PGR2017-00010
`SEM
`
`Page 1 of 48
`
`Page 1 of 48
`
`

`

`Examples from the specification of the subject Application USSN 14/259,011
`
`regarding such reverse geometry feature arrangement and resulting relatively low
`
`inductance are recited below re application Paragraphs [0050], and [0056] through
`
`[0061] (emphasis added):
`
`[0050] Referring to FIG. 1, in the multilayer ceramic capacitor according to
`an exemplary embodiment of the present disclosure, a 'length direction'
`refers to an 'L' direction, a 'width direction' refers to a 'W‘ direction, and a
`'thickness direction' refers to a 'T‘ direction. Here, the 'thickness direction'
`
`may be the same as a stacking direction in which dielectric layers are
`stacked.
`
`[0056] The first and second internal electrodes 121 and 122 may be
`disposed to face each other, having at least one of the dielectric layers
`111 interposed therebetween, and may be alternately exposed to the first
`or second side surface 85 or S6.
`
`[0057] The first and second internal electrodes 121 and 122 are
`alternately exposed to the first or second side surface S5 or 86, such that
`a reverse geometry capacitor [RGC] or low inductance chip capacitor
`(LICC[ may be obtained as described below.
`
`[0058] In a general multilayer ceramic electronic component, external
`electrodes may be disposed on opposing end surfaces of the ceramic
`body in a length direction thereof.
`
`[0059] In this case, when an alternative current (AC) voltage is applied to
`the external electrodes, a current path is relatively long, whereby an
`intensity of an induced magnetic field may be increased, resulting in an
`increase in inductance.
`
`[0060] In order to solve this problem, the first and second external
`electrodes 131 and 132 in the exemplary embodiment of the present
`disclosure may be disposed on the first and second side surfaces 85 and
`S6 of the ceramic body 110 opposing each other in the width direction §_9_
`
`as to reduce the current path.
`
`2 of 6
`
`Page 2 of 48
`
`Page 2 of 48
`
`

`

`[0061] In this case, since a distance between the first and second
`external electrodes 131 and 132 is relatively short, the current Qath
`
`may be reduced,
`
`resulting in a reduction in inductance.
`
`Further exemplary information from the specification of the subject Application
`
`USSN 14/259,011 relates to dielectric grain subject matter, as recited below re
`
`application Paragraphs [0087] and [0088] (emphasis added):
`
`[0087] FIG. 5 is an enlarged view of part Z of FIG. 4.
`
`[0088] Referring to FIG. 5, the average number of dielectric grains 111a
`present in a single dielectric layer 111 in a thickness direction thereof may
`
`be 2 or greater.
`
`Such Fig.5 of the USSN 14/259,011 is reproduced below:
`
`
`
`Claim 1 of the subject Application USSN 14/259,011 relates to multilayered
`
`ceramic capacitor subject matter, and recites in pertinent part (bracketed comments
`
`addedy
`
`1. A multilayer ceramic capacitor, comprising:
`
`a ceramic body [110] including dielectric layers [111] and having first
`
`and second main surfaces [81, 82] opposing each other, first and second
`
`30f6
`
`Page 3 of 48
`
`Page 3 of 48
`
`

`

`side surfaces [S5, SS] opposing each other, and first and second end
`surfaces [S3, S4] opposing each other;
`an active layer including a plurality of first and second internal
`electrodes [121, 122] disposed to face each other with at least one of the
`dielectric layers interposed therebetween and alternately exposed to the
`first or second side surface;
`
`upper and lower cover layers [112, 113] disposed on and below the
`active layer, respectively; and
`a first external electrode [131] disposed on the first side surface [83] of
`the ceramic body and electrically connected to the first internal electrodes
`[121] and a second external electrode [132] disposed on the second side
`surface [84] and electrically connected to the second internal electrodes
`
`[122],
`wherein when a thickness of the ceramic body is defined as T and a
`
`width thereof is defined as W, O.75W.ltoreq.T.ltoreq.1.25W is satisfied,
`
`when a gap between the first and second external electrodes is
`defined as G, 30 .mu.m.ltoreq.G.ltoreq.0.9W is satisfied {Fig. 4], and
`an average number of dielectric grains in a single dielectric layer in a
`thickness direction thereof is 2 or greater [Fig 5].
`
`independent claim 8 relates to a printed circuit board having at least two
`
`electrode pads, and such a multilayer ceramic capacitor mounted and soldered thereon.
`
`Document 1 (D1) is entitled "Land Grid Feedthrough Low ESL Technology," and
`
`discloses subject matter pertinent to the subject Application USSN 14/259,011. _S_e;e, for
`
`example, D1, Fig. 4a reproduced below and showing a reverse geometry multi-layer
`
`capacitor 400 mounted via traces 442 and 444 on printed circuit board 420:
`
`
`
`4of6
`
`Page 4 of 48
`
`Page 4 of 48
`
`

`

`Further, the D1 specification refers to reducing inductance in the context of both
`
`reverse geometry capacitors and low aspect ratio (length to width ratio). Both such
`
`features are pertinent to the subject Application USSN 14/259,011. S_ee, for example,
`
`D1, specification Col. 1, lines 33-67 (emphasis added):
`
`There may be several strategies for reducing equivalent series
`
`inductance, or ESL, of chip capacitors compared to standard multilayer
`chip capacitors.
`A first exemplagy strategy for reducing ESL
`involves reverse geometgy termination, such as employed in low
`inductance chi ca acitor LICC desi ns. In such LlCCs, electrodes
`
`are terminated on the long side of a chip instead of the short side.
`
`Since the total inductance of a chip capacitor is determined in part
`
`by its length to width ratio, LICC reverse geometry termination
`results in a reduction in inductance by as much as a factor of six from
`
`conventional MLC chips.
`
`Interdigitated capacitors (lDCs) incorporate another strategy for reducing
`
`capacitor inductance [by] having a main portion and multiple tab portions
`
`that connect to respective terminations formed on the capacitor periphery
`
`A still further technology utilized for reduction in capacitor inductance
`
`involves [a] low inductance chip array (LlCA) product, [which] achieves
`
`low inductance values by low aspect ratio of the electrodes...
`
`Another aspect of D1 discloses the relationship between the gap between a pair
`
`of external electrodes (which creates a current path or loop) and the resulting
`
`inductance of such arrangement. §§, D1, Fig. 2, per below and its related description:
`
`"FIG. 2 provides a graphical comparison of general inductance trends for low
`
`inductance MLCC components especially depicting lumped ESL values versus
`
`cancellation loop width for multiple exemplary LGA capacitor embodiments of differing
`
`sizes;. . . "
`
`5of6
`
`Page 5 of 48
`
`Page 5 of 48
`
`

`

`Measured ESL for 1206 Extended Land MLCC and LGA
`
`Capacitors vs Terminal Gap
`
`1000 ‘.
`
`Lumped
`
`ESL(pH)
`
`Terminal Gap (mm)
`ESL-LGA
`fl
`
`9
`
`ESL—MLCX
`
`FIG. 2
`
`Thus, per the foregoing, at least the exemplary above-indicated disclosure of
`
`Document 1 subject matter as relates to lowering inductance for a multilayer ceramic
`
`capacitor is pertinent to the subject Application USSN 14/259,011.
`
`60f6
`
`Page 6 of 48
`
`Page 6 of 48
`
`

`

`Third Party Submission for Application USSN 14/259,011
`
`Patent No.:
`
`Inventor:
`
`Application No.:
`
`Filed:
`
`Document 2
`
`US Patent 7,414,857
`
`Ritter et al.
`
`11/588,104
`
`October 26, 2006
`
`Application Publication Date:
`
`May 3, 2007
`
`Issue Date:
`
`August 19, 2008
`
`Concise Description:
`
`Document 2 was published as a patent prior to the earliest possible priority date
`
`ofJune 14, 2013 for the subject Application USSN 14/259,011.
`
`The subject Application USSN 14/259,011 is entitled ”Multilayer Ceramic
`
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`
`a particular capacitor arrangement which results in a reverse geometry capacitor having
`
`relatively low inductance.
`
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`132
`
`z
`
`131
`
`1 22“\ 3m
`‘- ”III...'A;_,—’u—il'— ;
`Z..'...".u.
`’2...n...'.'. :
`
`ill
`
`" "WE—lJ... A
`
`i .‘.m......lz
`
`Page 7 of 48
`
`Page 7 of 48
`
`

`

`Examples from the specification of the subject Application USSN 14/259,011
`
`regarding such reverse geometry feature arrangement and resulting relatively low
`
`inductance are recited below re application Paragraphs [0050], and [0056] through
`
`[0061] (emphasis added):
`
`[0050] Referring to FIG. 1, in the multilayer ceramic capacitor according to
`an exemplary embodiment of the present disclosure, a 'Iength direction'
`refers to an ‘L' direction, a 'width direction‘ refers to a 'W' direction, and a
`'thickness direction' refers to a 'T' direction. Here, the 'thickness direction'
`
`may be the same as a stacking direction in which dielectric layers are
`stacked.
`
`[0056] The first and second internal electrodes 121 and 122 may be
`disposed to face each other, having at least one of the dielectric layers
`111 interposed therebetween, and may be alternately exposed to the first
`or second side surface S5 or S6.
`
`[0057] The first and second internal electrodes 121 and 122 are
`alternately exposed to the first or second side surface 85 or 86, such that
`a reverse geometry capacitor [RGC] or low inductance chip capacitor
`[LlCC] may be obtained as described below.
`
`[0058] In a general multilayer ceramic electronic component, external
`electrodes may be disposed on opposing end surfaces of the ceramic
`
`body in a length direction thereof.
`
`[0059] In this case, when an alternative current (AC) voltage is applied to
`the external electrodes, a current path is relatively long, whereby an
`
`intensity of an induced magnetic field may be increased, resulting in an
`increase in inductance.
`
`[0060] In7, o_ob|em, the first and second external
`
`electrodes 131 and 132 in the exemplary embodiment of the present
`
`disclosure may be disposed on the first and second side surfaces S5 and
`S6 of the ceramic body 110 opposing each other in the width direction a
`
`as to reduce the current path.
`
`2 of 6
`
`Page 8 of 48
`
`Page 8 of 48
`
`

`

`[0061] In this case, since a distance between the first and second
`external electrodes 131 and 132 is relatively shortI the current path
`
`may be reducedI
`
`resulting in a reduction in inductance.
`
`Further exemplary information from the specification of the subject Application
`
`USSN 14/259,011 relates to dielectric grain subject matter, as recited below re
`
`application Paragraphs [0087] and [0088] (emphasis added):
`
`[0087] HS. 5 is an enlarged view of part Z of FIG. 4.
`
`[0088] Referring to FIG. 5, the average number of dielectric grains 111a
`present in a single dielectric layer 111 in a thickness direction thereof may
`
`be 2 or greater.
`
`Such Fig.5 of the USSN 14/259,011 is reproduced below:
`
`
`
`Claim 1 of the subject Application USSN 14/259,011 relates to multilayered
`
`ceramic capacitor subject matter, and recites in pertinent part (bracketed comments
`
`addedy
`
`1. A multilayer ceramic capacitor, comprising:
`a ceramic body [110] including dielectric layers [111] and having first
`
`and second main surfaces [81, 82] opposing each other, first and second
`
`30f6
`
`Page 9 of 48
`
`Page 9 of 48
`
`

`

`side surfaces [85, 86] opposing each other, and first and second end
`surfaces [83, S4] opposing each other;
`an active layer including a plurality of first and second internal
`electrodes [121, 122] disposed to face each other with at least one of the
`dielectric layers interposed therebetween and alternately exposed to the
`first or second side surface;
`
`upper and lower cover layers [112, 113] disposed on and below the
`active layer, respectively; and
`a first external electrode [131] disposed on the first side surface [83] of
`the ceramic body and electrically connected to the first internal electrodes
`[121] and a second external electrode [132] disposed on the second side
`surface [S4] and electrically connected to the second internal electrodes
`
`[122].
`wherein when a thickness of the ceramic body is defined as T and a
`
`width thereof is defined as W, O.75W.ltoreq.T.ltoreq.1.25W is satisfied,
`
`when a gap between the first and second external electrodes is
`defined as G, 30 .mu.m.ltoreq.G.ltoreq.0.9W is satisfied {Fig. 4], and
`an average number of dielectric grains in a single dielectric layer in a
`thickness direction thereof is 2 or greater [Fig. 5].
`
`Independent claim 8 relates to a printed circuit board having at least two
`
`electrode pads, and such a multilayer ceramic capacitor mounted and soldered thereon.
`
`Document 2 (D2) is entitled "Multilayer Ceramic Capacitor With Internal Current
`
`Cancellation and Bottom Terminals," and discloses subject matter pertinent to the
`
`subject Application USSN 14/259,011. §e_e_, for example, D2, Fig. 4 reproduced below
`
`and showing a ceramic multi-layer capacitor 42 mounted on printed circuit board 22 per
`
`vias and solder pads.
`
`_<-
`
`16
`
`18'
`
`
` 7157/1/574’4’fiW/IIII‘/
`
`
`
`26’
`
`, 20'
`
`
`5$V
`,
`,
`i‘ V
`§\‘VVV$‘~‘
`
`
`
`
`RRRRRRE? 555
`
`hytesssztstsm
`memes:
`
`o)))))-ZO))))))M
`$>b§§§2o§§§§§
`
`
`
`
`46
`
`22
`
`Page 10 of 48
`
`Page 10 of 48
`
`

`

`Further, the D2 specification refers to reducing inductance in the context of both
`
`reverse geometry capacitors and low aspect ratio (length to width ratio). Both such
`
`features are pertinent to the subject Application USSN 14/259,011. gig, for example,
`
`D2, specification Col. 1, lines 28-60 (emphasis added):
`
`The prior art includes several strategies for reducing equivalent series
`inductance, or ESL, of chip capacitors compared to standard multilayer
`chip capacitors. A first exemplary strategy involves reverse geometry
`termination, such as employed in low inductance chip capacitor
`[LICC] designs [which] are terminated on the long side of a chip
`instead of the short side. Since the total inductance of a chip
`
`capacitor is determined in part by its length to width ratioI LlCC
`reverse geometr_'y termination results in a reduction in inductance by
`as much as a factor of six from conventional MLC chips.
`
`Interdigitated capacitors (lDCs) incorporate a second known strategy for
`reducing capacitor inductance [by] having a main portion and multiple tab
`portions that connect to respective terminations formed on the capacitor
`
`periphery.
`
`A still further known technology utilized for reduction in capacitor
`
`inductance involves [a] low inductance chip array (LICA) product, [which]
`
`achieves low inductance values by low aspect ratio of the
`electrodes... .
`
`Another aspect of D2 discloses the relationship between the gap between a pair
`
`of external electrodes (which creates a current path or loop) and the resulting
`
`inductance of such arrangement. E, DZ, Fig. 3, per beiow and its related description:
`
`"FIG. 3 provides a graphical illustration of a general inductance trend for low
`
`inductance chip capacitors, especially depicting lumped ESL values versus cancellation
`
`loop width for multiple exemplary capacitor embodiments of differing sizes;"
`
`5of6
`
`Page11of48
`
`Page 11 of 48
`
`

`

`
`
`180
`
`1.69
`
`140
`
`120
`
`100 .
`
`ESL(pl-l) O
`Lumped
`
`80
`
`60
`
`4O
`
`20 -'
`
`.
`
`0
`
`0.5
`
`1
`
`1.5
`
`2
`
`Cancellation Loop Width (mm)
`
`Hg. 3
`
`Thus, per the foregoing, at least the exemplary above-indicated disclosure of
`
`Document 2 subject matter as relates to lowering inductance for a multilayer ceramic
`
`capacitor is pertinent to the subject Application USSN 14/259,011.
`
`60f6
`
`Page 12 of 48
`
`Page 12 of 48
`
`

`

`Third Party Submission for Application USSN 14/259,011
`
`Document 3
`
`Patent No.:
`
`Inventor:
`
`US Patent 5,134,540
`
`Rutt
`
`Application No.:
`
`07/758,623
`
`Filed:
`
`Issue Date:
`
`September 12, 1991
`
`July 28, 1992
`
`Concise Description:
`
`Document 3 was published as a patent prior to the earliest possible priority date
`
`of June 14, 2013 for the subject Application USSN 14/259,011.
`
`The subject Application USSN 14/259,011 is entitled "Multilayer Ceramic
`
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`
`a particular capacitor arrangement which results in a reverse geometry capacitor having
`
`relatively low inductance.
`
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`132
`
`z
`
`131
`
`7112
`
`121
`
`122~\
`
`111/"
`
`;""U4m‘;'—W‘
`7 ..'...AV——...'
`
`
`...n..fl_n.—.
`
`r IIIIII‘erI—I
`.I...'.....
`'.'..'.m..l
`Ina-m" A
`
`
`E mIIIIIxIIIIl
`'n.....’... A
`'...........l
`
`
`
`IIIIIIIIIIIII
`' ..n.'.'.J
`..'.',.,.,.',.,..7A
`
`
`
`113
`
`1of6
`
`Page 13 of 48
`
`Page 13 of 48
`
`

`

`Examples from the specification of the subject Application USSN 14/259,011
`
`regarding such reverse geometry feature arrangement and resulting relatively low
`
`inductance are recited below re application Paragraphs [0050], and [0056] through
`
`[0061] (emphasis added):
`
`[0050] Referring to FIG. 1, in the multilayer ceramic capacitor according to
`an exemplary embodiment of the present disclosure, a 'length direction’
`refers to an 'L' direction, a 'width direction' refers to a 'W' direction, and a
`
`‘thickness direction' refers to a 'T' direction. Here, the 'thickness direction'
`
`may be the same as a stacking direction in which dielectric layers are
`stacked.
`
`[0056] The first and second internal electrodes 121 and 122 may be
`disposed to face each other, having at least one of the dielectric layers
`111 interposed therebetween, and may be alternately exposed to the first
`or second side surface S5 or 86.
`
`[0057] The first and second internal electrodes 121 and 122 are
`
`alternately exposed to the first or second side surface 85 or 86, such that
`
`a reverse geometry capacitor [RGC] or low inductance chip capacitor
`
`[LlCC] may be obtained as described below.
`
`[0058] In a general multilayer ceramic electronic component, external
`
`electrodes may be disposed on opposing end surfaces of the ceramic
`
`body in a length direction thereof.
`
`[0059] in this case, when an alternative current (AC) voltage is applied to
`
`the external electrodes, a current path is relatively long, whereby an
`
`intensity of an induced magnetic field may be increased, resulting in an
`increase in inductance.
`
`[0060] In order to solve this problem, the first and second external
`
`electrodes 131 and 132 in the exemplary embodiment of the present
`
`disclosure may be disposed on the first and second side surfaces 85 and
`
`S6 of the ceramic body 110 opposing each other in the width direction _s_p
`
`as to reduce the current path.
`
`20f6
`
`Page 14 of 48
`
`Page 14 of 48
`
`

`

`[0061] In this case, since a distance between the first and second
`
`external electrodes 131 and 132 is relatively shortI the current Qath
`
`may be reduced,
`
`resulting in a reduction in inductance.
`
`Further exemplary information from the specification of the subject Application
`
`USSN 14/259,011 relates to dielectric grain subject matter, as recited below re
`
`application Paragraphs [0087] and [0088] (emphasis added):
`
`[0087] FIG. 5 is an enlarged view of part Z of FIG. 4.
`
`[0088] Referring to FIG. 5, the average number of dielectric grains 111a
`
`present in a single dielectric layer 111 in a thickness direction thereof may
`
`be 2 or greater.
`
`Such Fig.5 of the USSN 14/259,011 is reproduced below:
`
`
`
`Claim 1 of the subject Application USSN 14/259,011 relates to multilayered
`
`ceramic capacitor subject matter, and recites in pertinent part (bracketed comments
`
`addedy
`
`1. A multilayer ceramic capacitor, comprising:
`
`a ceramic body [110] including dielectric layers [111] and having first
`
`and second main surfaces [81, 82] opposing each other, first and second
`
`30f6
`
`Page 15 of 48
`
`Page 15 of 48
`
`

`

`side surfaces [85, 86] opposing each other, and first and second end
`
`surfaces [83, S4] opposing each other;
`
`an active layer including a plurality of first and second internal
`
`electrodes [121, 122] disposed to face each other with at least one of the
`
`dielectric layers interposed therebetween and alternately exposed to the
`
`first or second side surface;
`
`upper and lower cover layers [112, 113] disposed on and below the
`
`active layer, respectively; and
`
`a first external electrode [131] disposed on the first side surface [83] of
`
`the ceramic body and electrically connected to the first internal electrodes
`
`[121] and a second external electrode [132] disposed on the second side
`
`surface [84] and electrically connected to the second internal electrodes
`
`[122],
`
`wherein when a thickness of the ceramic body is defined as T and a
`
`width thereof is defined as W, O.75W.|toreq.T.ltoreq.1.25W is satisfied,
`
`when a gap between the first and second external electrodes is
`
`defined as G, 30 .mu.m.|toreq.G.ltoreq.O.9W is satisfied {Fig. 4], and
`
`an average number of dielectric grains in a single dielectric layer in a
`
`thickness direction thereof is 2 or greater [Fig. 5].
`
`Independent claim 8 relates to a printed circuit board having at least two
`
`electrode pads, and such a multilayer ceramic capacitor mounted and soldered thereon.
`
`Document 3 (D3) is entitled "Varistor or Capacitor and Method of Making Same,"
`
`and discloses subject matter pertinent to the subject Application USSN 14/259,011.
`
`§§§, for example, D3, Figs. 1 and 1A reproduced below and described as "FIG. 1. is a
`
`schematic sectional view through a capacitor or varistor in accordance with the
`
`invention. FIG. 1A is a magnified section of the circled component portion of FIG. 1.":
`
`FIG I
`
`
`OI
`I'D ' 03.0};II"
`
`
`9359.9239!!!29.9.9.9812191129','9\
`
`I9
`‘p.‘I'QI;I;I;I;I;I;I:I;OIII),o,oo‘0,v’ooN
`a999.999.99.99.999999999999§
`
`
`
`
`15 \mmmmmmu
`
`
`
`
`/6’
`
`4of6
`
`Page 16 of 48
`
`Page 16 of 48
`
`

`

`
`
`The D3 specification refers to features 13, 14, and 15 as dielectric layers, and
`
`enlarged Fig. 1A shows grains 24 and 25 regarding one illustrated exemplary grain
`
`boundary.
`
`_S_e_e_, for example, D3, specification Col. 3, lines 47—56 and Col. 4, lines 31—
`
`40.
`
`The D3 Abstract states in pertinent part:
`
`in accordance with the method the ceramic layers of the varistor are
`
`formed by providing at least two strata separated by a boundary layer
`
`which resists grain growth thereacross.
`
`By this method the ceramic
`
`layers have a predictable number of grain boundaries between adjacent
`electrodes.
`
`Since those of ordinary skill in the art understand that grain boundaries are
`
`around grains, plural "boundaries" clearly implies plurality of grains.
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`Another aspect of D3 discloses more explicitly that the more grains, the higher
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`the break down voltage, while a singular grain is not favorable. See, D3, Col. 1, lines
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`57-69:
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`It has been experimentally determined that the breakdown voltage of a
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`varistor-ceramic formulation is a function of the number of grain
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`boundaries of the ceramic grains intervening between adjacent electrode
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`layers. The greater the number of boundaries between adjacent layers,
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`the higher the break down voltage necessary to provide a conductive path.
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`50f6
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`Page 17 of 48
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`Page 17 of 48
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`

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`Conversely, in the event of a grain size such that grains of ceramic directly
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`span the distance between adjacent electrodes, the device will exhibit
`break down or pass current at extremely low voltages.
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`As stated further in D3, Col. 3, lines 15-17: "In this manner, there may be formed
`
`a ceramic layer wherein the number of grains taken in a depth-wise direction may be
`
`accurately controlled."
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`Also, D3, claim 3 states in pertinent part: "3. In a monolithic ceramic
`
`capacitor
`
`comprising at least one ceramic dielectric layer,
`
`said layer being comprised of at
`
`least two discrete strata, each of said strata being comprised of grains of ceramic
`
`material, ...."
`
`Therefore, the average number of dielectric grains is 2 or greater.
`
`Thus, per the foregoing, at least the exemplary above-indicated disclosure of
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`Document 3 subject matter as relates to grain related features for a ceramic capacitor is
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`pertinent to the subject Application USSN 14/259,011.
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`6of6
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`Page 18 of 48
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`Page 18 of 48
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`

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`Third Party Submission for Application USSN 14/259,011
`
`Patent No.:
`
`inventor:
`
`Application No.:
`
`Filed:
`
`Issue Date:
`
`Document 4
`
`US Patent 5,952,040
`
`Yadav et al.
`
`08/730,661
`
`October 11, 1996
`
`September 14, 1999
`
`Concise Description:
`
`Document 4 was published as a patent prior to the earliest possible priority date
`
`of June 14, 2013 for the subject Application USSN 14/259,011.
`
`The subject Application USSN 14/259,011 is entitled ”Multilayer Ceramic
`
`Capacitor and Board Having the Same Mounted Thereon." It relates in pertinent part to
`
`a particular capacitor arrangement which results in a reverse geometry capacitor having
`
`relatively low inductance.
`
`Fig. 4 of subject application USSN 14/259,011 is exemplary (reproduced below):
`
`121
`
`1 1 1 /...
`
`
`
`
`
`z 131132 112
`
`MW
`
`
`
`{’1Inmnnm __,
`ll'IIWJIJIII
`"...-'47....
`r 'u'w ...
`r...nnW-—IA
`
`
`
`'u....sar...q
`m.".'m'
`Well—...!!!—
`.... In...
`
`
`
`......III'.
`......‘I:
`
`
`'IIJIJIIIIIuI‘J‘
`...I'I..III
`"nn."'u.g
`
`
`”ll/WA
`
`
`1of5
`
`Page 19 of 48
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`Page 19 of 48
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`

`

`Examples from the specification of the subject Application USSN 14/259,011
`
`regarding such reverse geometry feature arrangement and resulting relatively low
`
`inductance are recited below re application Paragraphs [0050], and [0056] through
`
`[0061] (emphasis added):
`
`[0050] Referring to FIG. 1, in the multilayer ceramic capacitor according to
`an exemplary embodiment of the present disclosure, a 'length direction'
`refers to an 'L' direction, a 'width direction‘ refers to a 'W' direction, and a
`'thickness direction' refers to a 'T' direction. Here, the 'thickness direction'
`may be the same as a stacking direction in which dielectric layers are
`stacked.
`
`[0056] The first and second internal electrodes 121 and 122 may be
`disposed to face each other, having at least one of the dielectric layers
`111 interposed therebetween, and may be alternately exposed to the first
`or second side surface 85 or 86.
`
`[0057] The first and second internal electrodes 121 and 122 are
`alternately exposed to the first or second side surface 85 or 86, such that
`a reverse geometry capacitor [RGC] or low inductance chip capacitor
`[LlCC] may be obtained as described below.
`
`[0058] In a general multilayer ceramic electronic component, external
`electrodes may be disposed on opposing end surfaces of the ceramic
`body in a length direction thereof.
`
`[0059] In this case, when an alternative current (AC) voltage is applied to
`the external electrodes, a current path is relatively long, whereby an
`intensity of an induced magnetic field may be increased, resulting in an
`increase in inductance.
`
`[0060] In order to solve this problem, the first and second external
`electrodes 131 and 132 in the exemplary embodiment of the present
`disclosure may be disposed on the first and second side surfaces S5 and
`S6 of the ceramic body 110 opposing each other in the width direction _s__g
`
`as to reduce the current path.
`
`20f5
`
`Page 20 of 48
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`Page 20 of 48
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`

`

`[0061] in this case, since a distance between the first and second
`external electrodes 131 and 132 is relatively shortI the current path
`
`may be reduced,
`
`resulting in a reduction in inductance.
`
`Further exemplary information from the specification of the subject Application
`
`USSN 14/259,011 relates to dielectric grain subject matter, as recited below re
`
`application Paragraphs [0087] and [0088] (emphasis added):
`
`[0087] FIG. 5 is an enlarged view of part Z of FIG. 4.
`
`[0088] Referring to FIG. 5, the average number of dielectric grains 111a
`present in a single dielectric layer 111 in a thickness direction thereof may
`
`be 2 or greater.
`
`Such Fig.5 of the USSN 14/259,011 is reproduced below:
`
`
`
`FIG. 5
`
`Claim 1 of the subject Application USSN 14/259,011 relates to multilayered
`
`ceramic capacitor subject matter, and recites in pertinent part (bracketed comments
`
`addedy
`
`1. A multilayer ceramic capacitor, comprising:
`a ceramic body [110] including dielectric layers [111] and having first
`and second main surfaces [S1, 82] opposing each other, first and second
`
`30f5
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`Page 21 of 48
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`Page 21 of 48
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`

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`side surfaces [S5, S6] opposing each other, and first and second end
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`surfaces [83, S4] opposing each other;
`an active layer including a plurality of first and second internal
`electrodes [121, 122] disposed to face each other with at least one of the
`dielectric layers interposed therebetween and alternately exposed to the
`
`first or second side surface;
`
`upper and lower cover layers [112, 113] disposed on and below the
`
`active layer, respectively; and
`a first external electrode [131] disposed on the first side surface [83] of
`the ceramic body and electrically connected to the first internal electrodes
`[121] and a second external electrode [132] disposed on the second side
`surface [84] and electrically connected to the second internal electrodes
`
`[122].
`wherein when a thickness of the ceramic body is defined as T and a
`
`width thereof is defined as W, 0.75W.ltoreq.T.ltoreq.1.25W is satisfied,
`
`when a gap between the first and second external electrodes is
`defined as G, 30 .mu.m.ltoreq.G.ltoreq.0.9W is satisfied {Fig. 4], and
`an average number of dielectric grains in a single dielectric layer in a
`thickness direction thereof is 2 or greater [Fig. 5].
`
`Independent claim 8 relates to a printed circuit board having at least two
`
`electrode pads, and such a multilayer ceramic capacitor mounted and soldered thereon.
`
`Document 4 (D4) is entitled "Passive Electronic Components From Nano-
`
`Precision Engineered Materials," and discloses subject matter pertinent to the subject
`
`Application USSN 14/259,011.
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`In particular, D4 relates in part to ceramic layers coated
`
`with electrodes as part of passive electronic components.
`
`§_e_e_, for example, D4, specification Col. 6, lines 44-48 (emphasis added):
`
`Therefore, according to the foregoing objectives, one aspect of this
`
`invention involves the use of nanostructured precursors (narrowly
`
`distributed nanosize powders with mean grain size preferably less than
`
`100 nm and standard deviation preferably less than 25 nm) to form the
`
`ceramic layers, electrode layers, or both, in passive electronic
`
`components.
`
`4of5
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`Page 22 of 48
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`Page 22 of 48
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`

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`Another aspect of D4 discloses the benefit of using multiple grains, indicating that
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`the strength is better, and that the resulting electrical parameters are improved.
`
`S_ee, D4, Col. 8 lines 52 through Col. 9, line 10 (emphasis added):
`
`A primary aspect of this invention lies in the recognition that a standing
`barrier to markedly improved technology in the manufacture of passive
`electronic components exists in the limitations inherent with the grain size
`of the ceramic and electrode material used.
`Since precursor powders
`
`are not ductile, the films of ceramic material have to be packed several
`
`grains thick and sintered to ensure that there are no pin-holes in the
`resulting ceramic and electrode layers. Thus, even though the
`theoretical limit with existing materials and manufacturing technology on
`
`the thickness of the ceramic layer is in the 2 to 5 .mu.m range, current
`passive electronic components are routinely made with 5 to 20
`.mu.m thick ceramic layers. Attempts to reduce this thickness to the
`
`theoretical limit have resulted in problems of electrical, thermal,
`
`mechanical, or chemical breakdown with conseguent reliability
`
`issues. Thusl it is clear that the minimum thickness of ceramic and
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`electrode layers attainable with conventional processes is limited by
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`the grain size of the precursor ceramic and electrode material.
`
`In "Example 1 — Capacitor", the subject layer was about 8 to 9 grains thick. fl,
`
`D4, Col. 15, lines 62-65.
`
`Thus, per the foregoing, at least the exemplary above-indicated disclosure of
`
`Document 4 subject matter as relates to grain thickness for dielectric layers of a ceramic
`
`capacitor is pertinent to the subject Application USSN 14/259,011.
`
`50f5
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`Page 23 of 48
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`Page 23 of 48
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`

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`Third Party Submssséon farAppEicatian USSN MIESQ‘EM
`
`flacumam 5
`
`Besign‘ifien 5533*; 26365
`
`Titiez
`
`Subject:
`
`Tecqum TEMPE
`
`inductance a)? Bypass Capaciims; Haw is: Game,