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`9 Reproduced By IHS
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`With The Permission Of ECA
`Under RoyaHy Agreement
`
`EIA
`STANDARD
`
`ANSIIEIA 595-A-2009
`Approved: February 10, 2009
`
`VISUAL AND MECHANICAL
`INSPECTION MULTILAYER
`CERAMIC CHIP CAPACITORS
`
`EIA-595-A
`
`(Revision of EIA-595)
`
`FEBRUARY 2009
`
`Electronic Components Association
`
`EIA Standards
`Electronic Components Association
`
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`Exhibit 1009
`PGR2017-00010
`AVX CORPORATION
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`000001
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`

`

`NOTICE
`
`EIA Engineering Standards and Publications are designed to serve the public interest
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`adopting the Standard or Publication.
`
`This EIA Standard is considered to have International Standardization implication, but
`the International Electrotechnical Commission activity has not progressed to the point
`where a valid comparison between the EIA Standard and the IEC document can be
`made.
`
`This Standard does not purport to address all safety problems associated with its use or
`all applicable regulatory requirements.
`It is the responsibility of the user of this
`Standard to establish appropriate safety and health practices and to determine the
`applicability of regulatory limitations before its use.
`
`(From Standards Proposal No. 5094 formulated under the cognizance of the P-2.1
`Committee on Ceramic Capacitors)
`
`Published by:
`
`©ELECTRONIC COMPONENTS ASSOCIATION 2009
`EIA Standards and Technology Department
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`Arlington, VA 22201
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`PLEASE I
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`DON'T VIOLA TE
`THE
`LAWI
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`This document is copyrighted by the EIA and may not be reproduced without
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`CONTENTS
`
`Foreword
`Clause
`I
`l
`2.1
`2.2
`2.3
`2.4
`2.5
`2.6
`2.7
`3
`3.1
`3.2
`3.3
`3.4
`3.5
`3.6
`3.7
`4
`4.1
`4.2
`4.3
`5
`5.1
`5.2
`5.3
`5.4
`
`Figures
`I
`2
`3
`4
`5
`6
`7
`8
`9
`10
`11
`12
`13
`14
`15
`
`Scope
`Ceramic surface inspection
`Cracks
`Chipped areas
`Pinholes, holes, and voids in the ceramic body
`Delamination
`Blisters or foreign material
`Warpage and protrusions
`Marking
`End metallization inspection
`Pinholes and voids
`Bandwidth
`Stringers and smears
`Edge reduction
`Lifting or peeling of terminations
`Foreign material
`Bumps and protrusions
`Pretinned solder termination inspection
`Solder coverage
`Leaching
`Oversize
`Plated nickel/tin or nickel/solder inspection
`Barrier thickness
`Tin or solder thickness
`Plating bloom
`Tarnished end metallization
`
`Cracks
`Chipping (chipouts and chipins)
`Pinholes
`Delamination
`Blisters and foreign material
`Warpage
`Marking
`End metallization voids
`Bandwidth
`Stringers
`Chipped termination edges
`Lifted terminations
`Foreign material
`Solder coverage and leaching
`Oversize due to excessive solder dip buildup
`
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`Page
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`3
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`5
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`I
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`3
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`Foreword
`
`This specification was prepared under the cognizance of the P-2.1 Subcommittee
`on Ceramic Dielectric Capacitors of the Electronic Industries Alliance's sector
`Electronic Components, Assemblies, Equipment & Supplies Association (EIA/ECA) .
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`-----------1
`I
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`EIA-595-A, Visual and Mechanical Inspection
`Multilayer Ceramic Chip Capacitors
`Page I
`
`I Scope
`
`This document covers the general industry inspection requirements for multilayer ceramic chip capacitors. The
`devices selected for inspection may be examined under IO to 20 power magnification to determine compliance
`with the requirements specified herein.
`Increased magnification may be used when negotiated between the
`manufacturer and the user/buyer. Sampling plans or lot accept/reject criteria shall be negotiated between the
`manufacturer and the user I purchaser.
`
`2, Ceramic surface inspection
`
`2.1 Cracks
`There shall be no cracks in the ceramic surfaces (see figure I).
`
`Top or Bottom
`Surface
`
`Side Surface
`
`Figure I, Cracks
`
`2.2 Chipped areas
`Chipouts, or chipins Areas where ceramic can be seen to be forming a chipout, but the ceramic is still
`intact (see figure 2). Any single defect extending more than 20% of a side or 20% of the unmetallized top
`or bottom is not acceptable.
`In addition, the cumulated chipouts along any unmetallized edge shall not
`exceed 20% of the unmetallized length and I or width. Any chipped area (chipout or chipin) that results in
`exposed electrodes is not acceptable. Such defects are usually due to a fracture and found on the edges.
`
`Accept
`Chipouts and I or chipins
`not exposing electrodes
`and not over 20% of length .
`
`Chipouts and I or chipin
`exposing electrode, or
`greater than 20% of
`length on one side.
`
`Reject
`Cumulated chipouts and
`chipins exceed 20% of
`length and I or width.
`
`Figure 2, Chipped Areas (chipouts and chipins)
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`I I I
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`EIA-595-A. Visual and Mechanical Inspection
`Multilayer Ceramic Chip Capacitors
`Page 2
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`2.3 Pinholes, holes, and voids in the ceramic body
`Any pinholes, holes, or voids that expose the metal electrode are unacceptable (see figure 3).
`Accept
`
`Reject
`
`Voids represent surface
`defects and do not expose
`electrode material
`
`Void exposes
`electrode material
`
`Figure 3. Pinholes
`
`2.4 Delamination
`There shall be no delamination (separation) of the ceramic layers (see figure 4). Delaminations are most
`often observed on the sides of the chips. The pattern formed by the vitrified and nonseparated layers is
`referred to as a striation. When present, striations are most commonly seen in the sides and I or form a
`pattern under the end mets. Striations are acceptable.
`
`striations: A rant pa:tern of vitrified
`layers without f11Y mual sepa-a:ion.
`Sria:ions cre a:x::epta:>le.
`Figure 4. Delamination
`
`Delamlnatlons: The oeranic
`layers cre decrly sepcra:ed.
`Bectrodes ca, be visible.
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`EIA-595-A, Visual and Mechanical Inspection
`Multilayer Ceramic Chip Capacitors
`Page 3
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`2.5 Blisters or foreign material
`Blisters are not acceptable (see figure 5). Blisters are most often observed on the top or bottom surfaces
`of the chip. Foreign material that would interfere with mounting or cause electrical leakage is not
`acceptable. Ceramic materials fused to the surface are not acceptable if they interfere with mounting, or
`cause the part to have rejectable warpage.
`Accept
`
`Reject
`
`Snall srounts of ceranic ma:eria
`fused to theufa::eth.!t do not
`Interfere with mounting.
`
`All blisters we rejecta>le. Arry
`foreigi ma:eria tha interferes
`with moulting Is rejecla>le.
`
`Figure 5. Blisters and foreign material
`
`2.6 Warpage and protrusions
`When the chip is placed on a flat surface, warpage measured at the center of the chip shall be less than
`1% of the overall chip length. (see figure 6). Maximum warpage is 0.025 mm (O.OOlin) per 2.54 mm (0.100
`in) of the length dimension of the chip. In addition, any surface irregularities shall not protrude more than
`0.08 mm (0.003 in) from the surface of the chips, and the chip shall lie flat. Protrusions, when found, are
`usually on the top or bottom of the chip. In no case may the thickness envelope (distance between the
`plane the chip is sitting on, and the plane passing through the top surface of the chip) exceed the
`maximum allowable thickness, regardless of the warpage tolerance.
`Reject
`-----------------,---
`Tmax ~ 1.Smm Tactual r 1.8mm
`-----r-·
`-
`
`L=3.2mm
`
`Wa-~exaB!ing 1%ofthe
`len!;lh a,d I or exaB!ing
`macirnum thickness is rejectalle.
`Figure 6. Warpage
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`EIA-595-A, Visual and Mechanical Inspection
`Multilayer Ceramic Chip Capacitors
`Page4
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`2.7 Marking
`When marking is required, it shall be of the correct color (if applicable), and must include the correct
`characters (see figure 7). It must also be legible and of sufficient contrast for viewing. If marking bridges
`any portion of the end metallization, it is limited to 25% of the width of the marking character so affected.
`In addition, the marking must be legible, in consideration of the future loss of the end metallization
`portion during soldering.
`
`Reject
`
`More tha"t 25% of one
`cha'a:ter bridges the
`end metellizaion.
`
`MS"king is not
`dea-ly legble.
`
`Figure 7. Marking
`
`3 End metallization inspection; general requirements applicable to silver palladium, plated barriers,
`and solder dipped terminations
`
`3.1 Pinholes and voids
`The end surfaces of the chips shall be completely covered (see figure 8). The other metallized surface
`areas shall be also be completely covered with the exception that pinholes or voids less than or equal to
`5% of each individual surface area are allowed. Voids or pinholes which allow electrode exposure are
`unacceptable.
`
`Rnhole voids in end rnetalliza:ion which
`expose electrodes a,d voids geaer
`tha, 5% of the metallized a-ea on my
`individua metallized s.irfa:ie.
`
`Snall voids not exposing electrodes
`a,d not exceeding 5% of the
`metallized a-ea on a,y s.irfa:ie.
`
`Figure 8 - End metallization voids
`
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`EIA-595-A, Visual and Mechanical Inspection
`Multilayer Ceramic Chip Capacitors
`Page 5
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`3.2 Bandwidth
`Termination gaps must not reduce the end metallization bandwidth to less than the minimum limit (see
`figure 9). Additionally 90% of the length of the top and bottom surface termination bands must be within
`the minimum and maximum dimensional limits. The sides are not required to meet any minimum limit.
`Reject
`Accept
`
`Max Dimension
`1Min Dimension
`r:7"'~;-~~-,-~~-+--in
`
`Max Dimension
`fJlln Dimension
`1£".'"~t--,, ..... ~--,.--_,.,.......+,.........,
`
`·····&J
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`•
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`More tha, 90% of the metaliza:ion width
`on the top or bottom surfa::e is within the
`min I max baidwidth requirement.
`
`Lessthai 90%ofthe metalization
`width on the top or bottom surfcm is
`within the min I max requirement.
`
`Note: There is no requirement for the sides .
`
`Figure 9. Bandwidth
`
`3.3 Stringers or smears
`End metallization
`stringers or smears must not exceed 20% of the unmetallized surface length, as
`measured linearly along the edge (see figure I 0).
`
`Less thal 20% of the linea"
`unmetalized surfa::e leng'.h.
`
`Over 20%ofthelinea(cid:173)
`unmetalized surfa::e leng'.h.
`
`Figure I 0. Stringers
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`EIA-595-A, Visual and Mechanical Inspection
`Multilayer Ceramic Chip Capacitors
`Page 6
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`3.4 Edge reduction
`Mounting area edges must not be reduced by more than I 0% due to chipping or termination processes
`(see figure 11). Note that normal rounding of the corners to promote silver adhesion is not a rejectable
`phenomenon.
`
`Reject
`More tha110%of metallized
`edg35 reducsl by chipping.
`
`Figure I I. Chipped termination edges
`
`3.5 Lifting or peeling of terminations
`In the case of plated chips,
`There shall be no evidence of termination lifting on the chip (see figure 12).
`there may be a slight and acceptable amount of overplate beyond the edge of the barrier material .
`
`Termina:ion lifted
`from oeranic surm.
`
`Figure 12. Lifted terminations
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`EIA-595-A, Visual and Mechanical Inspection
`Multilayer Ceramic Chip Capacitors
`Page 7
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`3.6 Foreign material
`Foreign material (including grease or oil) on the end metallizations may interfere with bonding and is not
`acceptable (see figure 13).
`
`3.6 Bumps and protrusions
`Any surface irregularities must not cause the chip to exceed the warpage requirements, nor to fall outside
`the limits on length, width, and thickness. In addition, they must not cause a bonding problem (see figure
`13).
`
`Foreig'l meterlal, both 91lea'S
`aid bumps, thal l11E¥ interfere
`with bonding process.
`
`Figure 13. Foreign material
`
`Solder-dipped termination inspection; additional requirements beyond the general end
`4
`metallization inspection requirements
`
`NOTE -Solder dipping is an alternate end metallization option.
`
`4.1 Solder coverage
`Must be smooth, clean, non-dewetted, and must cover 90% or more of the base metallization on each
`mounting surface independently (see figure 14).
`
`Dewetting or lea::hing of the metallizaion a-eas.
`No lea::hing is allowed, aid dewett ing must be lei:B
`tha, 100/oof the a-eaof ea::h metallized surfa::e .
`
`Figure 14. Solder coverage and leaching
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`EIA-595-A, Visual and Mechanical Inspection
`Multilayer Ceramic Chip Capacitors
`Page8
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`4.2 Leaching
`
`There shall be no evidence of leaching (see figure 14). Leaching, when present, is typically found on the
`corners. It is the removal of the solderable base material, due to dissolution in the molten solder.
`
`4.3 Oversize
`Solder dipping (when used by the chip manufacturer) shall not increase the overall length, width, or
`thickness dimensions in excess of the overall limit (see figure 15). Note: As a guide, and not a
`requirement, solder dipping terminations normally will add no more than I 0% of the unsoldered
`maximum dimension, or 0.306 mm (0.012"), whichever is greater.
`
`W max
`
`B<oessive EK>lder buildup lnaeases F1Vf dimension
`(L, W, or T) beyond the madrrum aloweble.
`
`Figure 15. Over size due to excessive solder dip buildup
`
`5 Plated nickel/plated tin and plated solder inspection; additional requirements beyond the general
`end metallization inspection requirements
`
`NOTE: Plating is an end metallization option. Although it is the most common termination
`treatmentt other options are available.
`
`5.1 Barrier thickness
`Barrier plating (most commonly nickel) thickness shall be 1.27 micrometers (50 microinches) minimum
`and 625 micrometers (250 microinches) maximum.
`
`5.2 Tin or solder thickness
`Tin or solder plating thickness must be a minimum of 2.54 micrometers ( I 00 microinches.)
`
`5.3 Plating bloom
`
`Any metallic spot that appears on the unmetallized ceramic surface, and extends through the top or
`bottom ceramic surface cover layers and contacts the electrode is not acceptable. Any exposed
`electrode on the side surfaces may also plate, and is not acceptable. Such areas are in electrical contact
`with the inner electrodes, and may result in short circuit problems.
`
`5.4 Tarnished end metallization
`
`Any discolored or uniformly darkened area on the end metallization may be evidence of tarnished and
`unsolderable barrier metal, and should be rejected.
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