(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`
`(19) World Intellectual Property Organization
`International Bureau
`
`(43) International Publication Date
`
`8 February 2001 (08.02.2001) LTAAE
`
`(10) International Publication Number
`WO 01/10110 A2
`
`PEARL, LATZER & CO-
`EITAN,
`(74) Agent:
`HEN-ZEDEK; Gav Yam Center 2, Shenkar Street 7,
`46725 Herzlia (IL).
`(21) International Application Number;=PCT/IL00/00438
`
`(51) International Patent Classification’:
`
`HO4N
`
`(22) International Filing Date:
`
`24 July 2000 (24.07.2000)
`
`(25) Filing Language:
`
`(26) Publication Language:
`
`English
`
`English
`
`(30) Priority Data:
`60/145,960
`09/516,168
`
`29 July 1999 (29.07.1999)
`29 February 2000 (29.02.2000)
`
`US
`US
`
`(71) Applicant (for all designated States except US): VISION-
`SCIENCESINC. [US/US]; 40 Ramland Road South, Or-
`angeburg, NY 10962 (US).
`
`(81) Designated States (national): AE, AG, AL, AM,AT, AU,
`AZ, BA, BB, BG, BR, BY, BZ, CA, CH, CN, CR, CU, CZ,
`DE, DK, DM,DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR,
`HU,ID,IL, IN,IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR,
`LS, LT, LU, LV, MA, MD, MG, MK, MN, MW,MX,MZ,
`NO, NZ, PL, PT, RO, RU, SD, SE, SG,SI, SK, SL, TJ, TM,
`TR, TT, TZ, UA, UG, US, UZ, VN, YU, ZA, ZW.
`
`(84) Designated States (regional): ARIPO patent (GH, GM,
`KE, LS, MW, MZ, SD, SL, SZ, TZ, UG, ZW), Eurasian
`patent (AM, AZ, BY, KG, KZ, MD,RU,TJ, TM), European
`patent (AT, BE, CH, CY, DE, DK,ES, FI, FR, GB, GR,IE,
`IT, LU, MC, NL,PT, SE), OAPI patent (BF, BJ, CF, CG,
`CI, CM, GA, GN, GW, ML, MR,NE, SN, TD, TG).
`
`(72) Inventor; and
`STARK, Moshe
`(for US only):
`(75) Inventor/Applicant
`[{IL/IL]; Harimonim Street 9, 40500 Even Yehuda(IL).
`
`Published:
`
`Without international search report and to be republished
`upon receipt of that report.
`
`(54) Title: IMAGE-SENSOR ARCHITECTURE FOR PER-PIXEL CHARGE-INTEGRATION CONTROL
`
`[Continued on next page]
`
`
`
`
` Output
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`Vout
`READOUT CIRCUIT
`
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`
`(57) Abstract: A sensor array that produces a captured image at the end of a time frame. The array includes a plurality of unit
`cells which sense the image with multiple within-frame charge-integrations, and control means which separately controls each of
`the unit cells. The unit cells are programmable multiple charge-integration unit cells with modes of photocurrent integration and
`non-integration. The control means includes means for separately controlling multiple charge-integrations in a single frame capture
`of each unit cell, independently of the charge-integrations of the other unit cells.
`
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`WO 01/10110 A2
`
`—_[HIIUNEUINACININEAIATTAMRT
`
`For two-letter codes and other abbreviations, refer to the "Guid-
`ance Notes on Codes and Abbreviations" appearing at the begin-
`ning ofeach regular issue of the PCT Gazette.
`
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`PCT/1IL00/00438
`
`IMAGE-SENSOR ARCHITECTURE FOR PER-PIXEL
`
`CHARGE-INTEGRATION CONTROL
`
`FIELD OF THE INVENTION
`
`The present invention relates to image sensorarray architecture generally
`
`and, in particular, to logic control thereof.
`
`BACKGROUND OF THE INVENTION
`
`Image sensors are generally comprised of an array of sensing unit cells,
`
`wherein each unit cell comprises a pixel which is exposed to light, and produces
`
`an electrical response representative thereof. Hereinbelow are defined the basic
`
`terms usedin relation to image-sensor technology and several known-in-the-art
`
`methods for the same.
`
`The minimal signal that can be detected by an image sensor is defined
`
`as the minimal incidentlight intensity on the pixel that results in a recognizable,
`
`15
`
`meaningful response signal above the noise level. Signals with light intensity
`
`below the noise level are considered to act in the image sensor's cutoff region.
`
`The maximum signal
`
`that can be detected by an image sensor is
`
`defined as the maximal incident light intensity on an image sensor's pixel that
`
`results in a recognizable non-saturated response. Signals with light sensitivity
`
`20
`
`abovethis level are considered to be in the saturation range.
`
`The region betweenthe cutoff region and the saturation range is defined
`
`as the image sensor'ssensitivity range. Light signals with intensity in the image
`
`sensor’s sensitivity range yield a response signal
`
`that corresponds to the
`
`incominglight intensity
`
`25
`
`30
`
`The resolution and the minimum sensitivity determine the noise floor.
`
`Dynamic range (DR) performance is described in terms of the ratio between the
`
`highest
`
`intensity and the lowest
`
`intensity range limits. An image sensor's
`
`dynamic rangeis described in three equivalent ways.
`
`In the first way, the dynamic range is described astheratio:
`(1)
`DR'_= 10": 1
`
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`where DR‘, is the image sensor's dynamic-range performance andn is
`
`a positive number, normally roundedto an integer.
`Hence, an image sensor with a dynamic range of 10°: 1 can capture
`signals that are up to thousand times larger than its minimum signal.
`The second way of describing the dynamic range is in a logarithmic
`
`fashion, where:
`DR, = 20-logio DR",
`(2)
`The third way often used to describe the image sensor's dynamic range
`is by the number of bits required to describe the dynamic range in a binary
`
`number fashion. This number ofbits is directly related to the dynamic range by
`
`the following formula,
`(3)
`
`Np = Intg (log2DR', + 1),
`
`15
`
`20
`
`25
`
`where; N, is the number of bits, and Intg is a function that extracts the
`
`integer part of its argument.
`
`Ideally, the most desirable image sensor is one that imitates the human
`
`eye’s performance and captures scenes with comparable performanceto the
`
`human eye's retina. However, while the human eye’s retina provides a dynamic
`range of 10°: 1, commercially available image sensor's “silicon retinas" provide
`a dynamic rangethatis typically only 10°: 1. Thus, in comparison to the human
`eye's dynamic-range performance, the silicon retina performs quite poorly.
`
`Dynamic range is a central issue in image-sensor design research. The
`
`basis for the research is the understanding of the workings of the human eye’s
`
`retina. The superb performance of the human eye'sretina results from the fact
`
`that each retina’s photoreceptor locally adjusts its sensitivity to the intensity of
`
`the incident light. Although the individual photoreceptors of the human eye's
`retina each have a dynamic range of less than 10° : 1,
`the overall retina’s
`performance is much better due to photoreceptor’s capability to locally adjustits
`
`“quiescent point”. Shifting the point of operation means that the photoreceptor,
`
`when exposed to a high intensity of light, reduces its sensitivity while, when
`
`30
`
`exposed to a lowlight intensity, it increases its sensitivity.
`
`The research into improvementof the artificial retina’s dynamic rangeis
`
`intensive, and today takes one ofthe following forms:
`
`2
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`
`¢
`
`Logarithmic Sensors: This
`
`type
`
`of
`
`sensor
`
`logarithmically
`
`compresses the dynamic range. The logarithmic compression is done by a
`
`logarithmically behaving photosensor, or a logarithmically responding circuit to
`
`an input photocurrent.
`
`These circuits however, are quite sensitive to the manufacturing
`
`process, and slight variations in the manufacturing process may result in varying
`
`pixel-response sensitivities. Even adjacent pixels may significantly vary in their
`
`response sensitivity. This variance expresses itself in Fixed Pattern Noise
`
`(FPN), or in other ways that result in a poor quality image.
`
`e
`
`Multiple Exposure Sensors: Several images at different exposures
`
`(charge-integration periods) are acquired and then combined into a single
`
`image. Typically, the combination of several different-exposure images is done
`
`on the image sensor's video output.
`
`Due
`
`to
`
`image
`
`acquisition
`
`time,
`
`and
`
`to
`
` computing-
`
`intensive/time-consuming
`
`image-combination
`
`constraints,
`
`this method
`
`is
`
`typically restricted to the acquisition and processing of two images.
`
`The
`
`drawback of this method is that if the pair of acquired imagesdiffer substantially
`
`in their exposure times, the outcome can be image-color artifacts and edge
`
`artifacts.
`
`20
`
`e Autonomous/Per-Pixel Controlled-Exposure Time Sensors: For this
`
`approach, each pixel’s exposure time is independently controlled and locally
`
`adjusted to the incidentlight’s intensity. Efficient implementation of this method
`
`should yield the best results. Two noticeable attempts in this direction have
`
`been reported sofar.
`
`25
`One reported method is based uponaunit cell that incorporates a static
`
`Set-Resetflip-flop. Resetting each pixel at a programmable point
`
`in time
`
`triggers the charge accumulation and thus controls the charge-integration time.
`
`Unfortunately the result
`
`is a large unit-cell area, a low fill factor, or both.
`
`Therefore,
`
`this unit cell
`
`is not suitable for small-pixel/high-resolution image
`
`30
`
`sensors.
`
`Furthermore, the image sensor's dynamic range is highly dependent on
`
`the column scan rate. Column-scan rate is limited by the programming rate of
`
`3
`
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`each column.
`
`For instance, if the column-scan rate is to be performed at the
`
`pixel clock rate (which is by itself problematic and contributes to noise), each
`
`column program must be loaded in a single pixel time. This can be done only
`
`with a very wide andfast bus that loads the row control register.
`
`S. G. Chen and J. P. Lee discuss the use of flip-flops in their article
`
`and
`"Adaptive Sensitivity CCD Image Sensor: Charge-Coupled Device
`Solid-State Optical Sensors V’, Proc. SPIE, Vol. 2415, pp. 303-309, 315.
`
`However, the authors do not explain therein the details of implementation. The
`
`article describes an implementation limited to three different exposure intervals
`
`10
`
`with a ratio of 64: 8: 1. For many scenes, these steps are generally too crude to
`
`eliminate the quantization artifacts.
`
`A second reported method is
`
`the Independent Pixel Reset
`
`(IPR)
`
`method. This method requires an independent reset of integration capacitor
`
`charge in every unit cell. Each unit cell is individually reset through a row reset
`
`control, and a column reset contro! circuits.
`
`This method results in an
`
`area-efficient solution.
`
`However, the method is limited in its scope since unit cells with the
`
`same exposure time are not reset simultaneously. Therefore the unit cells at the
`
`upper left corner of the image sensor array are reset significantly sooner than
`
`20
`
`the unit cells at the bottom right corner. For instance, if the array is 768483
`
`lines, and the reset is performed with a 67-nsec pixel clock, the time difference
`
`between the upper left corner reset and the lower right corner reset is 24.86
`
`milliseconds, which is unacceptable for commercial video applications. Hence,
`
`the methodis not suitable for large arrays or for real-time 30 frames per second
`
`25
`
`video rate.
`
`Additionally, the exposure time of the sensoris limited to a few values,
`such as 1, %, %,
`‘V/s, and 1/16 of the maximum integration time, which is
`
`unsatisfactory for real-time high quality imaging. Hence, the IPR technique is
`
`currently unsuitable for most commercial applications.
`
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`PCT/1L00/00438
`
`SUMMARY
`
`improved CMOS image sensor
`is an objective to provide a novel,
`It
`architecture that facilitates improved performance and dynamic-range scene
`
`capture.
`
`There is therefore provided in accordance with a preferred embodiment
`
`of the present invention, a sensor array that produces a captured image at the
`end of a time frame. The array includes a plurality of unit cells which sense the
`image with multiple within-frame charge-integrations, and control means which
`separately controls each of the unit cells. The unit cells are programmable
`multiple charge-integration unit cells with modes of photocurrent integration and
`
`non-integration.
`Each unit cell
`
`includes a photosensor, a charge-storage device for
`
`accumulating charge transfer from the photosensor, and a programmable
`memory unit for storing a charge-integration state of the unit cell.
`The control means includes means for separately controlling multiple
`
`charge-integrations in a single frame capture of each unit cell, independently of
`the charge-integrations of the other unit cells.
`The control means includes means for providing N charge-integration
`
`sub-periods within a single frame capture, where N is equal to or greater than 1.
`Within each single frame capture,
`the
`control means generally
`simultaneously individually integrates the charge of each unit cell within a group
`of cells.
`Generally,
`the control means includes a row-select
`line and a
`column-select line. The row-select line carries a multiplicity of first signals to the
`
`unit cells and the column-selectline carries a multiplicity of second signals, such
`
`as program and sensesignals, to the unit cells.
`Furthermore, the contro! means also programs the unit cells. A group of
`
`cells, such as a line of unit cells,
`is generally simultaneously programmed,
`preferably in a sequential order. The means for programming mayalso include
`means for sequentially programming one or more lines of the plurality of unit
`
`10
`
`20
`
`25
`
`30
`
`cells.
`
`The control means includes means for defining the charge-integration
`
`sub-periods where, alternatively,
`
`the charge-integration sub-periods are of
`
`5
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`
`various time lengths. The control means also includes means for providing fine
`time resolution in clock-time units and meansfor providing wide dynamic range
`
`of charge-integration steps. Generally, the wide dynamic rangeis in the range
`of 2‘-1 unit steps of integration times.
`There is therefore further provided,
`
`in accordance with a preferred
`
`embodiment of the present invention, a method for sensing an image with a
`plurality of unit cells. The method includes the steps of individually accessing
`
`each of the unit cells and controlling charge-integration of each unit cell,
`
`independently of the charge-integration of other of the plurality of unit cells.
`The method
`further
`includes
`the
`steps
`of
`determining
`
`the
`
`charge-integration time for each unit cell and programming each unit cell
`according to the determined charge-integration time.
`
`There is
`
`therefore further provided in accordance with a preferred
`
`embodiment of the present invention, a method for improving the intra-scene
`
`dynamic range of an image-sensor array of multiple unit cells. The method
`
`includes the steps of individually accessing and individually controlling each unit
`
`cell.
`
`The method also includes the step of
`
`individually controlling the
`
`charge-integration time of each of
`
`the
`
`unit
`
`cells,
`
`including individually
`
`20
`
`programming such. The stepofindividually programming includes programming
`
`each unit cell according to a pre-determined charge-integration time and
`programming eachunit cell with multiple charge-integration sub-periods.
`There is
`therefore further provided,
`in accordance with a preferred
`
`embodiment of the present invention, a programmable image sensorincluding a
`
`25
`multiplicity of unit cells for capturing an image. The sensor includesafirst
`
`plurality P of input lines for carrying data, a secondplurality H of columns which
`
`are connected to the cells, wherein P is equal or smaller than H, and a controller
`
`for receiving the data and selectively distributing the data to the columns,
`
`to
`
`programNtimes the array, within a single frame of motion video.
`
`Generally, and__includesthe data is programming data
`
`
`
`
`
`
`30
`charge-integration/non-integration state data for each of the plurality of unit cells.
`
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`Preferably, each of the plurality of programmable unit cells is
`
`individually
`
`controlled.
`
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`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The present invention will be understood and appreciated morefully from
`the following detailed description taken in conjunction with the appended drawings
`
`in which:
`
`is a schematic illustration of an image-sensorarray architecture for
`1
`Fig.
`implementation with
`non-interlaced
`video,
`constructed
`and
`operative
`in
`accordance with a preferred embodimentof the present invention;
`Fig 2 is a schematic illustration of an image-sensor unit cell that provides
`multiple integration sub-periods and is used with the architectureillustrated in Fig.
`
`1;
`
`Fig. 3 is a schematic illustration of a row-program loader used in the
`architectureillustrated in Fig. 1, and constructed and operative in accordance with
`
`a preferred embodimentof the present invention;
`Fig. 4A and 4B are timing diagrams of single row programming when
`implemented with the architecture illustrated in Fig. 1;
`Fig. 5 is a timing diagram of a programming sequence implemented with
`
`the architectureillustrated in Fig. 1;
`Fig. 6 is a timing diagram of a programming/integration interval operative
`with the architectureillustrated in Fig. 1;
`Fig. 7 is a schematic illustration of an image-sensorarray architecture for
`implementation with interlaced video, constructed and operative in accordance
`with an alternative preferred embodimentof the present invention;
`Fig 8 is a schematicillustration of an alternative image sensor unit that
`provides multiple integration sub-periods and is used with the architecture
`
`illustrated in Fig. 7;
`Fig. 9 is a schematic illustration of a row-program loader used in the
`architectureillustrated in Fig. 7, and constructed and operative in accordance with
`an alternative preferred embodimentof the presentinvention,
`Fig. 10A and 10B are timing diagrams of single-row programming
`implemented with the architecture of Fig. 7.;
`Fig. 11 is a timing diagram of even-row programming implemented with
`the architecture of Fig. 7.; and
`
`20
`
`25
`
`30
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`Fig. 12 is a timing diagram of an interlaced readout, program and
`
`integration cycle implemented with the architecture of Fig. 7.
`
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`WO 01/10110
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`PCT/IL00/00438
`
`DETAILED DESCRIPTION OF THE PRESENTINVENTION
`
`Herein is detailed an innovative CMOS image sensor architecture and
`
`methodthatfacilitates independent control of the charge-integration time of each
`
`pixel.
`
`In a preferred embodiment, autonomous per-pixel exposure control
`
`is
`
`accomplished via direct and independent control of the pixel’s charge-integration
`
`time.
`
`The present invention describes two novel image-sensor architectures,
`
`for utilization in both interlaced and non-interlaced video. Preferably, the image-
`
`sensorarchitectures incorporate a multiplicity of image-sensor unit cells that are
`
`capable
`
`of multiple
`
`charge-integration sub-periods,
`
`and preferably,
`
`the
`
`architectures provide for individual charge-integration time per pixel.
`
`Implementation of the present
`
`invention facilitates programming the
`
`charge integration time in numerous, various-timed, small steps. As a result,
`
`hundreds, or even thousands, of exposure-time values are available. This is
`
`important for an effective implementation of dynamic range compression, and
`
`elimination of quantization noise and image artifacts. Hence, exposure timesin
`the range of 2° :
`1
`in unit steps are feasible for motion video.
`This is
`instrumental
`for accomplishing wide dynamic-range scene capture roughly
`
`comparable in performance to the human eye's retina.
`
`20
`
`Furthermore, via novel use of a row-program loader,
`
`the present
`
`invention provides for simultaneous different charge-integration intervals forall
`
`the pixels. The present invention describes loading an entire row program, one
`row at a time, at video rate. Furthermore, this operation is done outside the
`
`image sensor's array.
`Reference is now made to Fig.
`
`1
`
`an illustration of array 10, a novel and
`
`improved non-interlaced type CMOS image-sensor array architecture that
`
`comprises a plurality of unit cells 12 and implements autonomous, per-pixel,
`
`charge-integration control.
`
`Reference is now made in parallel to Fig. 2, an illustration of unit cell 12,
`
`the basic building block of array 10. Unit cell 12 captures light and produces
`electrical signals associated therewith. Preferably, unit cell 12 is capable of
`multiple-integration sub-periods, as
`is
`the unit
`cell described in patent
`10
`
`25
`
`30
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`PCT/1L00/00438
`
`application PCT/1L00/00129, CMOS Unit Cell with Autonomous/Per-Pixel
`Charge Integration Time Control Circuit, filed on March 2, 2000. Application
`PCT/1L00/00129 is co-pending to the same assignees as the invention
`presented herein, and is incorporated herein by reference.
`For purposesof clarity herein, reference to a “unit cell’ is synonymous
`reference
`to
`a
`“pixel”,
`and
`“integration”
`is
`synonymous’ with
`
`with
`
`charge-integration.
`All the unit cells 12 in array 10 undergo a programming cycle,
`in a
`manner to be explained in detail hereinbelow, wherein they are preprogrammed
`for a predetermined integration interval.
`Each such programming cycle is
`followed by the predetermined integration interval. Each such predetermined
`integration cycle may comprise a series of integration sub-periods and/or a
`series of non-integration sub-periods. At
`the completion of the integration
`interval the unit cell 12 is read out. The procedure of reset, programming cycle,
`
`integration cycle, and readout is repeated. An integration interval is defined as
`
`the period of time from reset to readout.
`During the integration sub-periods the preprogrammed unit cell 12
`injects charge into an integration capacitor which resides in unit cell 12. During
`the non-integration sub-periods,
`the integration capacitor stores the collected
`charge, but the preprogrammedunit cell 12 does not inject additional charge into
`the
`capacitor.
`As
`explained in PCT/1L00/00129,
`the
`integration
`and
`non-integration sub-periods may be multiple and alternate between integration
`and non-integration, depending on the predetermined programmedcycle.
`During the integration interval, all the unit cells 12 that are primarily
`enabled for charge integration are “exposed”to the light intensity.
`It
`is noted
`that although the integration interval is the sameforall unit cells 12, the charge
`collected during this period differs from unit cell 12 to unit cell 12. The charge
`accumulated per unit cell 12 is proportional to the effective charge-integration
`time (ie. the summation of the various integration sub-periods for each pixel)
`andto the local intensity of the incidentlight.
`
`10
`
`20
`
`25
`
`30
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`Unit cell 12 retains the so-far accumulated charge on its integration
`
`capacitor, as long it is not actively discharged.
`
`In such a manner, unit cell 12
`
`functions as an analog memory element which retains analog signals.
`
`Hence, the total integration time and total accumulated charge of each
`
`unit cell 12 is dependent on its associated sequence of programmedstates of
`
`integration/non-integration,
`
`such that each sub-period is subject to a different
`
`charge integration. Based upon PCT/1L00/00129, and for the special case
`
`where,
`
`(4)
`
`Tm =2":-To,
`
`k= 0,1,..., G-2, q-1,
`
`To is the basic time unit,
`
`Tm is the Int signal staying “high”in the i-th integration sub-period,
`
`q is the number of program/integration sub-periods in the sequence,
`
`T is the total charge integration time,
`
`then,
`
`(5)
`
`(6)
`
`q-1
`T =[9° Yum 2” or
`m=0
`
`and
`
`T= To + (Ug-1 Ug-2 --- U2 Uy Ud) 2
`
`Therefore the integration interval
`
`is programmable through the binary
`
`number (Ug-1 Ug-2 ... U2 U4 Ug)2.
`When (Ug-1 Ug-2 .-. U2 Uy Uo) 21S (00... 0 1)2 Ti (min) = To is the shortest
`
`20
`
`possible integration time.
`When (ug-1 Ug-2 --. U2 Ur Up) 21S (11... 1 1)2 T results in the longest
`possible integration time, which is,
`(7)
`Tmax = To: (27-1),
`
`25
`
`where,
`
`Tmax is the maximum integration time,
`
`q is the numberof program/integrate sub-periods,
`
`To is the basic charge integration time unit.
`(Ug-1 Ug-2 ... U2 Uy Ug)2 Can be any integer number in between the
`minimum and the maximum values,
`stepped in To units. Therefore,
`the
`
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`integration time can be any valuestarting with To, 2To, 3To...., in To steps, and
`
`up to Tmax.
`
`The collected charge or the corresponding voltage is proportional to the
`
`total integration time, and to the photocurrent magnitude. The photocurrentitself
`
`is proportional to the intensity of the incidentlight.
`
`This is summarized in the following two formulas:
`
`(8)
`
`(9)
`
`where,
`
`Q? = Ion: T,
`
`Vo = lop/Cy- T,
`
`10
`
`Ibn is the photocurrent, T is the total integration time,
`
`C, is the Integration Capacitor’s capacitance,
`
`Q? is the accumulated charge on the Integration Capacitor, and
`
`V‘ is the voltage across the Integration Capacitor.
`
`The implementation of equations (4) — (9) will be explained in detail
`
`15
`
`hereinbelow in connection with Figs. 6 and 12, respectively.
`
`Referring briefly to Fig. 1, array 10 comprises anarray oflines, arranged
`
`in rows along the x-axis and columns along the y-axis. Unit cells 12 are located
`
`at the x, y nodes of the lines, and connected thereto. The lines carry electrical
`
`signals that control the integration interval of each unit cell 12. For purposes of
`
`20
`
`identification, each unit cell 12 is generally designated by its location on the x, y
`
`axis. As such, the unit cell 12 located at (y = 0, x = 0) is identified as unit cell 12
`
`(0,0), and the unit cell located at (y = V - 1, x = H - 1) is identified as unit cell 12
`
`(V- 1, H -1).
`
`Array 10 additionally comprises a multiplicity of circuits located on the
`
`25
`
`horizontal and vertical axis,
`
`respectively.
`
`In one preferred embodiment, a
`
`readout circuit 14 and a row program loader 18 are located along the horizontal
`
`or y-axis, and a row program/read decoder 16 is located along the vertical or
`
`x-axis.
`
`It
`
`is noted that the usage of the terms vertical and horizontal are for
`
`purposesofclarity, and alternative locations of these circuits are included within
`
`30
`
`the scope of the present invention.
`
`In a preferred embodiment, the array of lines includes lines generally
`
`designated row-read (RwRd) lines, row-program (RwPrg) lines, column sense
`
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`lines, and
`(Rst)
`reset
`lines,
`lines, column program (ColPrg)
`(ColSense)
`integration (int) lines. Each line carries an associated signal, i.e. the RwRdline
`carries a RwRd signal and so on.
`
`The location designation of each line is represented by its respective
`location on the x or y axis and is generally designated as such, i.e.:
`the ColPrg
`line located at x = 0 is designated as ColPrg_0 line, and the RwPrgline located
`at y =i is designated as RwPrg_iline.
`Int lines: The Int (i.e. integration) line is one line that splits into multiple
`lines and is connected to all unit cells 12. The Int line carries the Int signal. All
`unit cells 12 are subject to integration controlled by the Int signal. Preferably,
`when the Int signal is high, charge integration takes place. During the integration
`sub period (when the Int signal is high), those associated unit cells 12 that have
`
`been programmedto integrate, do so.
`
`It is noted that even if a specific unit cell 12 is programmedto integrate
`during a specific sub-period,
`integration will take place only if the Int signal is
`high. Conversely, even if the Int signal
`is high,
`if a specific unit cell 12 is
`
`programmednotto integrate, then no integration will take place.
`
`20
`
`Rst lines: The Rst(i.e. reset) line is one line that splits into multiple lines
`and is connected to all unit cells 12. The Rst lines carry a Rst signal which
`drives all the unit cells 12 in array 10 to reset simultaneously. The Rst signal
`activates a transistor that resides in unit cells 12 that drains the residual charge
`which remained after
`the previous
`readout,
`thereby preconditioning the
`integration capacitors for the next integration interval.
`
`It
`
`is noted that, alternatively,
`
`reset does not always need to be
`
`25
`
`performed explicitly, but can be implicitly performed as part of the readout
`
`in which case,
`phase,
`alternatively eliminated.
`
`the Rst
`
`line and the corresponding transistor are
`
`Rwkdlines: In a preferred embodiment, the RwRad(i.e. row-read) lines
`
`are connected to the row program/read decoder 16,
`
`and the location
`
`30
`
`designations of the RwRd lines range from RwRd_0 to RwRd_V-1. Each RwRd
`
`line is connected to the associated unit cells 12 on its respective row. The
`RwRd lines carry a row read (RwRd) signal that controls the readouts of the
`
`14
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`associated unit cells. When the RwRd_i signal is high and all the other RwRd
`
`signals are low, the content of the unit cells 12 (i,j) is read. Typically, unit cells
`
`12 are readout after the completion of the charge integration cycle.
`
`RwPrg lines: In a preferred embodiment, the RwPrg (i.e. row-program)
`
`lines are connected to the row program/read decoder 16, and the location
`
`designations of the RwRd lines range from RwPrg_0 to RwPrg_V-1. Each
`
`RwPrgline is connected to all the associated unit cells 12 on its respective row.
`
`The RwPrg lines carry a row program (RwPrg)
`
`signal
`
`that controls the
`
`programming of the associated unit cells 12. The programming of the unit cells
`
`12 determines the charge integration sequence for each unit cell 12. Preferably,
`
`programming is done in a row-by-row fashion,
`
`i.e., when the RwPrg_i signal is
`
`high and all other RwRd signals are low,
`
`the unit cells 12 in
`
`row i are
`
`programmed.
`
`It is noted that in a preferred embodiment the programming of unit cells
`
`15
`
`12 is performed before the readoutstarts, or off-line. Thus, the time-consuming
`
`task of programming does not affect the integration or read-out timing of array
`
`10.
`
`lt is noted that the RwRd signal and the RwPrg signal function in tandem
`
`with each other. When the RwRd signal is high, the RwPrg signal is low, and
`
`20
`
`visa versa.
`
`RdEn and PrgEn signals: The Rwkd signal activates a RdEn (i.e.
`
`read-enable) signal
`
`that enables the readout of
`
`the accumulated charge
`
`(current/voltage) of the associated unit cell 12.
`
`Similarly,
`
`the RwPrg signal
`
`activates a PrgEn (i.e. program-enable) that enables the programming of the
`
`25
`
`associated unit cell 12.
`
`ColSense and ColPrglines: In a preferred embodiment, the ColSense
`
`(i.e. column-sense) and ColPrg (i.e. column-program) lines run between row
`
`program loader 18 and readout circuit 14.
`
`In one preferred embodiment, the
`
`ColSense lines and ColPrg lines are alternatively active; when the ColSenseline
`
`30
`
`is active - the ColPrg line is inactive, and visa versa. As such,
`
`the same
`
`physical line is usable for both functions. Alternatively, the ColSenselines and
`
`the ColPrg lines are separate physical lines.
`
`15
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