DS 00-001
`
`APPLICATION NOTE
`
`SOLID STATE IMAGE SENSORS
`
`TERMINOLOGY
`
`EASTMAN KODAK COMPANY
`
`MICROELECTRONICS TECHNOLOGY DIVISION
`
`ROCHESTER, NEW YORK 14650-2010
`
`Revision 0
`
`December 8, 1994
`
`Eastman Kodak Company - Microelectronics Technology Division - Rochester NY 14650-2010
` Phone (716)-722-4385 Fax (716)-477-4947
`
`
`Ex.1021 / Page 1 of 55Ex.1021 / Page 1 of 55
`
`TESLA, INC.TESLA, INC.
`
`

`

`DS 00-001
`
`TABLE OF CONTENTS:
`
`Title Page .................................................
`
`Table of Contents....................................
`
`Introduction.............................................
`
`1
`
`2
`
`3
`
`4
`Terminology............................................
`4
`Accumulation Mode............................
`4
`Active Area...........................................
`6
`Blooming...............................................
`7
`Buried Channel CCD ..........................
`8
`CCD Clock............................................
`9
`Charge Capacity ..................................
`Charge Coupled Device (CCD) ......... 10
`Charge Transfer Efficiency (CTE) ..... 10
`Charge Transfer Inefficiency (CTI) ... 11
`Color Filter Array (CFA) .................... 11
`Correlated Double Sampling (CDS) . 12
`Dark Current ........................................ 15
`Dark Reference Pixels ......................... 15
`Data Rate............................................... 16
`Defective Pixel...................................... 16
`Dynamic Range.................................... 16
`Electronic Shutter ................................ 17
`Fill Factor .............................................. 18
`Fixed Pattern Noise............................. 18
`Floating Diffusion................................ 19
`Four Phase CCD .................................. 20
`Frame Rate............................................ 20
`Frame Transfer Image Sensor............ 20
`Full-Frame Image Sensor.................... 22
`Horizontal CCD................................... 23
`Image Sensor ........................................ 24
`Integration Period................................ 24
`Interlaced Image Sensor ..................... 24
`Interline Image Sensor ........................ 25
`Lateral Overflow Drain (LOD) .......... 26
`
`26
`Lenticular Array((Lenslets)................
`Light Shield.......................................... 27
`Linear Image Sensor ........................... 27
`Modulation Transfer Function ......... 28
`Multiple Outputs.................................
`28
`Noise ..................................................... 29
`Non-Interlaced..................................... 29
`Output Amplifier ................................ 30
`Output Linearity.................................. 31
`Output Sensitivity...............................
`33
`Photodiode Lag ................................... 34
`Photoresponse Nonuniformity ......... 37
`Pixel....................................................... 37
`Pixel-to-Pixel Crosstalk ...................... 38
`Potential Well....................................... 40
`Progressive Scan..................................
`41
`Pseudo Two Phase CCD.....................
`41
`Quantum Efficiency............................ 42
`Reset Clock........................................... 43
`Resolution............................................. 44
`Responsivity......................................... 46
`Saturation ............................................. 46
`Schottky Barrier Diodes ..................... 47
`Sensitivity............................................. 47
`Smear..................................................... 47
`Spectral Response................................ 48
`Surface Channel................................... 48
`Three Phase CCD ................................ 49
`Transfer Gate Clock ............................ 50
`True Two Phase CCD .........................
`51
`UV Enhancement Coating ................. 51
`Vertical CCD........................................ 52
`Vertical Overflow Drain (VOD)........ 52
`Wafer Thinning.................................... 53
`
`Bibliography............................................ 54
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 2 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 2 of 55Ex.1021 / Page 2 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`DS 00-001
`
`INTRODUCTION:
`
`This application note has been written to clarify some of the terminology
`used to describe the operation and performance of solid state image
`sensors. It is intended for use by anyone considering using these sensors
`in a systems design, and particularly for first time users. This note
`provides only brief explanations of the common terms encountered in
`image sensor specifications. A listing of suggested readings on solid state
`image sensors and applications is located at the end of this document.
`__________________________________________________________________
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 3 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 3 of 55Ex.1021 / Page 3 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`Accumulation Mode:
`
`Active Area:
`
`DS 00-001
`
`TERMINOLOGY:
`
`Accumulation mode, also referred to as MPP mode (Multi-
`Pinned Phase) is the state in a semiconductor where the
`majority carrier concentration at the oxide-semiconductor
`interface is greater than the substrate or bulk carrier
`concentration. When applied to solid state image sensors, the
`accumulation mode of operation can result in greatly reduced
`dark current and dark pattern noise.
`Accumulation is achieved by applying the appropriate voltage
`levels to the CCD and transfer gates. For an n-type buried
`channel CCD, the majority carriers are holes. To attract holes
`to the SiO2-Si interface, a voltage sufficiently less than the
`substrate potential must be applied.
`Image sensors which gain the most benefit from running in
`accumulation mode are those which operate under long
`integration times. Not all image sensors can support the
`accumulation mode of operation. Many image sensors have
`ESD protection circuitry at the inputs to protect the sensor,
`and these circuits often limit the negative swing of the applied
`voltages to greater than -1.0 volts.
`___________________________________
`
`The surface area of an image sensor which is light sensitive is
`called the active area. In the case of interline and linear
`sensors, this area is usually made up of only the photodiode
`active area, since all other regions on the imager are typically
`covered with a metal layer which prevents incident light from
`being absorbed within the silicon substrate. The area of the
`light sensitive CCD or photodiode (Lp x Wp) may be greater
`than the active area (La x Wa), in which case the metal light
`shield is used to define the smaller active area. In full-frame
`sensors, the active area is defined by this light shield.
`
`Continued on next page(cid:201)
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 4 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 4 of 55Ex.1021 / Page 4 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`Active Area:
`Continued(cid:201)
`
`Photodiode with Aperture Light Shield
`
`Metal Light Shield
`
`Wa
`
`Photodiode
`
`La
`
`W p
`
`Photodiode
`
`e
`
`Silicon Substrate
`
`Array of Photodiodes
`
`Incident
`Photon
`
`Wa
`
`Lp
`
`La
`
`____________________________________
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 5 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 5 of 55Ex.1021 / Page 5 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`Blooming:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`When the maximum charge capacity of the CCD or photo-
`diode is exceeded, the excess charge will overflow into
`adjacent CCD cells or photosites. This overflow of
`photogenerated charge is termed Blooming. The result of
`blooming is a corrupted image near the blooming site. The
`extent of the image degradation is dependent on the level of
`excess charge and on the architecture of the imager being
`used. The effects of blooming can be minimized by
`incorporating an antiblooming structure near the charge
`collection site. Antiblooming structures are constructed so as
`to provide a safe path for the excess photogenerated charge
`(i.e. blooming charge). Vertical antiblooming structures reside
`below the charge collection site and allow excess charge to
`overflow directly into the substrate; whereas, lateral
`antiblooming structures reside adjacent to the charge
`collection site and allow excess charge to overflow into a
`reversed biased diode. Clocking schemes may be used to
`reduce blooming; however, these are less effective at higher
`frame rates.
`
`Lateral Overflow Structure
`
`Overflow
`Drain
`
`Overflow
`Gate
`
`Light
`
`Transfer
`Gate
`
`CCD
`Phase 1
`
`Vertical Overflow Structure
`
`BLOOMING!
`
`Electrostatic Potential
`Distance in Silicon
`
`Light Shield
`
`Field SiO2
`
`Transfer
`Gate
`
`Light
`
`Field SiO2
`
`----------------------------
`
`BLOOMING!
`e
`
`e
`
`e
`
`e
`ee
`
` eee
`e
`
`e
`
`e
`e
`e
`
`e
`
`ee
`ee
`
`e
`
`h
`
`External Bias "OFF"
`
`External Bias "ON"
`
`Electrostatic Potential
`
`________________________________
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 6 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 6 of 55Ex.1021 / Page 6 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`Buried Channel CCD:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`The Charge Coupled Device (CCD) structure can be used in
`image sensors to transport and collect photogenerated charge.
`The physical location of charge contained within a CCD stage
`measured with respect to the surface of the silicon substrate is
`called the channel.
`A buried channel CCD is one in which the channel is located
`some distance below the surface of the silicon. That is, below
`the silicon - silicon dioxide interface (Si-SiO 2 interface), which
`is known to contain a higher density of electron traps and a
`higher dark current. Transferring charge at or near the Si-SiO2
`surface can degrade the charge transfer efficiency (especially
`at higher CCD clocking speeds) and cause an increase in dark
`noise.
`
`Surface Channel
`
`Buried Channel
`
`SiO - Si
`2
`Interface
`
`Electrostatic Potential
`
`Channel
`
`Distance Into Silicon
`______________________________
`
`Zc
`
`Channel
`
`Distance Into Silicon
`
`SiO - Si
`2
`Interface
`
`Electrostatic Potential
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 7 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 7 of 55Ex.1021 / Page 7 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`DS 00-001
`
`TERMINOLOGY: Continued:
`
`Charge Coupled Devices (CCDs) use input timing signals to
`setup the electrostatic potentials necessary to transport charge.
`A two phase CCD will require two input signals, a three phase
`will require three signals, and a four phase CCD will require
`four input signals. The amplitude of the CCD input signals,
`combined with the built in channel potential of each phase,
`will determine the magnitude of the electrostatic potential
`under each phase, and the phase relationships between the
`input clocks will permit the transportation of charge.
`For a two phase CCD, two input timing signals are required
`for operation. For charge to move from phase 1 (f 1) to phase 2
`(f 2), it is necessary that the phase 1 signal turn "OFF" (external
`bias = 0.0 v) and phase 2 signal turn "ON" (external bias >=
`VCCD v). Similarly, the phase 2 signal should be "OFF" and
`the phase 1 signal "ON" to transport charge from phase 2 to
`phase 1. This results in two input timing signals which are
`complements of each other, as shown below. The "ON" /
`"OFF" duty cycle of each clock is typically 50%, but may vary
`as long as the "ON" / "OFF" times meet the specification
`requirements and the signals remain complements of each
`other.
`
`Cross Sectional View of True Two Phase CCD
`
`One CCD Stage (cell)
`
`One CCD Stage (cell)
`
`++++++
`
`++++++
`
`++++++
`
`++++++
`
`N Type Implant
`P Type Implant
`
`2f
`f 1
`
`Electrostatic Potential
`
`CCD Clock:
`
`External Bias "OFF"
`External Bias "ON"
`
`Continued on next page(cid:201)
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 8 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 8 of 55Ex.1021 / Page 8 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`CCD Clock:
`Continued(cid:201)
`
`f 1
`
`2f
`
`Charge Capacity:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`Input Timing for Two Phase CCD
`Tp
`
`The point at which the complementary clock signals cross (e.g.
`50% of amplitude) is very important for optimum operation.
`The phase 1 and phase 2 signals are controlled differently
`during the photodiode to CCD charge transfer. Once the
`charge transfer is complete, the CCD signals again resume the
`complementary pattern.
`____________________________________
`
`The maximum amount of charge that an imager can collect
`and transfer while maintaining all performance specifications
`is termed the saturation charge level and defines charge
`capacity. Charge capacity may be limited by either the
`photosite or CCD capacity. If the charge capacity is exceeded,
`the excess charge will overflow into adjacent structures and
`produce artifacts known as blooming and smear. If an anti-
`blooming structure is adjacent to the charge collection site, the
`excess charge will be prevented from overflowing into
`adjacent charge collection and transport structures; thus,
`prevent blooming from occurring.
`Multiplying the charge capacity (Nsat) by the charge-to-
`voltage conversion factor yields that maximum output
`voltage, or saturation voltage.
`
`dV
`Vsat = Nsat .
`[Volts]
`dN
`
`________________________________
`
`
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 9 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 9 of 55Ex.1021 / Page 9 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`Charge Coupled
`Device:
`
`Charge Transfer
`Efficiency:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`A Charge Coupled Device (CCD) is an integrated circuit
`which allows individual charge packets to be transferred over
`a physical distance while maintaining the original charge
`packet integrity. Charge coupled devices are ideally suited for
`use in solid state imagers as a means of transferring integrated
`photogenerated charge. The CCD may be used to collect the
`photogenerated charge, or it may be placed adjacent to a array
`of photodiodes or photocapacitors. A CCD used to directly
`collect photogenerated charge will have reduced
`photoresponse at shorter optical wavelengths due to the
`presence of polysilicon electrodes.
`Several of the more common CCD structures are described in
`more detail in other sections.
`____________________________________
`
`Charge Transfer Efficiency (CTE) is the fraction of charge
`which is successfully transferred during one CCD transfer
`cycle (note that a phase CCD will have two transfer cycles per
`CCD stage). CTE is equal to one minus the Charge Transfer
`Inefficiency (CTI), or:
`
`CTE = 1 - CTI .
`
`Some manufacturers define CTE as the charge transferred per
`CCD stage, so care should be taken when comparing different
`manufacturer’s specifications for CTI and CTE to ensure that
`both use the same definition. The total charge remaining in a
`CCD stage after being clocked through the entire CCD is
`termed the CTE per line for linear imagers or CTE per frame
`for area array image sensors, and is equal to:
`
`CTE Line = (CTE) CCD_Transfers
`(For Linear Image Sensors)
`
`or:
`
`CTE Frame = (CTE X)X_CCD_Transfers x (CTE Y)Y_CCD_Transfers
`(For Area Array Image Sensors)
`____________________________________
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 10 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 10 of 55Ex.1021 / Page 10 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`DS 00-001
`
`Charge Transfer
`Inefficiency:
`
`TERMINOLOGY: Continued(cid:201)
`
`Charge Transfer Inefficiency (CTI) is the fraction of charge left
`behind during a CCD transfer.
` Care should be taken when comparing different manu-
`facturer’s specifications for CTI or CTE to ensure that both use
`the same definition.
`Charge Transfer Inefficiency is measured by injecting a
`sequence of charge packets of known size into a CCD and then
`monitoring the resultant imager output waveform. Note that
`a two phase CCD will have two transfers per CCD stage. The
`injected signal amplitude and the signal lost from the injected
`signal are then used to calculate CTI as follows:
`
`CTI =
`
`Vlost
`NLost
`Vinjected ·
`Ninjected ·
` CCD_Transfers
` CCD_Transfers
`____________________________________
`
` =
`
`Color Filter Array (CFA): For color imaging applications, it is necessary to separate the
`optical spectrum of the incident image into three color bands.
`In most applications it is desirable to perform the color
`separation on the imager. Color separation is typically
`accomplished by depositing organic dyes on the imager
`surface. The color dyes, or color filters, can be configured to
`work in an additive (RGB) or subtractive (YMC) process. That
`is, the deposited layers may act as transmission filters or as
`absorbing filters. The deposition of three color filters yields
`three bandpass filters, which can be designed to occur in any
`pattern across an imager.
`On tricolor linear imagers, a blue bandpass filter is deposited
`on one whole channel, a green bandpass filter is deposited one
`another channel, and a red bandpass filter is deposited on the
`remaining channel. Thus, a single pass scan of an object
`obtains all color information. Color filter patterns on area
`arrays can also occur in varying arrangements.
`
`____________________________________
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 11 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 11 of 55Ex.1021 / Page 11 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`Correlated Double
`Sampling (CDS):
`
`DS 00-001
`
`TERMINOLGY: Continued(cid:201)
`
`A schematic diagram of a typical image sensor output stage
`and the corresponding image sensor timing are shown below.
`The output stage functions as follows. The reset gate signal
`(f R) is turned "ON" to reset the floating diffusion node. Then
`reset is turned "OFF" and the output signal is allowed to settle.
`Next the phase 2 CCD clock (f 2) is turned "OFF" and the phase
`1 CCD clock (f 1)turned "ON". As the phase 2 CCD clock turns
`"OFF", the charge in the last phase 2 stage is dumped onto the
`floating diffusion node and the output signal is allowed to
`settle at its new value. Finally, the reset gate signal is again
`turned "ON" and the cycle repeats.
`The voltage level of the output signal after the reset gate has
`turned "OFF" and before phase 2 is turned "OFF" is called the
`reset level. This level is typical in the range of 7 to 9 volts. The
`reset level will have a noise component due to variations in
`the effective "ON" resistance of the reset transistor (Q1). This
`noise is very small, but detectable in very high dynamic range
`systems.
`
`Output Circuitry
`
`Reset
`Dr ain
`
`VDD
`
`Out put
`
`-+
`
`Q4
`
`Q2
`
`Q3
`
`Continued on next page(cid:201)
`
`Reset
`
`Q1
`
`2f
`
`OG
`
`Floating
`Diffusion
`
`e
`
`e e
`
`e ee
`ee
`e e e
`e
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 12 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 12 of 55Ex.1021 / Page 12 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`DS 00-001
`
`Correlated Double
`Sampling (CDS):
`Continued(cid:201)
`
`TERMINOLOGY: Continued(cid:201)
`
`Signal Timing
`
`1
`
`2
`
`R
`
`Output
`
`Bright
`Input Light
`Intensity
`
`Dark
`
`Typical saturation voltages are in the range of 1 to 3 volts.
`This makes the lowest level of the output signal about 4 volts
`(7 - 3). Most analog-to-digital converters will not accept inputs
`signals in this range, so some signal processing must be
`performed on the output signal.
`The goals of processing the output signal are to (1) remove the
`reset level noise, and (2) translate the output signal to a level
`acceptable by analog to digital converters. Goal number 1 is
`met by performing a differential measurement on each
`photosite (also known as Correlated Double Sampling, or
`CDS), and goal number 2 is achieved by converting the output
`signal to a ground referenced, positive going signal.
`
`Continued on next page(cid:201)
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 13 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 13 of 55Ex.1021 / Page 13 of 55
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`TESLA, INC.TESLA, INC.
`
`f
`f
`f
`

`

`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`Correlated Double
`Sampling (CDS):
`Continued(cid:201)
`
`The timing required to perform the CDS signal processing is
`shown below. There are several common circuits used to
`perform the CDS function; however, all make a differential
`measurement.
`
`CDS Timing Signals
`
`Output
`
`C
`(clamp)
`
`S
`(sample)
`
`One method is to AC couple the output signal and then clamp
`it to ground during the flat reset portion of the signal.
`Variations in the output which occur after the clamp is
`complete will be with respect to ground. Then the ground
`referenced signal is passed through an inverting amplifier,
`resulting in a positive going ground referenced signal. Only
`one additional sample pulse is required to complete the
`processing by sampling the signal during the active portion of
`the signal (i.e. during the time when the phase 2 CCD input is
`"OFF").
`The clamped and sampled signal is then ready for direct input
`into an analog-to-digital converter.
`Another method uses two sample pulses to charge one
`capacitor to the reset level and another to the active portion of
`the output. The two signals are then fed into an inverting
`differential amplifier where a difference measurement is
`performed and the signal is converted to a positive going,
`ground referenced signal.
`____________________________________
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 14 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 14 of 55Ex.1021 / Page 14 of 55
`
`TESLA, INC.TESLA, INC.
`
`f
`f
`

`

`Dark Current:
`
`Dark Reference Pixels:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`Dark signal is a termed used to refer to the background signal
`present in the image sensor readout when no light is incident
`upon the image sensor. This background signal is a result of
`thermally emitted charge being collected in the photosites
`transfer gates, and CCDs. The magnitude of the dark signal is
`dependent on the image sensor architecture, mode of
`operation (see Accumulation Mode), and on the image sensor
`operating temperature. Due to the present of localized defects
`in the silicon substrate, the dark signal collected in each pixel
`will vary from pixel to pixel. This variation in dark signal is
`called the dark signal noise. The average current associated
`with the readout of a complete dark image is referred to as the
`dark current. The dark current will double for approximately
`every 9¡C increase in image sensor temperature.
`___________________________________________
`
`Dark reference pixels are groups of photo-sensitive pixels
`covered by a metal light shield. These pixels are used as a
`black level reference for the image sensor output. Since the
`incident light is blocked from entering these pixels, the signal
`contained in these pixels is due only to dark current. It is
`assumed that each photo-sensitive pixel (active and dark
`reference) will have approximately the same dark signal; thus,
`subtracting the average dark reference signal from each active
`pixel signal will remove the background dark signal level.
`Dark reference pixels are typically located at one or both ends
`of the arrays, as shown below for a linear image sensor.
`
`Single Channel of Linear Image Sensor
`
`LS
`LOG
`Photodiodes
`TG1
`TG2
`
`SG
`IG
`ID
`
`f 2f 1
`
`f R
`
`RD
`
`VDD
`
`FD
`
`VID
`
`Dark Reference Photodiode
`Active Photodiode
`___________________________________________
`
`OGSUB
`VSS
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 15 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 15 of 55Ex.1021 / Page 15 of 55
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`TESLA, INC.TESLA, INC.
`
`

`

`Data Rate:
`
`Defective Pixel:
`
`Dynamic Range:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`The data rate is the total number of pixels being clocked off an
`imager over a period of time. If the imager has only one
`output, then the data rate is typically equal to the horizontal
`CCD clocking rate. An imager with two outputs will have a
`data rate equal to two times the horizontal CCD clocking rate,
`assuming both outputs are clocked out in parallel.
`____________________________________
`
`A defective pixel is one whose response to illumination
`variations differs significantly from the mean response of all
`other pixels. The maximum deviation from the mean response
`permitted is imager as well as application dependent. The
`number and type of defects acceptable is also application
`dependent, and can range from zero to as many as 1000
`defects in some cases. It is sometimes possible to remove the
`effect of the defective pixel by applying one of several signal
`processing defect correction algorithms. One of the simplest
`such algorithms is to replace the defective pixel with the
`average response of the two nearest neighboring pixels.
`(i.e. Pd = (Pd-1 + Pd+1) / 2).
`___________________________________________
`
`Dynamic Range (DR) is the ratio of the maximum output
`signal, or saturation level, of an image sensor to the dark noise
`level of the imager. The dark noise level, or noise floor of an
`imager is typically expressed as the root mean square (rms)
`variation in dark signal voltage. The dark signal includes
`components from dark current within the photosite and CCD
`regions, reset transistor and output amplifier noise, and input
`clocking noise. An input referred noise signal in the charge
`domain can be calculated by dividing the dark noise voltage
`by the imager charge-to-voltage conversion factor. The
`dynamic range is typically expressed in units of decibels as:
`
`Vsat
`
`VDark,rms ł(cid:246)(cid:247)(cid:247)(cid:247)(cid:247)(cid:247)
`
` = 20 . LOG
`DR = 20 . LOG
`
`
`____________________________________
`
`Nsat
`
`NDark,rms ł(cid:246)(cid:247)(cid:247)(cid:247)(cid:247)(cid:247)
`
`
`
`[dB]
`
`
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 16 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 16 of 55Ex.1021 / Page 16 of 55
`
`TESLA, INC.TESLA, INC.
`
`Ł(cid:230)(cid:231)(cid:231)(cid:231)(cid:231)(cid:231)
`Ł(cid:230)(cid:231)(cid:231)(cid:231)(cid:231)(cid:231)
`

`

`Electronic Shutter:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`An electronic shutter is used to vary the effective integration
`time (Teff) of a group of pixels. The circuitry used to perform
`the shuttering drains all charge out of the photosensitive pixel
`for a fraction of the total integration time (Tint).
`When used on tri-linear image sensor arrays, the electronic
`shutter can be used to balance the color response of the red,
`green and blue channels.
`
`Typical Electronic Shutter Timing
`
`Transfer
`Gate
`
`Exposure
`Control Gate
`(LOG)
`
`Tint
`
`T eff
`
`Single Channel of Linear Image Sensor
`
`LS
`LOG
`Photodiodes
`TG1
`TG2
`
`f R
`
`RD
`
`VDD
`
`FD
`
`VID
`
`OG SUB
`Cross Sectional View of Lateral Electronic Shutter
`
`VSS
`
`Scanvenger
`Diode
`
`Exposure
`Control Gate
`
`Incident
`Photon
`
`Transfer
`Gate #1
`
`Transfer
`Gate #2
`
`CCD
`Phase 1
`
`Metal
`Light Shield
`
`+++++++++++++++++++
`
`Photodiode
`
`++++++
`
`+++++++++++++
`
`External Bias "OFF"
`External Bias "ON"
`
`____________________________________
`
`SG
`IG
`
`ID
`
`f 2f 1
`
`Electrostatic Potential ( )
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 17 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 17 of 55Ex.1021 / Page 17 of 55
`
`TESLA, INC.TESLA, INC.
`
`y
`

`

`Fill Factor:
`
`Fixed Pattern Noise:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`The fill factor is the ratio of the light sensitive area to the total
`photosite area. Fill factor on some types of area arrays can be
`improved using lenlets (see Lenticular Arrays).
`____________________________________
`
`If the output of an image sensor under no illumination is
`viewed at high gain a distinct non-uniform pattern, or fixed
`pattern noise, can be seen. This fixed pattern can be removed
`from the video by subtracting the dark value of each pixel
`from the pixel values read out in all subsequent frames. Dark
`fixed pattern noise is usually caused by variations in dark
`current across an imager, but can also be caused by input
`clocking signals abruptly starting or stopping or by having the
`CCD clocks not being close compliments of each other.
`Mismatched CCD clocks can result in high instantaneous
`substrate currents, which when combined with the fact that
`the silicon substrate has some non zero resistance can result in
`the substrate potential bouncing. The pattern noise can also be
`seen when the imager is under uniform illumination. An
`imager which exhibits a fixed pattern noise under uniform
`illumination and shows no pattern in the dark is said to have
`Light pattern noise or Photosensitivity pattern noise. In
`addition to the reasons mentioned above, light pattern noise
`can be caused by the imager entering saturation, the
`nonuniform clipping effect of the antiblooming circuit, and by
`non-uniform, photosensitive pixel areas often caused by debris
`covering portions of some pixels.
`
`___________________________________________
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 18 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 18 of 55Ex.1021 / Page 18 of 55
`
`TESLA, INC.TESLA, INC.
`
`

`

`Floating Diffusion:
`
`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`The floating diffusion is the charge sensing node used to
`convert the charge packets carried by the CCD into a voltage
`change which can be detected at the imager output. The term
`floating diffusion describes the charge sensing node structure,
`which is typically formed by implanting and diffusing a N-
`type dopant into a P-type substrate. During operation, the N
`side of the diode (the diffusion) is reset to a positive potential
`by the reset transistor (Q1) and then allowed to float. When
`charge is subsequently dumped onto the floating diffusion a
`proportional change in voltage occurs. The change in voltage
`due to a charge packet of size D N on the charge sensing node
`will be D V = q D N / C, where C is the effective node
`capacitance and q is the elementary charge.
`
`Typical Image Sensor Output Amplifier
`Reset
`Dr ain
`
`VDD
`
`Out put
`
`-+
`
`Q4
`
`Q2
`
`Q3
`
`Reset
`
`Q1
`
`2f
`
`OG
`
`Floating
`Diffusion
`
`e
`
`e e
`
`e ee
`ee
`e e e
`e
`
`____________________________________
`
`____________________________________________________________________________________________________
`DS 00-001, Revision No. 0.
`Page 19 of 54
`Effective Date: 1994-12-08
`
`
`Ex.1021 / Page 19 of 55Ex.1021 / Page 19 of 55
`
`TESLA, INC.TESLA, INC.
`
`

`

`DS 00-001
`
`TERMINOLOGY: Continued(cid:201)
`
`Four Phase CCD:
`
`A four phase CCD is one which requires four polysilicon
`electrodes to make up one CCD cell. Four phase CCDs require
`four input clocks to properly transport charge.
`
`N Type Implant
`
`Four Phase CCD
`One CCD Stage (cell)
`
`4f
`3
`2f
`f 1
`- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
`
`External Bias "OFF"
`External Bias "ON"
`
`Electrostatic Potential ( )y
`
`Frame Rate:
`
`The frame period (Tp) of an imager is the time lapsed between
`successive image readouts, and the frame rate is the number of
`images which can be read out during one second (Fp = 1/Tp).
`
`Frame Transfer Image
`Sensors:
`
`____________________________________
`
`A frame transfer image sensor is similar to the full frame
`imager with the addition of an optically isolated frame storage
`region. These devices operate by first turning "OFF" the
`vertical CCDs and opening the external shutter. At the end of
`the integration time, the image in region A is quickly
`transferred into region B, which is not light sensitive.
`
`Continued on next page(cid:201)
`
`__________________________________________________