`
`Eastman Kodak Company
`Technical Data
`Kodak Digital Science KAC-0311 Image Sensor
`
`Key Specifications
`
` •
`
` Pixel Size: 7.8µm x 7.8µm
`• Fill factor: 40%
`Image Size: 5.0mm x 3.7mm (1/3”)
`•
`• Responsivity: 90,000 electrons/Lux-sec
`• Saturation Signal: 45,000 electrons
`• Min Light: 5 Lux at 30FPS/F2 lens
`• Scan Modes: Progressive/Interlace
`• Operation Modes: Continuous & Single
`• Shutter Modes: Rolling or Global
`• Nominal Readout Rate: 14 MHz
`• Maximum Readout Rate: 20 MSPS
`• Frame Rate: 0-60 frames per second
`• System Dynamic Range: 49 dB
`• Programmable gain: -3.0dB to 17.4dB
`• ADC: 10-bit, RSD ADC (DNL +/-0.5
`LSB, INL +/-1.0 LSB)
`• Power Dissipation: 215mW (dynamic) /
`25mW (standby)
`
` KAC – 0311
`640 x 480 VGA CMOS Image Sensor
`Fully Integrated Timing, Analog Signal
`Processing & 10 bit ADC
`
`Features
`• 1/3” Color VGA Digital Image Sensor
`• 640 x 480 pixel progressive/interlace scan
`• 7.8µm square pixels with patented pinned photodiode
`architecture
`• Bayer - CMY CFA, Monochrome
`• High sensitivity, quantum efficiency, and charge con-
`version efficiency
`• Low fixed pattern noise / Wide dynamic range
`• Patented Electronic Shutter Operation
`• 30fps full VGA at 10MHz Master Clock Rate
`• 60fps full VGA at 20MHz Master Clock Rate
`• Antiblooming and continuous variable speed shutter
`• 10x linear programmable gain
`• 10-bit, pipelined algorithmic RSD ADC
`• User selectable digital output formats:
`• 8-bit companded data
`• 10-bit linear data
`• Pixel addressability to support ‘Window of Interest’
`windowing, resolution, and sub-sampling
`• Analog column offset correction
`Integrated on-chip timing/logic circuitry
`•
`• Digitally programmable via I2C interface
`• CDS sample and hold for suppression of low fre-
`quency and correlated reset noise
`• Dark reference pixels with automatic Frame Rate
`Clamp
`• Single master clock operation
`• Single 3.3V power supply
`• 48 pin CLCC package
`
`
`
`
`
`
`Release Date: 8/5/2002
`
`Eastman Kodak Company - Image Sensor Solutions
`
`
`For the most current information regarding this product:
`Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
`
`Revision No. 1
`Page 1 of 56
`
`
`
`Ex.1010 / Page 1 of 56Ex.1010 / Page 1 of 56
`
`TESLA, INC.TESLA, INC.
`
`

`

`
`
`Eastman Kodak Company
`Technical Data
`Kodak Digital Science KAC-0311 Image Sensor
`
`ADC0
`
`ADC1
`
`ADC2
`
`ADC3
`
`ADC4
`
`ADC5
`
`ADC6
`
`ADC7
`
`ADC8
`
`ADC9
`
`1234567
`
`48
`47
`46
`
`N/C N/C
`15
`14
`
`N/C N/C N/C N/C
`35
`34
`33
`32
`
`N/C N/C
`37
`36
`
`N/C N/C
`39
`38
`
`N/C
`40
`
`N/C
`41
`
`4Dark + 8Isolation
`
`704
`
`512
`
`8Dark + 8Isolation
`
`VGA ACI Image Sensor Array
`
`480
`
`640
`
`12Dark + 8Isolation
`
`40Dark + 8Isolation
`
`0 1
`
`01
`
`Row Decoder and Drivers
`
`Column
`Sequencer
`& Drivers
`
`Column Decode, Sensing, CDS, and Muxing
`
`Master Row Sequencer,
`
`and Timing Generator
`Integration Control,
`
`SOF
`
`VCLK
`
`HCLK
`
`TRIGGER
`
`INIT
`
`MCLK
`
`45
`44
`43
`
`30
`
`28
`
`24
`
`CFRCA
`
`21
`
`CFRCB
`
`Frame
`Rate
`Clamp
`
`Column
`DOVA
`
`2.0x
`6dB
`
`Global
`Dova
`
`2.0x
`6dB
`
`20
`
`18
`19
`
`13
`
`CVREFM
`
`CVREFP
`
`EXTRES
`
`6
`
`Bandgap
`Reference
`and Bias
`Generation
`
`-1.51 → 8.72 dB
`WB
`PGA
`0.84 →
`2.73x
`
`6
`Mux and
`Color Sequencer
`
`6
`
`6
`
`6
`
`6
`
`-1.51 → 8.72 dB
`Exposure
`PGA A&B
`0.84 →
`2.73x
`
`6
`
`6
`
`10 Bit
`RSD
`Pipelined
`ADC
`
`I2C Serial
`Interface and
`Register Decode
`
`26
`
`25
`
`SDATA
`
`SCLK
`
`29
`
`TS
`
`27
`
`STBY
`
`10
`
`BLANK
`
`42
`
`DVSS
`
`9 DVSS
`
`31
`
`DVDD
`
`8
`
`DVDD
`
`23
`
`AVSS
`
`17
`
`AVSS
`
`12
`
`AVSS
`
`22
`
`AVDD
`
`16
`
`AVDD
`
`11
`
`AVDD
`
`
`
`Figure 1: KAC-0311 Block Diagram
`
`The KAC-0311 is a fully integrated, high performance 1/3” optical format VGA CMOS image sensor including integrated
`timing control and programmable analog signal processing. This sensor provides system designers a complete imaging solu-
`tion with a monolithic image capture and processing engine. System benefits enable design of smaller, portable, low cost and
`low power systems. Each pixel on the sensor is individually addressable allowing the user to control the “Window of Inter-
`est” (WOI), panning and zooming, sub-sampling, resolution, exposure, white balance, and other image processing features
`via a two pin I2C compatible interface. This device runs from a single 3.3V supply and single master clock.
`The imager uses Kodak’s patented Pinned Photodiode CMOS active pixels. The 7.8µm pixel design provides true correlated
`double sampling for low read noise operation, high quantum efficiency, low dark current, and no image lag. Kodak’s pat-
`ented pixel design combined with low noise mixed signal circuits provides a high sensitivity, low noise integrated “camera
`on a chip”.
`
`
`
`
`
`
`
`Eastman Kodak Company - Image Sensor Solutions
`
`
`For the most current information regarding this product:
`Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
`
`Revision No. 1
`Page 2 of 56
`
`
`
`Ex.1010 / Page 2 of 56Ex.1010 / Page 2 of 56
`
`TESLA, INC.TESLA, INC.
`
`

`

`
`
`Eastman Kodak Company
`Technical Data
`Kodak Digital Science KAC-0311 Image Sensor
`
`Power Value
`
`Description
`
`Pin
`Pin
`Name
`No.
`I2C Serial Clock Line
`SCLK
`25
`I2C Serial Data Line
`SDATA
`26
`Power Down Standby Enable
`STBY
`27
`Sensor Initialize
`INIT
`28
`Dig Output Tri-State Enable
`TS
`29
`TRIGGER Still Frame Capture Trigger
`30
`31 DVDD
`Digital Power
`32 NC
`Unused
`33 NC
`Unused
`34 NC
`Unused
`35 NC
`Unused
`3.3 V
`36 NC
`Unused
`0 V
`27k Ω 37 NC
`Unused
`38 NC
`Unused
`39 NC
`Unused
`40 NC
`Unused
`41 NC
`Unused
`42 DVSS
`Digital Ground
`43 HCLK
`Pixel Sync
`44 VCLK
`Line Sync
`45
`SOF
`Start of Frame Sync
`46 ADC9
`Output Bit 9=512d
`47 ADC8
`Output Bit 8=256d
`48 ADC7
`Output Bit 7=128d
`
`3.3 V
`0 V
`
`3.3 V
`0 V
`0.1µF
`0.1µF
`1.0µF
`1.0µF
`3.3 V
`0 V
`
`Pin
`Type
`I
`I/O
`I
`I
`I
`I
`P
`I
`I
`I
`I
`I
`I
`I
`I
`I
`I
`G
`O
`O
`O
`O
`O
`O
`
`Power
`
`Value
`
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`
`3.3 V
`
`0 V
`
`
`
`Description
`
`Pin
`Pin
`Name
`No.
`Output Bit 6=64d
`ADC6
`1
`Output Bit 5=32d
`ADC5
`2
`Output Bit 4=16d
`ADC4
`3
`Output Bit 3=8d
`ADC3
`4
`Output Bit 2=4d
`ADC2
`5
`Output Bit 1=2d
`ADC1
`6
`Output Bit 0=1d
`ADC0
`7
`Digital Power
`DVDD
`8
`Digital Ground
`DVSS
`9
`Pixel Invalid
`10 BLANK
`Analog Power
`11 AVDD
`Analog Ground
`12 AVSS
`External Bias Resistor
`13
`EXTRES
`Unused
`14 NC
`Unused
`15 NC
`Analog Power
`16 AVDD
`Analog Ground
`17 AVSS
`18 CVREFM ADC Bottom Bias Ref Capacitor
`19 CVREFP ADC Top Bias Ref Capacitor
`20 CFRCB
`Frame Rate Clamp Capacitor
`21 CFRCA
`Frame Rate Clamp Capacitor
`22 AVDD
`Analog Power
`23 AVSS
`Analog Ground
`24 MCLK
`Master Clock = Pixel Rate
`
`Pin
`Type
`O
`O
`O
`O
`O
`O
`O
`P
`G
`O
`P
`G
`I
`
`P
`G
`O
`O
`O
`O
`P
`G
`I
`
`D
`D
`D
`D
`D
`D
`D
`D
`D
`D
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`A
`D
`
`
`KAC-0311 Pin Definitions
`
`30
`
`29
`
`28
`
`27
`
`26
`
`25
`
`24
`
`23
`
`22
`
`21
`
`20
`
`19
`
`
`
`42
`
`41
`
`40
`
`39
`
`38
`
`37
`
`36
`
`35
`
`34
`
`33
`
`32
`
`31
`
`Die Center
`
`Optical
`Center
`
`Die Placement
`position tolerance
`±200um (±7.9mil)
`
`Row 0
`
`1225.5um(48.2mil)
`
`(0,0)
`
`Column 0
`
`181.5um (7.1mil)
`
`0.280" (7.11mm)
`
`0.280" (7.11mm)
`
`43
`
`44
`
`45
`
`46
`
`47
`
`48 1
`
`2 3 4 5 6
`
`7
`
`8
`
`9
`
`10
`
`11
`
`12
`
`13
`
`14
`
`15
`
`16
`
`17
`
`18
`
`Figure 2 Pinout Diagram
`
`Legend:
`P = VDD
`G = VSS
`I = Input
`O = Output
`D = Digital
`A = Analog
`
`
`
`
`
`
`
`Eastman Kodak Company - Image Sensor Solutions
`
`
`For the most current information regarding this product:
`Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
`
`Revision No. 1
`Page 3 of 56
`
`
`
`Ex.1010 / Page 3 of 56Ex.1010 / Page 3 of 56
`
`TESLA, INC.TESLA, INC.
`
`

`

`
`
`Eastman Kodak Company
`Technical Data
`Kodak Digital Science KAC-0311 Image Sensor
`
`Table Of Contents
`Overview .....................................................................................................................................................................7
`1
`Sensor Interface...........................................................................................................................................................8
`2
`Pixel Architecture........................................................................................................................................................8
`2.1
`Color Filters.................................................................................................................................................................9
`2.2
`Frame Capture Modes ...............................................................................................................................................10
`2.3
`2.3.1 Continuous Frame Rolling Shutter Capture Mode (CFRS).......................................................................................10
`2.3.2
`Single Frame Rolling Shutter capture mode (SFRS).................................................................................................10
`2.3.3
`Single Frame Global Shutter capture mode (SFGS) .................................................................................................10
`2.3.4
`Image Scan Modes ....................................................................................................................................................10
`2.3.5 Window of Interest Control.......................................................................................................................................11
`2.3.6
`Sub-Sampling Control(Resolution)...........................................................................................................................11
`2.4
`Virtual Frame (VF)....................................................................................................................................................11
`2.5
`Integration Time........................................................................................................................................................12
`2.5.1 CFRS Integration Time .............................................................................................................................................12
`2.5.2
`SFRS Integration Time..............................................................................................................................................12
`2.5.3
`SFGS Integration Time Control ................................................................................................................................12
`2.6
`Frame Rate ................................................................................................................................................................12
`2.6.1 CFRS Frame Rate......................................................................................................................................................13
`2.6.2
`SFRS Frame Rate ......................................................................................................................................................13
`2.6.3
`SFGS Frame Rate......................................................................................................................................................13
`3
`Analog Signal Processing Chain Overview ..............................................................................................................14
`3.1
`Correlated Double Sampling (CDS)..........................................................................................................................14
`3.2
`Frame Rate Clamp (FRC)..........................................................................................................................................14
`3.2.1 Column Digital Offset Voltage Adjust (DOVA).......................................................................................................15
`3.2.2 Digitally Programmable Gain Amplifiers (DPGA)...................................................................................................15
`3.2.3 White Balance Control PGA .....................................................................................................................................15
`3.2.4 Global Gain PGA ......................................................................................................................................................16
`3.2.5 Global Digital Offset Voltage Adjust (DOVA).........................................................................................................16
`3.2.6 Analog to Digital Converter (ADC)..........................................................................................................................16
`3.2.7 Digital Signal Post Processing Data Compander ......................................................................................................17
`4
`Additional Operational Conditions............................................................................................................................17
`4.1
`Initialization...............................................................................................................................................................17
`4.2
`Standby Mode ...........................................................................................................................................................17
`4.3
`Internal Bias Current Control ....................................................................................................................................17
`4.4
`Readout Speed...........................................................................................................................................................18
`5
`KAC-0311 Waveform Diagrams...............................................................................................................................19
`5.1
`CFRS Data Waveforms .............................................................................................................................................19
`5.2
`SFGS Data Waveforms .............................................................................................................................................21
`6
`KAC-0311 Register Reference Map .........................................................................................................................22
`7
`Detailed Register Block Assignments .......................................................................................................................25
`7.1
`Color Gain Registers 00h (cid:198) 03h ..............................................................................................................................25
`7.2
`Reference Voltage Adjust Registers (0Ah, 0Bh)........................................................................................................27
`7.3
`Power Configuration Registers (0Ch)........................................................................................................................28
`7.4
`Reset and Tristate Control Register (0Eh) .................................................................................................................29
`7.5
`Global Gain Register (10h) ........................................................................................................................................29
`7.6
`Column DOVA DC Register (20h)............................................................................................................................30
`
`
`
`
`
`
`
`Eastman Kodak Company - Image Sensor Solutions
`
`
`For the most current information regarding this product:
`Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
`
`Revision No. 1
`Page 4 of 56
`
`
`
`Ex.1010 / Page 4 of 56Ex.1010 / Page 4 of 56
`
`TESLA, INC.TESLA, INC.
`
`

`

`
`
`Eastman Kodak Company
`Technical Data
`Kodak Digital Science KAC-0311 Image Sensor
`
`7.7
`7.8
`7.9
`7.10
`7.11
`7.12
`7.13
`7.14
`7.15
`7.16
`7.17
`7.18
`8
`8.1
`8.2
`8.3
`8.4
`8.5
`8.6
`8.7
`8.8
`8.9
`8.10
`9
`
`
`Column DOVA Control (21h) ...................................................................................................................................31
`Column DOVA RAM (22h) ......................................................................................................................................32
`Global DOVA (23h) ..................................................................................................................................................33
`Post ADC Control (32h) ............................................................................................................................................34
`Capture Mode Control (40h)......................................................................................................................................35
`Subsample Control (41h) ...........................................................................................................................................36
`Programmable Window of Interest (WOI) (45h-4Ch)................................................................................................37
`Integration Time Control (4Dh (cid:198) 4Fh)......................................................................................................................40
`Programmable Virtual Frame (50h (cid:198) 53h)................................................................................................................41
`SOF Control Register (54h) .......................................................................................................................................43
`VCLK Control Register (55h)....................................................................................................................................43
`Internal Timing Control Register (60h).....................................................................................................................44
`I2C Serial Interface ....................................................................................................................................................45
`KAC-0311 I2C Bus Protocol .....................................................................................................................................46
`START Signal ...........................................................................................................................................................46
`Slave Address Transmission .....................................................................................................................................46
`Acknowledgment.......................................................................................................................................................46
`Data Transfer.............................................................................................................................................................46
`Stop Signal ................................................................................................................................................................47
`Repeated START Signal ...........................................................................................................................................47
`I2C Bus Clocking and Synchronization.....................................................................................................................47
`Register Write ...........................................................................................................................................................47
`Register Read ............................................................................................................................................................48
`Electrical Characteristics ...........................................................................................................................................50
`Table Of Figures
`Figure 1: KAC-0311 Block Diagram ........................................................................................................................................2
`Figure 2 Pinout Diagram ..........................................................................................................................................................3
`Figure 3: KAC-0311 Spectral Response....................................................................................................................................9
`Figure 4: Optional Bayer CMY Pattern CFA ............................................................................................................................9
`Figure 5: WOI Definition ........................................................................................................................................................11
`Figure 6: Bayer ½ x ½ Sub-sample Example. .........................................................................................................................11
`Figure 7: Virtual Frame Definition..........................................................................................................................................12
`Figure 8: Conceptual block diagram of CDS...........................................................................................................................14
`Figure 9: FRC Conceptual Block Diagram..............................................................................................................................14
`Figure 10: Color Gain Register Selection................................................................................................................................16
`Figure 11: Available Companding Curves ..............................................................................................................................17
`Figure 12: Power Consumption dependence on External Resistor..........................................................................................18
`Figure 13 : Dynamic Range wrt Mclk Frequency ...................................................................................................................18
`Figure 14: CFRS Default Frame Sync Waveforms .................................................................................................................19
`Figure 15: CFRS Default Row Syncs Waveforms ..................................................................................................................19
`Figure 16: SFRS Single Frame Mode Sync Waveforms .........................................................................................................20
`Figure 17: SFRS Interlaced Scan Mode Sync Waveforms......................................................................................................21
`Figure 18: Frame View of SFGS Sync Waveforms ................................................................................................................21
`Figure 19: One row view of SFGS Sync Waveforms..............................................................................................................21
`Figure 20: I2C Bus WRITE Cycle ...........................................................................................................................................45
`Figure 21: I2C Bus READ Cycle .............................................................................................................................................49
`
`
`
`
`
`
`
`Eastman Kodak Company - Image Sensor Solutions
`
`
`For the most current information regarding this product:
`Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
`
`Revision No. 1
`Page 5 of 56
`
`
`
`Ex.1010 / Page 5 of 56Ex.1010 / Page 5 of 56
`
`TESLA, INC.TESLA, INC.
`
`

`

`
`
`Eastman Kodak Company
`Technical Data
`Kodak Digital Science KAC-0311 Image Sensor
`
`Figure 22: I2C Bus Timing ......................................................................................................................................................52
`Figure 23: Pixel Data Bus Timing Diagram ............................................................................................................................53
`Figure 24: 48 Terminal ceramic leadless chip carrier..............................................................................................................54
`Figure 25: Focal plane with respect to package.......................................................................................................................55
`Figure 26: Center of the focal plane array with respect to the die cavity (top view)...............................................................56
`
`List Of Tables
`Table 1: I2C Address Ranges...................................................................................................................................................22
`Table 2 : I2C Initialization Register Script...............................................................................................................................22
`Table 3: I2C Address Assignments (0h- 3Fh) ...........................................................................................................................23
`Table 4: I2C Address Assignments (40h - FFh) ........................................................................................................................24
`Table 5: DPGA Color 1 Gain Register (00h) ...........................................................................................................................25
`Table 6: DPGA Color 2 Gain Register (01h) ...........................................................................................................................25
`Table 7: DPGA Color 3 Gain Register (02h) ...........................................................................................................................26
`Table 8: DPGA Color 4 Gain Register (03h) ...........................................................................................................................26
`Table 9: Negative Voltage Reference Register (0Ah)..............................................................................................................27
`Table 10: Positive Voltage Reference Register (0Bh)..............................................................................................................27
`Table 11: Power Configuration Register (0Ch)........................................................................................................................28
`Table 12: Reset and Tristate Control Register (0Eh) ...............................................................................................................29
`Table 13: DPGA Global Gain Register (10h) ..........................................................................................................................29
`Table 14: Column DOVA DC Offset (20h) .............................................................................................................................30
`Table 15: Column DOVA Control (21h)..................................................................................................................................31
`Table 16: Column DOVA RAM (22h).....................................................................................................................................32
`Table 17: Global DOVA Register (23h) ..................................................................................................................................33
`Table 18: Post ADC Control Register (32h) ............................................................................................................................34
`Table 19: Capture Mode Register (40h)...................................................................................................................................35
`Table 20: Sub-Sample Control Register (41h) .........................................................................................................................36
`Table 21: WOI Row Pointer MSB Register (45h) ...................................................................................................................37
`Table 22: WOI Row Pointer LSB Register (46h) ....................................................................................................................37
`Table 23: WOI Column Pointer MSB Register (49h) ..............................................................................................................37
`Table 24: WOI Column Pointer LSB Register (4Ah) ..............................................................................................................38
`Table 25: WOI Row Depth MSB Register (47h) .....................................................................................................................38
`Table 26: WOI Row Depth LSB Register (48h) ......................................................................................................................38
`Table 27: WOI Column Depth MSB Register (4Bh) ...............................................................................................................39
`Table 28: WOI Column Depth LSB Register (4Ch) ................................................................................................................39
`Table 29: Integration Time MSB Register (4Dh).....................................................................................................................40
`Table 30: Integration Time ISB Register (4Eh) .......................................................................................................................40
`Table 31: Integration Time LSB Register (4Fh) ......................................................................................................................40
`Table 32: Virtual Frame Row Depth MSB (50h).....................................................................................................................41
`Table 33: Virtual Frame Row Depth LSB (51h) ......................................................................................................................41
`Table 34: Virtual Frame Column Width MSB (52h) ...............................................................................................................42
`Table 35: Virtual Frame Column Width LSB (53h).................................................................................................................42
`Table 36: SOF Control Register (54h) .....................................................................................................................................43
`Table 37: VCLK Control Register (55h)..................................................................................................................................43
`Table 38: Internal Timing Control Register (60h).................................................................................................................... 44
`
`
`
`
`
`
`
`Eastman Kodak Company - Image Sensor Solutions
`
`
`For the most current information regarding this product:
`Web: www.kodak.com/go/imagers Phone: (585) 722-4385 Email: imagers@kodak.com
`
`Revision No. 1
`Page 6 of 56
`
`
`
`Ex.1010 / Page 6 of 56Ex.1010 / Page 6 of 56
`
`TESLA, INC.TESLA, INC.
`
`

`

`
`
`Eastman Kodak Company
`Technical Data
`Kodak Digital Science KAC-0311 Image Sensor
`
` Overview
`
` 1
`
`
`The KAC-0311 is a solid state CMOS Active CMOS Imager (ACITM) that integrates the functionality of complete
`analog image acquisition, digitizer, and digital signal processing system on a single chip. The image sensor com-
`prises a VGA format pixel array with 640x480 active elements. The image size is fully programmable to user
`defined windows of interest. The pixels are on a 7.8µm pitch. High sensitivity and low noise are a characteristic
`of the pinned photodiode2 architecture utilized in the pixels. The sensor is available in a Monochrome version
`without microlenses, or with Bayer (CMY) patterned Color Filter Arrays (CFAs) without microlenses.
`
`Integrated timing and programming controls allow video or still image capture progressive scan modes. Frame
`rates are programmable while keeping the Master Clock frequency constant. User programmable row and column
`start/stop allow windowing down to a 1x1 pixel window for digital zoom of a panable viewport. Subsampling
`provides reduced resolution while maintaining constant field of view.
`
`The analog video output of the pixel array is processed by an on-chip analog signal pipeline. Correlated Double
`Sampling (CDS) eliminates the pixel reset temporal and pattern noise. The Frame Rate Clamp (FRC) enables real
`time optical black level calibration and offset correction. The programmable analog gain consists of expo-
`sure/global gain to map the signal swing to the ADC input range, and white balance gain to perform color balance
`in the analog domain. The ASP signal chain consists of (1) Column op-amp; (2) Column DOVA; (