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`I IIIII IIIIIIII
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`)011,11 11111 111111 IIII
`
`US011061682B2
`
`( 12 ) United States Patent
`(12) United States Patent
`Vorbach
`Vorbach
`
`( 10 ) Patent No .:
`US 11,061,682 B2
`(10) Patent No.: US 11,061,682 B2
`( 45 ) Date of Patent :
`Jul . 13 , 2021
`(45) Date of Patent:
`Jul. 13, 2021
`
`( 54 ) ADVANCED PROCESSOR ARCHITECTURE
`(54) ADVANCED PROCESSOR ARCHITECTURE
`( 71 ) Applicants : Martin Vorbach , Lingenfeld ( DE ) ;
`(71) Applicants:Martin Vorbach, Lingenfeld (DE);
`Hyperion Core , Inc. , Los Gatos , CA
`Hyperion Core, Inc., Los Gatos, CA
`( US )
`(US)
`( 72 ) Inventor : Martin Vorbach , Lingenfeld ( DE )
`Inventor: Martin Vorbach, Lingenfeld (DE)
`(72)
`( * ) Notice :
`Subject to any disclaimer , the term of this
`Notice:
`Subject to any disclaimer, the term of this
`(*)
`patent is extended or adjusted under 35
`patent is extended or adjusted under 35
`U.S.C. 154 ( b ) by 0 days .
`U.S.C. 154(b) by 0 days.
`15 / 535,697
`15/535,697
`Dec. 13 , 2015
`Dec. 13, 2015
`PCT / US2015 / 065418
`PCT/US2015/065418
`
`( 65 )
`(65)
`
`( 21 ) Appl . No .:
`(21)
`Appl. No.:
`( 22 ) PCT Filed :
`(22)
`PCT Filed:
`( 86 ) PCT No .:
`(86)
`PCT No.:
`$ 371 ( c ) ( 1 ) ,
`§ 371 (c)(1),
`( 2 ) Date :
`Jun . 13 , 2017
`Jun. 13, 2017
`(2) Date:
`( 87 ) PCT Pub . No .: WO2016 / 100142
`(87) PCT Pub. No.: WO2016/100142
`PCT Pub . Date : Jun . 23 , 2016
`PCT Pub. Date: Jun. 23, 2016
`Prior Publication Data
`Prior Publication Data
`US 2018/0004530 A1
`Jan. 4 , 2018
`US 2018/0004530 Al
`Jan. 4, 2018
`Foreign Application Priority Data
`( 30 )
`Foreign Application Priority Data
`(30)
`Dec. 15 , 2014
`( EP )
`14197929
` 14197929
`Dec. 15, 2014
`(EP)
`( EP )
`Jun . 24 , 2015
`150201036
` 150201036
`Jun. 24, 2015
`(EP)
`( 51 ) Int . CI .
`(51) Int. Cl.
`GO6F 9/38
`G06F 9/38
`G06F 9/30
`G06F 9/30
`GOOF 9/32
`G06F 9/32
`( 52 ) U.S. CI .
`(52) U.S. Cl.
`CPC
`CPC
`
`( 2018.01 )
`(2018.01)
`( 2018.01 )
`(2018.01)
`( 2018.01 )
`(2018.01)
`
`G06F 9/3855 ( 2013.01 ) ; GO6F 9/3001
`G06F 9/3855 (2013.01); G06F 9/3001
`( 2013.01 ) ; G06F 9/3017 ( 2013.01 ) ;
`(2013.01); G06F 9/3017 (2013.01);
`( Continued )
`(Continued)
`( 58 ) Field of Classification Search
`(58) Field of Classification Search
`CPC
`G06F 9/3855
`G06F 9/3855
`CPC
`See application file for complete search history .
`See application file for complete search history.
`
`srco src1
`src
`
`0211
`
`0211 v
`
`r3
`
`rr3
`rr1 72 rr3
`
`0231
`0231
`
`1
`
`I
`
`02321 1
`0232
`
`r3 src2
`rc2
`
`0212
`0212
`tgtorr1
`tgtO
`
`rr2
`
`rr3
`
`0121 src3
`012
`0213
`0213
`tgt1 rr1 rr2 rr3
`tgtl rr
`
`( 56 )
`(56)
`
`5,699,537 A
`5,699,537 A
`5,923,862 A *
`5,923,862 A *
`
`References Cited
`References Cited
`U.S. PATENT DOCUMENTS
`U.S. PATENT DOCUMENTS
`12/1997 Sharangpani et al .
`12/1997 Sharangpani et al.
`7/1999 Nguyen
`7/1999 Nguyen
`( Continued )
`(Continued)
`FOREIGN PATENT DOCUMENTS
`FOREIGN PATENT DOCUMENTS
`
`G06F 9/28
` G06F 9/28
`712/208
`712/208
`
`EP
`EP
`WO
`WO
`
`9/2014
`14185745.8
`9/2014
`14185745.8
`2002/071249
`9/2002
`9/2002
`2002/071249
`( Continued )
`(Continued)
`
`OTHER PUBLICATIONS
`OTHER PUBLICATIONS
`Cheol - Ho Jeong , Woo - Chan Park , Tack - Don Han , Sang - Woo Kim
`Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Sang-Woo Kim
`and Moon - Key Lee , “ In order issue out - of - order execution floating
`and Moon-Key Lee, "In order issue out-of-order execution floating-
`point coprocessor for CalmRISC32 , ” Proceedings 15th IEEE Sym
`point coprocessor for Ca1mRISC32," Proceedings 15th IEEE Sym-
`posium on Computer Arithmetic . ARITH - 15 2001 , Vail , CO , USA ,
`posium on Computer Arithmetic. ARITH-15 2001, Vail, CO, USA,
`2001 , pp . 195-200 , doi : 10.1109 / ARITH.2001.930119 . *
`2001, pp. 195-200, doi: 10.1109/ARITH.2001.930119.*
`( Continued )
`(Continued)
`Primary Examiner Michael J Metzger
`Primary Examiner — Michael J Metzger
`( 74 ) Attorney , Agent , or Firm IP Spring
`(74) Attorney, Agent, or Firm — IP Spring
`
`( 57 )
`ABSTRACT
`ABSTRACT
`(57)
`The invention relates to a method for processing instructions
`The invention relates to a method for processing instructions
`out - of - order on a processor comprising an arrangement of
`out-of-order on a processor comprising an arrangement of
`execution units . The inventive method comprises looking up
`execution units. The inventive method comprises looking up
`operand sources in a Register Positioning Table and setting
`operand sources in a Register Positioning Table and setting
`operand input references of the instruction to be issued
`operand input references of the instruction to be issued
`accordingly , checking for an Execution Unit ( EXU ) avail
`accordingly, checking for an Execution Unit (EXU) avail-
`able for receiving a new instruction , and issuing the instruc
`able for receiving a new instruction, and issuing the instruc-
`tion to the available Execution Unit and entering a reference
`tion to the available Execution Unit and entering a reference
`of the result register addressed by the instruction to be issued
`of the result register addressed by the instruction to be issued
`to the Execution Unit into the Register Positioning Table
`to the Execution Unit into the Register Positioning Table
`( RPT ) .
`(RPT).
`
`20 Claims , 26 Drawing Sheets
`20 Claims, 26 Drawing Sheets
`
`I0221!
`
`instr r3 , srco , src1 0221
`instr r3, srcO, srcl
`0222
`0222
`1
`instr tgt0 , r3 , src2 0223
`0223
`instr tgtO, r3, src2
`0224
`0224
`instr tgt1 , r3 , src3 0225
`0225
`str tgt1, r3, src3
`0226
`0226
`instr r3 , src4 , src5 0227
`instr r3, src4, src5 10227
`
`0201
`0201
`
`0116
`0116
`T
`
`0131
`0131
`
`WIZ, Inc. EXHIBIT - 1069
`WIZ, Inc. v. Orca Security LTD.
`
`WIZ, Inc. EXHIBIT - 1069
`WIZ, Inc. v. Orca Security LTD.
`
`

`

`US 11,061,682 B2
`Page 2
`
`(52) U.S. Cl.
`CPC
`
`G06F 9/30065 (2013.01); G06F 9/30098
`(2013.01); G06F 9/325 (2013.01); G06F
`9/327 (2013.01); G06F 9/382 (2013.01);
`G06F 9/384 (2013.01); G06F 9/3824
`(2013.01); G06F 9/3826 (2013.01); G06F
`9/3828 (2013.01); G06F 9/3836 (2013.01);
`G06F 9/3842 (2013.01); G06F 9/3844
`(2013.01); G06F 9/3846 (2013.01); G06F
`9/3848 (2013.01); G06F 9/3857 (2013.01);
`G06F 9/3861 (2013.01); G06F 9/3863
`(2013.01); G06F 9/3885 (2013.01)
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`7,096,345 B1 *
`
`8/2006 Chen
`
`7,111,152 B1 * 9/2006 Cofler
`
`2002/0188828 Al * 12/2002 Sugimoto
`
`2007/0055852 Al * 3/2007 Hanes
`
`2013/0205123 Al *
`
`8/2013 Vorbach
`
` G06F 9/3838
`712/217
` G06F 9/3836
`712/216
`G06F 9/30083
`712/215
` G06F 9/3851
`712/228
` G06F 9/30043
`712/221
`
`FOREIGN PATENT DOCUMENTS
`
`WO
`WO
`WO
`WO
`WO
`WO
`WO
`
`2010/142432
`2010/043401
`2011/079942
`2012/003997
`2012/123061
`2012/167933
`2013/098643
`
`2/2010
`4/2010
`7/2011
`1/2012
`9/2012
`12/2012
`7/2013
`
`OTHER PUBLICATIONS
`
`"ARM7TDMI-S Data Sheet", Document No. ARM DDI 0084D,
`ARM Ltd., UK, 1998, 60 pages.
`Balasubramonian, "Lecutre Notes: Out-of-Order Processors", Uni-
`versity of Utah, Oct. 13, 2007, 8 pages.
`
`European Patent Office, International Search Report for Interna-
`tional Patent Application No. PCT/US2015/065418, dated Jul. 7,
`2016, 6 pages.
`European Patent Office, Written Opinion for International Patent
`Application No. PCT/US2015/065418, dated Jul. 7, 2016, 8 pages.
`Fog, "The microarchitecture of Intel, AMD and VIA CPUs: An
`optimization guide for assembly programmers and compiler mak-
`ers", http://www.agner.org/optimize/microarchitecture.pdf, 1996-
`2017, 233 pages.
`Goulding-Hotta, et al., "The GreenDroid Mobile Application Pro-
`cessor: an Architecture for Silicon's Dark Future", University
`California, San Diego; Published by the IEEE Computer Society,
`Mar./Apr. 2011, 10 pages.
`Gunadi, et al., "CRIB: Consolidated Rename, Issue, and Bypass",
`ISCA'11, Jun. 4-8, 2011, San Jose, California, USA, 2011, 10
`pages.
`Rotenberg, et al., "Trace Cache: a Low Latency Approach to High
`Bandwith Instruction Fetching", Proceedings of the 29th annual
`ACM/IEEE international symposium on Microarchitecture. IEEE
`Computer Society, 1996, 12 pages.
`Thomadakis, "The Architecture of the Nehalem Processor and
`Nehalem-EP SMP Platforms", Texas A&M University, Mar. 17,
`2011, 49 pages.
`Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arith-
`metic Units", IBM Journal of Research and Development archive;
`vol. 11, Issue 1, Jan. 1967, pp. 25-33.
`UK Intellectual Property Office, Examination Report for United
`Kingdom Patent Application No. 1711202.0, dated Aug. 20, 2018,
`5 pages.
`UK Intellectual Property Office, Examination Report for United
`Kingdom Patent Application No. 1711202.0, dated Aug. 17, 2017,
`10 pages.
`"Computer Organization and Architecture, Chapter 15. Control Unit
`Operation", umcs.maine.edu, http://aturing.umcs.maine.edu/—meadow/
`courses/cos335/COA15.pdf, Mar. 16, 2010, 9 pages.
`Lazzaro, "CS 152 Computer Architecture and Engineering: Lecture
`6—Superpipelining + Branch Pre-diction", UC Berkeley, https://
`inst.eecs.berkeley.edu/—cs152/sp14/lecnotes/lec3-2.pdf, Feb. 6, 2014,
`37 pages.
`Sima, Derso "Microarchitecture of Superscalars (3): Branch Pre-
`diction", Universitas Budensis , John von Neumann Faculty of
`Informatics, Fall 2007, 73 pages.
`
`* cited by examiner
`
`

`

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`

`

`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 2 of 26
`
`US 11,061,682 B2
`
`c:(
`ttb LL
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`0224
`instr tgtl, r3, src3 10225
`0226
`instr r3, src4, src5 10227
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`0201
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`Fig. 2
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`
`#06: cmp rl, r3
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`#07: movlt r4, rl
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`#08: cmp r3, r2
`
`#09: movlt r4, r2
`
`#10: store r4
`
`#11: load r3
`
`#12: add r3, r3, r2
`0301
`
`#13: store r3
`
`#01: load rl
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`#02: load r2
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`#03: load r3
`r3
`#04: mov r4,
`r2,
`#05: add rl,
`r3
`#06: cmp rl,
`r4 = rl
`#07: mux lt ?
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`#09
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`#10
`
`Fig. 3
`
`

`

`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 5 of 26
`
`US 11,061,682 B2
`
`cr
`ab
`U7
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`Start instruction issue
`
`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 5 of 26
`
`US 11,061,682 B2
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`

`

`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 7 of 26
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`US 11,061,682 B2
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`

`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 9 of 26
`
`US 11,061,682 B2
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`
`to
`0
`CO
`0
`
`N
`O
`00
`0
`
`00
`o
`00
`0
`
`N
`.-I
`00
`0
`
`0
`v-i
`00
`0
`
`*-10.
`
`Cr)
`N
`00
`0
`
`m
`0
`00
`0
`
`A
`
`c-I
`N
`00
`0
`
`d-
`o
`00
`0
`
`r -I
`Cr
`00
`0
`
`L.r)
`0
`00
`0
`
`1
`
`N
`N
`00
`0
`
`

`

`lualud °S11
`
`9Z JO OT WIN
`
`Zll Z89`190`11 Sf1
`
`mov
`MOV
`
`#5
`Ro,
`
`R1, #0
`
`0952
`
`; RO is current number, 5 assumed for start value
`
`; R1 is count of number of iterations
`
`while
`
`SUBS
`
`
`
`R7, R0, #1
`
`; repeat if RO != 1
`
`body
`
`BEQ
`
`ADD
`
`exit
`
`R1, R1, #1
`
`; increment number of iterations
`
`ANDS
`
`R7,
`R0, #1
`
`; test whether RO is odd
`
`BEQ
`
`ADD
`
`ADD
`
`B
`
`even
`
`R0, R0, R0, LSL #1 ; if odd, set RO = RO + (RO « 1) + 1
`
`R0, R0, #1
`
`while
`
`; could jump directly to 'loop': (guaranteed RO > 1)
`
`even
`
`MOV
`
`R0, R0, ASR #1
`
`; if even, set RO = RO >> 1
`
`B
`
`while
`
`exit
`
`; else done
`
`Fig. 9A
`
`MOV
`
`MOV
`
`while
`
`SUBS
`
`body
`
`BEQ
`
`ADD
`
`R1,
`#0
`
`0951
`
`; R1 is count of number of iterations
`
`; R0 is current number, 5 assumed for start value
`
`R0,
`#5
`R7, R0, #1 0931
`; repeat if RO != 1
`0941
`exit
`; increment number of iterations
`
`
`
`R1, R1,
`#1
`
`ANDS
`
`
`
`R7, R0,
`#1
`
`; test whether RO is odd
`
`ADDNE
`
`
`
`R0, R0, R0, LSL #1
`
`
`
`ADDNE
`
`R0,
`
`
`R0, #1
`
`MOVEQ
`
`exit
`
`while
`
`
`
`
`
`R0, R0, ASR #1
`0942
`0932
`
`; if odd, set RO = RO + (RO « 1) + 1
`
`; if even, set RO = RO >> 1
`
`; else done
`
`Fig. 9B
`
`

`

`lualud °S11
`
`9Z JO H Po MS
`
`Zll Z89`190`11 Sf1
`
`MOV
`
`MOV
`
`
`
`R0, #5
`
`R1,
`#0
`
`;
`
`
`
`RO is current number, 5 assumed for start value
`
`;
`
`R1 is count of number of iterations
`
`while
`
`SUBS
`
`R7,
`R0, #1
`
`; repeat if RO != 1
`
`body
`
`BEQ
`
`ADD
`
`ANDS
`
`ADD
`
`ADDNE
`0901 MOVEQ
`B
`
`exit
`
`exit
`
`
`
`R1, R1, #1
`
`
`
`0902
`increment number of iterations
`
`;
`
`R7,
`
`
`R0, #1
`
`;
`
`test whether RO is odd
`
`R2, R0, R0, LSL #1 ; if odd, set RO = RO + (RO << 1) + 1; SPECULATIVE!!
`
`
`
`R0, R2, #1
`
`
`
`
`
`R0, R0, ASR #1
`
`
`
`while
`
`; if even, set RO = RO >> 1
`0903
`
`; else done
`
`Fig. 9C
`
`MOV
`
`MOV
`
`R0, #5
`
`R1, #0
`
`; RO is current number, 5 assumed for start value
`
`; R1 is count of number of iterations
`
`while
`
`SUBS
`
`R7, R0, #1
`
`; repeat if RO != 1
`
`body
`
`0921
`
`exit
`
`BEQ
`
`ADD
`
`ADD
`
`IF
`
`exit
`
`R1, R1,
`#1
`
`increment number of iterations
`
`
`
`R2, R0, R0, LSL #1
`
`if odd, set RO = RO + (RO « 1) +
`
`SPECULATIVE!!
`
`#2, R0 & #1
`
`ADD.T
`
`R0, R2, #1
`
`MOV.F
`
`R0, R0, ASR #1
`
`if even, set RO = RO >> 1
`
`B
`
`while
`
`else done
`
`Fig. 9D
`
`

`

`lualud °S11
`
`9Z JO Z1 WIN
`
`Zll Z89`190`11 Sf1
`
`1004
`
`1001
`
`1005
`
`r0, r1
`V
`
`1002
`
`PP 1003
`
`ADD
`ANDS
`
`R1, R1, #1
`
`R7, R0, #1
`
`ADDNE R0, R0, R0, LSL #1
`
`ADDNE R0, R2, #1
`
`MOVEQ R0, R0, ASR #1
`
`SUBS R7, R0, #1
`BEQ
`
`exit
`while
`
`B
`
`PP
`
`0, rl, €q
`
`r7
`
`PP
`
`Fig. 10
`
`

`

`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 13 of 26
`
`US 11,061,682 B2
`
`i loop:
`
`k_loop:
`
`mov r0, #0
`mov rl, #0
`
`k
`
`mul r3, r10, r0
`add r3, r3, r1
`ldr r3, [r7, r3]; matrix C
`
`mov r2, #0
`
`j loop:
`
`mul r4, r10, r0
`add r4, r4, r2
`ldr r4, [r8, r4]; matrix A
`
`mul r5, r12, r2
`add r5, r5, r1
`ldr r5, [r9, r5]; matrix B
`
`mul r4, r4, r5
`add r3, r3, r4
`
`add r2, r2, #1
`cmp r2, r12
`bne j_loop
`
`mul r4, r10, r0
`add r4, r4, rl
`str r3, [r7, r4]
`
`end jm loop
`
`add r1, r1, #1 ; end k loop
`
`
`cmp rl, rll
`bne k_loop
`
`add r0, r0 #1 ; end i loop
`
`
`cmp r0, r10
`bne i loop
`
`exit:
`
`1101
`
`1102
`
`1103
`
`1121
`
`1111
`
`1104
`
`1112
`
`1113
`
`Fig. 11
`
`

`

`lualud °S11
`
`9Z JO VI WIN
`
`Zll Z89`190`11 Sf1
`
`211
`
`valid flag
`(v=valid,
`iv=invalid)
`
`1201
`
`1203
`
`v
`v
`
`1204
`1205
`
`1202
`
`Fig. 12A
`
`instruction
`
`1217
`A
`
`1218
`
`1220
`
`1219D' 1212
`
`215
`216
`
`1213 1214
`
`Fig. 12B
`
`1201
`
`1203
`
`v
`v
`
`1204
`1205
`
`1202
`
`

`

`lualud °S11
`
`9Z JO ST WIN
`
`Zll Z89`190`11 Sf1
`
`0
`I—‘
`
`
`
`N
`Lk)
`
`-P.
`
`add
`instro
`
`inStr2
`
`cmp
`add
`instro
`
`bne
`
`cmp
`add
`
`instro
`for
`cmp
`
`instr+2
`instro
`for
`
`v
`v
`
`v
`v
`
`iv
`iv
`
`v
`
`v
`
`
`
`I-4
`(,K)
`
`
`-P.
`
`I-4
`w
`1--1
`Ul
`
`add
`mul
`instri
`
`Idr
`add
`mul
`
`instr*i
`fldr
`add
`
`instr+2
`instro
`fldr
`
`b
`instri
`i n St L2
`
`subs
`b
`instro
`
`beq
`subs
`b
`
`instr.1
`while
`subs
`
`instr+2
`instr+1
`while
`
`v
`v
`
`v
`v
`
`iv
`iv
`
`v
`
`v
`v
`
`instr+3
`v
`instr+2
`v
`instr+1
`Fig. 13A
`
`I-1
`w
`cn
`cn
`
`instr+3
`v
`instr+2
`v
`instr+1
`Fig. 136
`
`I-4 a)
`
`instr+3
`v
`i nstr+2
`v
`instr+1
`Fig. 13C
`
`!..-.. 1201
`(„3 1204
`rt 1205
`
`"j* 1201
`m 1204
`7I-P 1205 ----
`I---
`r -
`j . 1201
`rD 1204 ------
`Z-. 1205 ------ -
`
`v
`v
`
`iv
`iv
`
`j . 12 01.---..---..-....
`m 1204
`v
`Z 1205
`iv
`
`v
`v
`
`r-t.
`3 1201-- -
`rm., 1204 -
`'4 1205 ----- -
`r-t•
`j . 1201
`m 1204
`F., 1205
`
`------------ ---
`

`

`lualud °S11
`
`9Z JO 91J I
`
`Zll Z89`190`11 Sf1
`
`1211
`,--t
`j' 1201
`fp 1204
`ri. 1205
`
`at. 1211--
`W 1201
`7 1204
`I-1 1205
`
`at. 1211
`(Do 1201
`7 1204
`NJ 1205
`
`V
`
`V
`v
`
`IV
`
`— 1211 -------
`W) 1201
`7 1204
`w 1205
`
`iv
`iv
`
`ct. 1211
`W) 1201
`r+1. 1204
`1205 --------- --
`
`IV
`
`add
`instri
`instr2
`
`cmp
`add
`instri
`
`bne
`cmp
`add
`
`mov
`bne
`cmp
`
`I—I
`I-1
`
`
`
`1-1,
`w
`
`c,,1!)
`
`mov
`
`instr*1
`for
`cmp
`Fig. 13D
`
`v
`
`
`
`v
`
`b
`instri
`instr2
`
`invalid(nop)
`b
`instri
`
`subs
`b
`instri
`
`beq
`subs
`b
`
`mov
`
`mov
`
`mov
`
`instr+i
`while
`subs
`Fig. 13E
`
`I-4
`UJ
`NJ
`F-1
`
`I--1
`U..)
`
`NJ
`
`I--1
`UJ
`-Ph
`U.)
`
`N
`U..)
`4=.
`
`I--1
`U.)
`N.)
`
`

`

`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 17 of 26
`
`US 11,061,682 B2
`
`loop:
`
`k loop:
`
`j loop:
`
`mov
`mov
`
`fldr
`mov
`
`fldr
`fldr
`
`mul
`add
`
`r0,
`r
`
`#0
`#0
`
`i
`;
`; k
`
`r3, [r3,
`r2,
`#0
`
`(r10*T0)+r1) ] 1401
`;
`j
`
`[r8,
`r4,
`r5, [r8,
`
`(r10*r0)+T2)] 1402
`(r12*r2)+r1) ] 1403
`
`r4,
`r3,
`
`r4, r5
`r3, r4
`
`endfor
`
`(r2,
`
`+#1, r12,
`
`j loop) 1411
`
`fstr
`
`r3, [r7,
`
`r10*T0)+r1)] 1404
`
`endfor
`endfor
`
`(r1, +#1, rll, k_loop) 1412
`loop) 1413
`(r0, +#l, r10, i
`
`exit:
`
`loop:
`
`(nop)
`(nop)
`
`; mov
`; mov
`
`r0, #0
`rl, #0
`
`k_loop: fldr
`(nop)
`
`r3, [r3, r10*r0) +r1) ]
`r2, #0
`; mov
`
`j loop:
`
`fldr
`fldr
`
`mul
`add
`
`r4, [r8,
`r5, [r8,
`
`(r10*r0)+T2)]
`(r12*r2)+r1) ]
`
`r4, r4, 1.5 1431
`r3, r3, r4
`
`1431
`1432
`
`1401
`1433
`
`1402
`1403
`
`endfor
`
`(r2, +#1, r12, j_loop, #0) 1421
`
`fstr
`
`r3, [r7,
`
`(r10*r0)+r1)]
`
`1404
`
`endfor
`endfor
`
`k loop, #0) 1422
`-i-ffl, rll,
`(rl,
`loop, #0) 1423
`(r0, +#1, r10, i
`
`exit:
`
`Fig. 14A
`
`Fig. 14B
`
`

`

`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 18 of 26
`
`US 11,061,682 B2
`
`I loop: for
`
`(r0, +#1, r10, #0)
`
`k loop: for
`fldr
`
`(rl, +#1, rll, #0)
`r3, [r3, (r10*r0)+ri)]
`
`loop: for
`fldr
`fldr
`
`(r2, +#1, r12, #0)
`r4, [r8, (r10*r0)+r2)]
`r5, [r8, (r12*r2)+rl)]
`
`mul
`add
`
`r4, r4, r5
`r3, r3, r4
`
`endfor
`
`fstr
`
`r3, [r7, r10*r0)+r1)]
`
`Fig. 14C
`
`endfor
`endfor
`
`exit:
`
`

`

`U.S. Patent
`
`Jul. 13, 2021
`
`Sheet 19 of 26
`
`US 11,061,682 B2
`
`1215/1216
`
`1501
`1212
`
`1513
`
`1512
`
`H 1511
`
`1510
`
`1509
`
`1508
`
`1507
`
`-0. 1521
`
`0
`is)
`
`CU
`
`Dispatch States
`
`co
`Ln
`ri
`
`Lc)
`0
`
`Lo
`
`r -I
`
`V
`Ln
`0
`N
`
`%-1
`
`N
`r -I
`
`m
`0
`N
`
`N
`
`m
`0 Ls)
`
`r -I
`
`1219/..
`1220
`
`r, co
`Ul CA
`ri
`
`0
`
`r-I
`
`N 0
`ri
`
`0
`N
`
`

`

`lualud °S11
`
`9Z JO OZ WIN
`
`Zll Z89`190`11 Sf1
`
`Fig. 16A
`
`time t
`
`time t + I +1
`
`time t + I + 2
`
`i
`
`+ u..)
`
`fldr: 1402, 1403 1601
`71y
`I clock cycles latency
`
`mul/add: 1431 1602
`fstr: 1404
`
`1603
`
`endfor: 1421, 1422, 1423
`
`Fig. 166
`
`time t
`
`fldr: 1402, 1403 1601 endfor: 1421, 1422, 1423 (1) 1611
`1613 + I clock cycles latency
`
`time t + I
`
`time t + I + 1
`
`N'EC
`
`mul/add: 1431 1602 endfor: 1421, 1422, 1423 (2)
`fstr: 1404
`
`1603
`
`1612
`
`

`

`lualud °S11
`
`9Z JO 1Z WIN
`
`Zll Z89`190`11 Sf1
`
`Fig. 16C
`
`time t
`
`time t + I
`
`fldr: 1402, 1403 1601 endfor: 1421, 1422, 1423 (1)
`1613+
`I clock cycles latency
`
`mul/add: 1431
`I
`16211
`
`1602
`
`endfor: 1421, 1422, 1423 (2)
`I 1623
`1622
`
`1611
`
`1612
`
`time t + I + 1
`
`fstr: 1404
`
`1603
`
`Fig. 16D
`
`time t
`
`fldr: 1402, 1403 1601 endfor: 1421, 1422, 1423 (1)
`
`1631
`
`1613 I I clock cycles latency
`
`1632
`
`time t + I
`
`time t + I + 1
`
`mul/add: 1431 1602
`I
`1621t
`
`fstr: 1404
`
`1603
`
`1623
`
`

`

`lualud °S11
`
`9Z JO ZZ WIN
`
`Zll Z89`190`11 Sf1
`
`fldr
`fldr
`fldr
`
`r3, [r3,
`r4, [r8,
`r5, [r8,
`
`(T10*r0)+r1)]
`(r10*r0)+r2) ]
`(r12*r2)+rl) ]
`
`1706
`
`170
`
`mul
`add
`
`r4, r4,
`r3, r3,
`
`r5
`r4
`
`1704,
`
`1702
`
`17100
`
`1709
`
`1712
`
`171
`fstr r3, [r7, (r10*r0)+r1)]
`
`Fig. 17A
`
`i_loop:
`k_loop:
`j
`loop:
`1703
`
`l_loop:
`k_loop:
`j
`loop:
`1708
`
`for
`for
`for
`
`(r0, +#1, r10, i_loop, #0)
`(rl, +#1, rll,
`k loop, #0)
`(r2, +#1, r12, j
`loop, #0)
`
`for
`for
`for
`
`(r0, +#1, r10, i_loop, #0)
`(rl, +#1, rll, k_loop, #0)
`(r2, +#1, r12, j
`loop, #0)
`
`1704,
`
`'I
`1702
`
`i_loop:
`k_loop:
`j
`loop:
`1703
`
`Fig. 17B
`
`for
`for
`for
`
`(r0, +#1, r10, i_loop, #0)
`(rl, +#1, rll, k_loop, #0)
`(r2, +#1, r12, j
`loop, #0)
`
`fldr
`fldr
`fldr
`
`r3, [r3,
`r4, [r8,
`r5, [r8,
`
`(r10*r0)+r1) ]
`(r10*r0)+r2)]
`(r12*r2)+rl) ]
`
`1706
`
`170
`
`mul
`add
`
`r4, r4, r5
`r3, r3, r4
`
`1712
`
`171
`fstr r3, [r7, (r10*r0)+r1)]
`
`1701
`
`1707
`
`1711
`
`1701
`
`1707
`
`1711
`
`

`

`lualud °S11
`
`9Z JO £Z WIN
`
`Zll Z89`190`11 Sf1
`
`stp
`
`<trg(0)
`<idx(0)
`
`<trg(1)
`<idx(1)
`
`Fig. 18
`
`<trg(2)
`<idx(2)
`exit
`
`•••.,
`
`1823 1823
`
`
`
`18 06(1) 6 ( 1 )
`
`1802(0)
`1803(0)
`
`>
`cnt
`w- 18 0 1 ( 0 )
`clr
`
`18 0 4 ( 0) All-
`
`-
`
`1805(0) I
`
`.
`
`1802(1,`
`1803(1:
`
`18 02(2) 2 (2)
`
`1803(2)
`
`ext(0)
`
`18 0 6 ( 2)
`
`>
`cnt
`
`1801(1)
`
`I v- 1804(1)
`
`.44--
`
`1805(1) I
`
`clr
`
`>
`cnt
`
`1801(2)
`
`clr
`
`1822
`
`ext(1)
`
`18 0 6 ( 3)
`
`H1804(2)
`
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`

`US 11,061,682 B2
`
`1
`ADVANCED PROCESSOR ARCHITECTURE
`
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`
`The present application is a U.S. national phase applica-
`tion of International Patent Application No. PCT/US2015/
`065418, filed Dec. 13, 2015, which claims priority to
`European Patent Application No. 14197929.4, filed Dec. 15,
`2014, and European Patent Application No. 15020103.6,
`filed Jun. 24, 2015, the contents of all of which are incor-
`porated herein by reference in their entirety.
`The present application also claims priority to the follow-
`ing applications, all incorporated by reference in their
`entirety:
`PCT/EP2009/007415, filed Oct. 15, 2009;
`PCT/EP2010/003459, filed Jun. 9, 2010;
`PCT/EP2010/007950, filed Dec. 28, 2010;
`PCT/EP2011/003428, filed Jul. 8, 2011;
`PCT/EP2012/000713, filed Feb. 17, 2012;
`PCT/EP2012/002419, filed Jun. 6, 2012;
`PCT/IB2012/002997, filed Dec. 17, 2012; and
`EP 14 18 5745.8, filed Sep. 22, 2014.
`
`BACKGROUND AND FIELD OF INVENTION
`
`The present invention relates to data processing in general
`and to data processing architecture in particular.
`Energy efficient, high speed data processing is desirable
`for any processing device. This holds for all devices wherein
`data are processed such as cell phones, cameras, hand held
`computers, laptops, workstations, servers and so forth offer-
`ing different processing performance based on accordingly
`adapted architectures.
`Often similar applications need to be executed on differ-
`ent devices and/or processor platforms. Since coding soft-
`ware is expensive, it is be desirable to have software code
`which can be compiled without major changes for a large
`number of different platforms offering different processing
`performance.
`It would be desirable to provide a data processing archi-
`tecture that can be easily adapted to different processing
`performance requirements while necessitating only minor
`adoptions to coded software.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a diagrammatic illustration of an example
`EXU-Block comprising multiple EXUs;
`FIG. lA is a diagrammatic illustration of an example
`execution unit;
`FIG. 2 is a block diagram of an example system illustrat-
`ing a fundamental operating mode for one or more described
`features;
`FIG. 3 is a diagrammatic illustration of example graphs
`for registers and example code using the graphs;
`FIG. 4 is a diagrammatic illustration of an example
`algorithm implementing an out-of-order processing mode;
`FIG. 5 is a diagrammatic illustration of an example
`implementation using a Register Positioning Table;
`FIG. SA is a diagrammatic illustration of an example
`Register Positioning Table which can be used in the imple-
`mentation of FIG. 5;
`FIG. 6 is a diagrammatic illustration of an example
`implementation of an enhanced Register Positioning Table
`(RPT);
`
`5
`
`10
`
`15
`
`2
`FIG. 7 is a diagrammatic illustration of an example
`implementation using a described Issue Unit;
`FIG. 7A is a diagrammatic illustration of an example
`Trash Unit for an associated Register Positioning Table;
`FIG. 7B is a diagrammatic illustration of an example
`Sample-and-Hold Unit comprising a dedicated Sample-and-
`Hold Stage for each one of the Execution Units;
`FIG. 8 is a diagrammatic illustration of an example
`Control Unit;
`FIG. 8A is a diagrammatic illustration of example level
`outputs of decoders of the Control Unit of FIG. 8;
`FIGS. 9A-9D are diagrammatic illustrations of examples
`of assembly programs and pseudo code including interrupt
`processing;
`FIG. 10 is a diagrammatic illustration of an example
`implementation using a loop acceleration method;
`FIG. 11 is a diagrammatic illustration of example code
`implementing an example matrix multiplication for an Ana-
`lyzer and Optimizer Unit (AOU);
`FIGS. 12A and 12B are diagrammatic illustrations of
`different example AOUs;
`FIGS. 13A-13E are diagrammatic illustrations of different
`example instruction patterns operated on by an AOU;
`FIGS. 14A-14C are diagrammatic illustrations of example
`25 instructions and/or microcode generated by an AOU;
`FIG. 15 is a diagrammatic illustration of an example
`integration of described features into a standard processor;
`FIGS. 16A-16D are diagrammatic
`illustrations of
`example execution sequences;
`FIGS. 17A and 17B are diagrammatic illustrations of
`synchronization models for FIGS. 16C and 16D based on the
`exemplary code of FIG. 14C;
`FIG. 18 is a diagrammatic illustration of an example
`implementation of an index computation part of a Loop
`35 Control Unit;
`FIG. 18A is a diagrammatic illustration of an example
`implementation providing computation of a Program Pointer
`(PP) while a Loop Control Unit is active;
`FIG. 19 is a diagrammatic illustration of an example
`40 load/store unit; and
`FIG. 20 is a diagrammatic illustration of an example
`implementation of a shared bus.
`
`20
`
`30
`
`45
`
`DETAILED DESCRIPTION OF THE
`INVENTION
`
`55
`
`This patent describes a novel, optimized method and
`architecture overcoming the above limitations.
`This patent focuses on implementations of out-of-order
`so processing modes on ZZYX processors.
`It is an object of the present invention to provide an
`improvement over the prior art of processing architectures
`with respect to at least one of data processing efficiency,
`power consumption and reuse of the software codes.
`The present invention describes a new processor archi-
`tecture called ZZYX thereafter, overcoming the limitations
`of both, sequential processors and dataflow architectures,
`such as reconfigurable computing.
`It shall be noted that whereas hereinafter, frequently terms
`60 such as "each" or "every" and the like are used when certain
`preferred properties of elements of the architecture and so
`forth are described. This is done so in view of the fact that
`generally, it will be highly preferred to have certain advan-
`tageous properties for each and every element of a group of
`65 similar elements. It will be obvious to the average skilled
`person however, that some if not all of the advantages of the
`present invention disclosed hereinafter might be obtainable,
`
`

`

`3
`even if only to a lesser degree, if only some but not all
`similar elements of a group do have a particular property.
`Thus, the use of certain words such as "each", "any" "every"
`and so forth. is intended to disclose the preferred mode of
`invention and whereas it is considered feasible to limit any
`claim to only such preferred embodiments, it will be obvious
`that such limitations are not meant to restrict the scope of the
`disclosure to only the embodiments preferred.
`Subsequently Trace-Caches are used. Depending on their
`implementation, they either hold undecoded instructions or
`decoded instructions. Decoded instructions might be micro-
`code according to the state of the art. Hereinafter the content
`of Trace-Caches is simply referred as instruction or opcodes.
`It shall be pointed out, that depending on the implementation
`of the Trace-Cache and/or the Instruction Decode (ID) stage,
`actually microcode might reside in the Trace-Cache. It will
`be obvious for one skilled in the art that this is solely
`implementation dependent; it is understood that "instruc-
`tions" or "opcodes" in conjunction with Trace-Cache is
`understood as "instructions, opcodes and/or microcodes
`(depending on the embodiment)".
`It shall also be noted that notwithstanding the fact that a
`completely new architecture is disclosed hereinafter, several
`aspects of the disclosure are considered inventive per se,
`even in cases where other advantageous aspects described
`hereinafter are not realized.
`The technology described in this patent is particularly
`applicable on
`ZYXX processors as described in PCT/EP 2009/007415
`and PCT/EP 2011/003428 and PCT/EP 2012/000713
`and DE 11 007 370.7;
`their memory architectures as described in PCT/EP 2010/
`003459, which are also applicable on multi-core pro-
`cessors are known in the state of the art (e.g. from Intel,
`AMD, MIPS, IBM and ARM); and
`exemplary methods for operating ZYXX processors and
`the like as described in ZZYX09 (DE 10 013 932.8),
`PCT/EP 2010/007950.
`Particularly reference is made to following related patent
`applications: Priority is claimed to the patent applications
`[1], [2], [3], [4], [5], [6], [7], and [8].
`The patents listed above are fully incorporated by refer-
`ence for detailed disclosure.
`The ZZYX processor comprises multiple ALU-Blocks in
`an array with pipeline stages between each row of ALU-
`Blocks. Each ALU-Block may comprise further internal
`pipeline stages. In contrast to reconfigurable processors data
`flows preferably in one direction only, in the following
`exemplary embodiments from top to bottom. Each ALU
`may execute a different instruction on a different set of data,
`whereas the structure may be understood as a MIMD
`(Multiple Instruction, Multiple Data) machine.
`It shall be explicitly noted, that the term ALU or ALU-
`Block is not limiting to the functionality of Arithmetic-
`Logic-Units. It should rather be understood as EXU or
`EXU-Block, where EXU stands for Execution Unit. Thus an
`"ALU" within an ALU-Block might support arithmetic-
`logic functions, but not necessarily has to. An "ALU" as
`used in this specification might be for example a floating
`point unit, a