(12) United States Patent
`AOn0
`
`USOO6351798B1
`(10) Patent No.:
`US 6,351,798 B1
`(45) Date of Patent:
`Feb. 26, 2002
`
`(54) ADDRESS RESOLUTION UNIT AND
`ADDRESS RESOLUTION METHOD FOR A
`MULTIPROCESSOR SYSTEM
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`
`(75) Inventor: Fumio Aono, Tokyo (JP)
`(73) Assignee: NEC Corporation, Tokyo (JP)
`(*) Notice:
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/333,051
`(22) Filed:
`Jun. 15, 1999
`Foreign Application Priority Data
`(30)
`Jun. 15, 1998
`(JP) ........................................... 10-166723
`
`(51) Int. Cl." ....................... G06F 15/16; G06F 15/173;
`G06F 12/10
`
`(52) U.S. Cl. ............................. 712/11; 712/14; 712/17;
`712/18; 712/30; 712/244; 711/210; 711/206;
`709/248; 709/249
`
`(58) Field of Search .............................. 709/251.7, 252,
`709/314, 313, 215, 219, 230, 213, 249,
`238, 216; 711/145, 144, 214, 163, 221,
`216, 210, 206; 714/12, 27; 712/10, 12,
`13, 14, 15, 16, 17, 23, 28, 29, 36, 11, 20,
`18, 30, 31; 710/40, 39, 129, 200, 240, 220,
`244, 23
`
`4,694,396 A * 9/1987 Weisshaar et al. .......... 709/313
`5,574,849 A 11/1996 Sonnier et al. ............... 714/12
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`
`62-67665
`3/1987
`3-132845
`6/1991
`9-146903
`6/1997
`9-179771
`7/1997
`OTHER PUBLICATIONS
`Japanese Office Action dated Oct. 31, 2000 with partial
`translation.
`* cited by examiner
`Primary Examiner Daniel H. Pan
`(74) Attorney, Agent, or Firm McGinn & Gibb, PLLC
`(57)
`ABSTRACT
`The present invention provides an address resolution method
`for use in a multiprocessor System with distributed shared
`memory. The method allows users to change a memory
`configuration and a System configuration to increase System
`operation flexibility and to isolate errors. A cell controller
`indexes into an address resolution table using the high-order
`part of a processor-specified address. A write protection flag
`Specifies whether to permit write access from other cells. An
`attempt to write-access a cell inhibited for write access
`causes a logical circuit to output an acceSS exception signal.
`9 Claims, 11 Drawing Sheets
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`200,500
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`ADDRESS
`RESOLUTION TABLE
`
`CELL MODULE NUMBER
`VIS IME CELL
`
`112
`
`
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`120
`
`ADDRESS WITHIN CELL
`191
`
`

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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 1 of 11
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`US 6,351,798 B1
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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 2 of 11
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`US 6,351,798 B1
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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 3 of 11
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`US 6,351,798 B1
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`START
`
`RETRIEVE ADDRESS
`RESOLUTION TABLE - S301
`S3O2
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`S303
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`VALID
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`MODULE IN CELL
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`PROTECTED 2
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`ACCESS
`EXCEPTION
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`

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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 4 of 11
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`US 6,351,798 B1
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`
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`

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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 5 of 11
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`US 6,351,798 B1
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`

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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 6 of 11
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`US 6,351,798 B1
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`Feb. 26, 2002
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`Sheet 7 of 11
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`US 6,351,798 B1
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`

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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 8 of 11
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`US 6,351,798 B1
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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 9 of 11
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`US 6,351,798 B1
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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 10 of 11
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`US 6,351,798 B1
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`

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`U.S. Patent
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`Feb. 26, 2002
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`Sheet 11 of 11
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`US 6,351,798 B1
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`

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`US 6,351,798 B1
`
`1
`ADDRESS RESOLUTION UNIT AND
`ADDRESS RESOLUTION METHOD FOR A
`MULTIPROCESSOR SYSTEM
`
`BACKGROUND OF THE INVENTION
`The present invention relates to a multiprocessor System
`and address resolution method therefor, and more particu
`larly to a multiprocessor System featuring the distributed
`shared memory architecture and to address resolution
`method therefor.
`Compared with a System where all memory is provided in
`one location, a System featuring the distributed shared
`architecture which distributes memory among multiple pro
`ceSSors gives the user fast access to local memory. However,
`when multiple memories located at different locations are
`organized into one memory Space in the distributed shared
`memory configuration, it is necessary to check whether a
`requested access is to a local memory or to a remote memory
`and, when the acceSS request is to a remote memory, it must
`be transferred to the requested remote memory. This requires
`Some means for resolving addresses (e.g., an address trans
`lation table).
`A System with a typical distributed Shared memory con
`figuration usually has a plurality of configuration units
`(hereinafter called “cells'), each having computer's main
`components Such as processors and memories, intercon
`nected with each other to form a large System. In this case,
`it is relatively easy to Separate each cell and run it as an
`independent computer. This Separation is called
`"partitioning, and a separated cell is called “a partition' or
`“domain'. This configuration gives an advantage over a
`centralized memory System in that a large System can be
`built easily.
`On the other hand, in a large Symmetric multiprocessor
`computer in which multiple processors share memory, there
`are Software constraints and resource competitions that
`make it difficult to increase performance in proportion to the
`number of processors (Scalability). There is also a physical
`limitation on the number of processors that can be added. To
`cope with these problems, multiple computers are Some
`times interconnected to build a System which provides large
`processing power. A System like this is called "a cluster
`System', and the independent computers constituting the
`cluster system are called “nodes'. The cluster system allows
`the user to build a System of any size and, in addition,
`ensures availability. That is, in many cases, the cluster
`System having multiple computers, each operating
`independently, prevents an error or a crash generated in one
`location of the system from affecting the whole system. For
`this reason, the cluster System is Sometimes used to build a
`System which requires high reliability.
`The problems with the cluster system described above is
`that the Setup and the management of the System is more
`complex than a single computer of the Same size and that the
`cabinets and cables require additional costs. To Solve these
`problems, an “in-box” cluster System is on the market today.
`In this System, multiple already-interconnected Small com
`puters are installed in one cabinet and the Setup and test are
`made before shipping. However, conventional cluster
`Systems, including the “in-box” cluster System, use a net
`work for computer interconnection. This results in a large
`communication overhead, Sometimes preventing perfor
`mance from increasing as more nodes are added.
`On the other hand, added processors do not always
`increase the performance of a large Single computer depend
`ing upon the processing it performs. In addition, an error or
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`a failure, once caused in a large Single computer, Sometimes
`affects the whole system.
`SUMMARY OF THE INVENTION
`The present invention Seeks to Solve the problems asso
`ciated with the prior art described above. It is an object of
`the present invention to provide a computer System, featur
`ing the distributed Shared memory architecture, which Selec
`tively acts as a single Symmetric multiprocessor computer
`System or as an “in-box' cluster System. The computer with
`this configuration Solves the problems with, and takes
`advantage of, the Symmetric computer System and the “in
`box' cluster System depending upon processing to be per
`formed.
`According to one aspect of the present invention, there is
`provided a multiprocessor System having a plurality of cells
`each including at least one processor and at least one
`memory, wherein the multiprocessor System determines a
`cell including the memory indicated by a specified address
`and inhibits a write request if destination of the request is
`Some other cell.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`An embodiment of the present invention can be better
`understood with reference to the text and to the following
`drawings, as follows:
`FIG. 1 is a block diagram Showing the configuration of a
`multiprocessor System used in an embodiment of the present
`invention;
`FIG. 2 is a diagram showing the configuration of a cell
`controller used in the embodiment of the present invention;
`FIG. 3 is a flowchart showing the operation of the
`embodiment of the present invention;
`FIG. 4 is a diagram Showing an example of the address
`resolution table used to implement the first example of
`memory configuration according to the present invention;
`FIG. 5 is a diagram showing the memory map of the first
`example of memory configuration according to the present
`invention;
`FIG. 6 is a diagram Showing an example of the address
`resolution table used to implement the Second example of
`memory configuration according to the present invention;
`FIG. 7 is a diagram showing the memory map of the
`Second example of memory configuration according to the
`present invention;
`FIG. 8 is a diagram Showing an example of the address
`resolution table used to implement the third example of
`memory configuration according to the present invention;
`FIG. 9 is a diagram showing the memory map of the third
`example of memory configuration according to the present
`invention;
`FIG. 10 is a diagram showing an example of the address
`resolution table used to implement the fourth example of
`memory configuration according to the present invention;
`and
`FIG. 11 is a diagram showing the memory map of the
`fourth example of memory configuration according to the
`present invention.
`DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`An embodiment of the present invention will be described
`in detail by referring to the attached drawings.
`Referring to FIG. 1, the embodiment of a multiprocessor
`System according to the present invention comprises a
`
`

`

`3
`plurality of cells 400 interconnected by a network 500. In the
`following description, assume that the System has four cells
`400 each with four processor 200, four memories 300, and
`one cell controller 100. These may be set up according to the
`System requirements.
`The memories 300 are distributed among the cells 400.
`From each processor 200, the distance to a memory in its
`own cell differs from the distance to a memory in Some other
`cell. The time to access a memory in its own cell also differs
`the time to access a memory in Some other cell. From the
`physical aspect, this configuration is “a distributed shared
`memory architecture', from the time aspect, it is called “an
`non-uniform memory access (NUMA) architecture”. On the
`other hand, even in the distributed shared memory
`configuration, all memories may be logically combined into
`one large Space for processing by Software. In this case, from
`a Software point of View, the memories are allocated as if
`they were equal in distance to all processors. That is, the
`System may be configured So that any processor views the
`System the same way. In this Sense, a System with this
`topology is thought of as one aspect of a Symmetric multi
`processing computer.
`A data processing System with this configuration allows
`the user to use the System as one Symmetric multiprocessor
`computer and, with Some additional units, as a plurality of
`Small computers.
`Referring to FIG. 2, the cell controller 100 in each cell
`comprises an address register 110, an address resolution
`table 120, a write protection flag 130, a cell number register
`141, an access type register 142, a comparator 150, and a
`logical AND circuit 160.
`The address resolution table 120 is initialized at system
`startup time. The memories 300 distributed among the cells
`are configured as one non-overlapping memory space
`through the address resolution table 120. When the proces
`Sor 200 requests a memory address, the cell controller 100
`indexes the address resolution table 120 for the physical cell
`to be accessed. The address resolution table 120, composed
`of a plurality of entries, is indexed by a module address 111
`of the address sent from the processor 200 or the network
`500 and stored in the address register 110. Each entry of the
`address resolution table 120 comprises a validity bit 121, a
`cell number 122, and a module number within the cell 123.
`The validity bit 121 indicates whether or not the entry is
`valid. For example, the value of “0” indicates that the entry
`is not valid, and the value of “1” indicates that the entry is
`valid. The cell number 122 indicates the number of the cell
`in which the memory module corresponding to the address
`is included. The cell number may be a number physically
`assigned within the System or a number logically assigned
`with the cell as the relative address of “0”. Therefore, “the
`Same cell numbers' mean that the cells are Substantially the
`Same, not in expression. The module number within the cell
`123 indicates the number of the module of the memory 300
`within the cell corresponding to the address. The module
`number within the cell 123 and an address offset within the
`module 112 are combined into an address within the cell
`191.
`The write protection flag 130 indicates whether or not a
`write request from other cells is permitted. For example, the
`value of “0” permits a write from other cells; the value of “1”
`inhibits a write from other cells and generates an acceSS
`exception.
`The cell number register 141 contains the number of the
`cell in which the processor 200 Sending an access request is
`included. The acceSS type register 142 contains a value
`indicating the type of the access request. For example, the
`value of “1” indicates write access. The comparator 150
`compares the contents of the cell number register 141 with
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`the cell number 122 read from the address resolution table
`120. The logical AND circuit 160 generates an access
`exception generation signal 161 when the validity bit 121 of
`the address resolution table 120 indicates that the entry is
`“valid', when the access type is “write”, when the write
`protection flag 130 indicates that a write is “inhibited”, and
`when the cell number 122 read from the address resolution
`table 120 does “not match' the value in the cell number
`register 141. This signal 161 ensures node independence in
`the cluster configuration and prevents error propagation.
`Next, the operation of the embodiment according to the
`present invention will be described with reference to the
`drawings.
`Referring to FIGS. 1 to 3, when the processor 200 issues
`a memory access request, the cell controller 100 indexes the
`address resolution table 120 using the module address 111
`(step S301). If the validity bit 121 indicates that the entry is
`“invalid” (step S302), the circuit generates an address fault
`assuming that the acceSS request was issued to a non
`existing address. If the memory address is found an address
`in some other cell (step S303), the circuit accesses that cell
`via the network 500. If the memory address is in its own cell,
`the circuit accesses the corresponding module in the cell
`(step S304). If an access request is received from some other
`cell and if it is not a “write” request (step S311), the circuit
`accesses the corresponding memory module in the same way
`the circuit accesses the memory module in response to an
`access request generated within its own cell (step S304). On
`the other hand, if an access request received from Some other
`cell is a “write' request, the circuit checks the write protec
`tion flag 130 (step S312). If the rite protection flag 130
`indicates that a write from some other cell is “permitted”, the
`circuit accesses the corresponding module (step S304); if the
`write protection flag 130 indicates that a write from some
`other cell is "inhibited', the circuit generates an access
`exception.
`Some examples of the memory configuration of the
`embodiment according to the present invention will now be
`described.
`When the address resolution tables 120 of nodes iO to i3
`are set up as shown in FIG. 4, the memory configuration is
`as shown in FIG. 5. In FIG. 5, the Solid line areas are
`memories physically installed on each node. Although it is
`assumed in this example that all nodes has the same amount
`of memory, they need not have the same amount of memory
`in an actual System. The vertical axis indicates the memory
`module addresses with the address Space Starting with
`address “0” in each node. Address “0” is at the top of FIG.
`4, while address “O'” is at the bottom in FIG. 5.
`In this memory configuration example, module address
`ees X0 to X2 of each node, which are mapped to the private
`memory of the node, are independent with each other (cell
`private memory). On the other hand, module addresses x3 to
`X6 are set up So that they are unique acroSS cells to allow
`them to be accessed from any node using common addresses
`(shared communication area). In this example, the shared
`area is more than the half of the logical address Space of each
`node. This is because each cell has four memory modules for
`convenience. In an actual configuration, the ratio of the
`shared area to the private area may be Smaller.
`When the address resolution tables 120 of nodes 1900 to
`#3 are set up as shown in FIG. 6, the memory configuration
`is as shown in FIG. 7. In the example shown in FIG. 7, cell
`S0 and cell S1 constitute a computer with the symmetric
`multiprocessor configuration. These two cells form one
`node. The cluster System is therefore comprises three nodes:
`node #0 (cell #0 and cell S1), node #2 (cell S2), and node #3
`(cell S3). In node #0, a total of seven modules, that is, all
`physical memory modules of cell #0 and memory modules
`x0 to X2 of cell S1, are set up as private memory for common
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`use by cell S0 and cell S1. Module X3 of cell S1 is shared
`among the nodes as cluster shared memory (communication
`area). The memory maps of cell S2 and cell S3 are substan
`tially the same as those shown in FIG. 5 with the exception
`that the addresses of the memory modules Set up as shared
`memory are different from those in FIG. 5.
`In the setup shown in FIG. 6, the write protection flag 130
`is used to Specify whether to permit write access from other
`cells. That is, write acceSS in the Same node is permitted even
`if the access is acroSS cells. Therefore, for a memory Setup
`where two or more cells are in the Same node, write acceSS
`from a particular cell (a cell in the same node) must be
`permitted.
`When the address resolution tables 120 of nodes iO to i3
`are set up as shown in FIG. 8, the memory configuration is
`as shown in FIG. 9. In this configuration, only one memory
`module in one particular node is shared among nodes. Note
`that, in this configuration, the write protection flag 130 of
`that memory module must be write-permission. This allows
`all nodes to write into that particular memory module in
`node #0, making available the memory module as commu
`nication means. The problem with this configuration is that
`an error, if generated in node #0, may inhibits node-to-node
`communication, Sometimes forcing the System to go down.
`Therefore, this configuration should be selected with the
`memory size and the communication amount in mind.
`When the address resolution tables 120 of nodes iO to i3
`are set up as shown in FIG. 10, the memory configuration is
`as shown in FIG. 11. This memory configuration is the one
`used for a Symmetric multiprocessor. The memory modules
`of the nodes are re-configured Sequentially, beginning with
`memory module x0 of node #0, into one contiguous address
`Space composed of 16 memory modules. In this configura
`tion, all nodes can acceSS all memory modules.
`In the above description, the address translation table 120
`is used as an example of address resolution means. Out of
`the information stored in the address translation table 120,
`only the routing information is required for forwarding
`access requests from one cell to another. Thus, other infor
`mation Such as the one required for identifying a location a
`destination cell need not always be Stored in the address
`translation table, Such information may be stored, for
`example, at a location within the destination cell.
`The embodiment of the present invention has the address
`resolution table 120 which determines in which cell a
`requested address is included. In addition, the write protec
`tion flag 130 is provided to specify whether or not a write
`request from other cells is permitted. These allow various
`memory configurations to be implemented in a multipro
`cessing System and, at the same time, prevents an error in
`one cell from affecting other cells.
`AS described above, the method according to the present
`invention determines in which cell an address to be accessed
`is included and, at the same time, controls write access from
`one cell to another. Therefore, this method allows the user to
`build various memory configurations for flexible multipro
`ceSSor System operation, ensures cell independence, and
`prevents an error generated in one cell from affecting other
`cells.
`What is claimed is:
`1. A multiprocessor System having a plurality of cells each
`including at least one processor, at least one memory
`module, and a cell controller connecting Said at least one
`processor and Said at least one memory module, wherein
`Said cell controller comprises:
`an address resolution table having at least one entry
`corresponding to Said at least one memory module,
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`each of Said at least one entry holding a number of the
`cell where the corresponding memory module exists,
`means for Searching Said address resolution table using a
`requested address and, when the cell where the memory
`module associated with the requested address is located
`is Some other cell, for accessing the other cell;
`a write protection flag indicating whether or not a write
`acceSS request from other cells is permitted; and
`means for detecting an access exception when an access
`request from Some other cell is the write access request
`and when Said write protection flag indicates that the
`write access request from the other cells is inhibited.
`2. The multiprocessor System according to claim 1,
`wherein each entry of said address resolution table further
`holds a module number within cell of the corresponding
`memory module, and wherein the memory module included
`in said cell is identified by said module number within the
`cell.
`3. The multiprocessor System according to claim 1,
`wherein at least one entry of Said address resolution table
`includes, as the number of the cell where the memory
`module associated with the address exists, the number of the
`cell where Said address resolution table is not included.
`4. The multiprocessor System according to claim 3,
`wherein Said write protection flag is set up to inhibit the
`write access request from other cells.
`5. The multiprocessor System according to claim 4,
`wherein the write access request from one particular cell is
`permitted regardless of the Setup of Said write protection
`flag.
`6. The multiprocessor System according to claim 1,
`wherein said address resolution tables of at least two cells
`have the same cell number in at least one pair of corre
`sponding entries.
`7. The multiprocessor System according to claim 1,
`wherein said address tables of all cells have the same cell
`number in all corresponding pairs of entries.
`8. A cell controller in a multiprocessor System having a
`plurality of cells each including at least one processor, at
`least one memory module, and the cell controller connecting
`Said at least one processor and Said at least one memory
`module, Said cell controller comprising:
`an address resolution table composed of a plurality of
`entries each of which includes a number of the cell
`where the memory module associated with an address
`exists,
`means for Searching Said address resolution table using a
`requested address and, when the cell where the memory
`module associated with the requested address is located
`is Some other cell, for accessing the other cell;
`a write protection flag indicating whether or not a write
`acceSS request from other cells is permitted; and
`means for detecting an access exception when an access
`request from Some other cell is the write access request
`and when Said write protection flag indicates that the
`write access request from the other cells is inhibited.
`9. The cell controller according to claim 8, wherein each
`entry of Said address resolution table further includes an
`identification number of the memory module within the cell,
`Said memory module associated with the address, and
`wherein the memory module included in Said cell is iden
`tified by said identification number within the cell.
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