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`Kluwer Academic Publishers
`
`I
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`!!
`
`Page 1
`
`Qualcomm Ex. 1014
`
`

`

`Networks on Chip
`
`edited by
`Axel Jantscb
`Royal Institute of Technology, Stockholm
`
`and
`Hanno Tenhunen
`Royal Institute of Technology, Stockholm
`
`KLUWER ACADEMIC PUBLISHERS
`BOSTON/DORDRECHT/LONDON
`
`Page 2
`
`Qualcomm Ex. 1014
`
`

`

`A C.I.P. Catalogue record for this book is available from the Ubrar.y of Congress.
`
`Contents
`
`ISBN 1-4020-7392-5
`
`Published by Kluwer Academic Publishers,
`P.O. Box 17, 3300AA Dordrecht, The Netherlands.
`
`Sold and distributed in North, Central and South America
`by Kluwer Academic Publishers,
`101 Plrilip Drive, Norwell, MA 02061, U.S.A.
`
`In all other countries, sold and distributed
`by Kluwer Academic Publishers,
`P.O. Box 322, 3300 AH Dordrecht, The Netherlands.
`
`Preface
`
`Part I System Design and Methodology
`
`1
`Will Networks on Chip Close the Productivity Gap?
`Axel Jantsch and Hannu Tenhunen
`
`2
`A Design Methodology for NoC-based Systems
`Juha-Pekka Soininen and Hannu Heusala
`
`3
`Mapping Concurrent Applications onto Architectural Platforms
`Andrew Mihal and Kurt Keuti,er
`
`vii
`
`3
`
`19
`
`39
`
`Printed on acid-free paper
`
`4
`61
`Guaranteeing The Quality of Services in Networks on Cbip
`Kees Goossens, JohnDielisse,i, JefvanMeerberg_'!_n, Peter Poplavko, AndreiRitdulescu,
`Edwin Rijpkema, Erwin Waterlander and Paul ffielage
`
`All Rights Re!lerved
`e 2003 Kluwer Academic Publishers, Boston
`No part of this work may be reproduced, stored in a re1rievaJ system, or transmitted
`in any fonn or by any means, electronic, mechanical, photocopying, microfilming, recording
`or otherwise, without written permission from the Publisher, with the exception
`of any material supplied specifically for the purpose of being entered
`and executed on a computer system, for exclusive use by the purchaser of the work.
`
`Prlnled in the Netherlands.
`
`Part II Hardware and Basic Infrastructure
`
`5
`On Packet Switched Networks for On-chip Communication
`Shashi Kumar
`
`6
`Energy-reliability Trade-off for NoCs
`Davide Bertozzi, Luca Benini and Giovanni De Micheli
`
`7
`Tusting Strategies for Networks on Chip
`Raimund Ubar and Jaan Raik
`
`85
`
`107
`
`131
`
`V
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`Page 3
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`Qualcomm Ex. 1014
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`

`

`vi
`
`8
`Clocking Strategies for Networks on Chip
`Johnny Oberg
`
`9
`A Parallel Computer as a NoC Region
`·
`Martti Forsell
`
`10
`An IP-Based On-Chip Packet-Switched Network
`llkka Saastamoinen, David Siguenza-Tortosa and Jari Nurmi
`
`NETWORKS ON CHIP
`
`Preface
`
`153
`
`173
`
`193
`
`Part m Software and Application Interfaces
`11
`Bey~d the vo_n Neumann Machine: Communication as the Driving De-
`sign Paradigm for MP-SoC from Software to Hardware
`Eric Verhulst
`
`217
`
`,.
`
`12
`Noc Application Programming Interfaces
`Zhonghai Lu and Raimo Hauldlahti
`13
`261
`Multi-level Software Validation for Noc
`Sund:gjff!__ Yoda, GabrielaNicolescu, lulianaBacivarov. Wassim YousseJAimenBouchhima
`an A,une A. Jerraya
`
`239
`
`14
`S~ftware for Multiprocessor Networks on Chip
`Miltos Grammatikakis, Marcello Coppola and Fabrizio Sensini
`
`281
`
`During the 1990s more and more processor cores and large reusable compo(cid:173)
`nents have been integrated on a single silicon die, which has become known un(cid:173)
`der the label System on Chip (SoC). Main difficulties of this era were, and still
`are. the standardization of the component interfaces and the validation of the
`entire system with respect to its physical and functional properti~. Buses and
`point to point connections were the main means to connect the components.
`Buses are attractive because they provide high performance interconnections
`while they can still be shared by several communication partners. Hence they
`can be used very cost efficiently.
`As silicon technology advances further, several problems related to buses
`have appeared. Buses can efficiently connect 3.10 communication partners but
`they do not scale to higher numbers. Even worse, they behave very unpre(cid:173)
`dictably as seen from an individual component, because many other compo(cid:173)
`nents also use them. A second problem comes from the physics of deep submi(cid:173)
`cron technology. Long, global wires and buses become undesirable due to their
`low and unpredictable performance, high power consumption and noise phe(cid:173)
`nomenon. A third problem comes from the application perspective. Designing
`and verifying the inter-task communication in a system is a hard problem per
`se. Getting it to work and dimensioning communication resources correctly
`is even harder for large bus based communication networks due to the unpre(cid:173)
`dictability of the communication performance. Moreover, every system has a
`different communication structure, making reuse difficult.
`As a consequence, around 1999 several research groups have started to in•
`vesti.gate systematic approaches to the design of the communication part of
`SoCs. It soon turned out that the problem has to be addressed at all levels from
`the physical to the architectural to the operating system and application level.
`Hence, the term Network on Chip (NoC) is today used mostly in a very broad
`meaning, encompassing the hardware communication infra-structure, the mid(cid:173)
`dleware and operating system communication services and a design methodol(cid:173)
`ogy and tools to map applications onto a NoC. All this together can be called a
`NoC platform. The breadth of the topic is also highlighted by the scope of this
`book which ranges from physical issues to embedded software. Quite natural
`
`vii
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`Page 4
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`Qualcomm Ex. 1014
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`

`

`I
`
`SYSTEM DESIGN AND METHODOLOGY
`
`li
`
`viii
`
`NETWORKS ON CHIP
`
`for a young and quickly evolving research area, the tenninology is not yet uni(cid:173)
`fonnly used and different authors use the terms differently. as it will become
`apparent when reading this book.
`It should not come as a surprise that the first part deals with design and
`methodology issues. The infamous design productivity gaJ>.is one of the strongest,
`if not the single most important, driving force towards design, architecture and
`implementation structures. Only when we succeed to restrict the design spaoe
`in a sensible way will we be able to exploit technology potential. Several
`chapters of the :first part emphasize predictability of the design process and the
`guarantee of high level features by all implementations.
`The second part is concerned with the hardware infrastructure. The net(cid:173)
`work topology, power management, fault tolerance, testing and clocking, among
`other topics, are all key issues that must be-solved satisfactori•y to make NoCs
`feasible.
`Software and the application perspective is in the center of part three. Not
`surprisingly, communication services and the role of the operating system in
`future NoC systems a.re central in the chapters of this part.
`Although this book touches upon most of the important NoC issues, many
`are only superficially dealt with and some key issues are not addressed. NOC:
`is a young and emerging area and we still have to learn to asses the quality of a
`particular solution, be it for the topology, switch design. communication or op•
`crating system services, with respect to an application or application area. We
`expect for the near future that NoC specific cost and performance will be devel(cid:173)
`oped that may be application sensitive. An interesting question is for instance,
`how to express the communicati.onpetfonnance of a NoC. Raw bandwidth may
`oot be adequate for applications with a highly variable traffic pattern consisting
`of a mixture of real-time control messages and high throughput video streams.
`In addition. transient faults may occasionally destroy transmitted information,
`which may make a fault management and retransmission scheme necessary.
`But again, this will depend on the sensitivity of the application data. Hence,
`efficiency of a particular NoC system will be more and more expressed in re(cid:173)
`lation to an application or an application area. Existing benchmarks can be
`used to address this question but new and modified benchmarks will also be
`required.
`As it is indicated frequently in this book, NoC could lead to a fundamental
`paradigm shift with respect to the way we develop platfonns, we design sys(cid:173)
`tems and we model applications. At least it will result in a scalable platform
`architecture for the billion transistor chip era. We expect in any case th_e NoC
`area to flourish and prosper and take unexpected and innovative turns and di(cid:173)
`rections and we hope that this book contributes to this exciting research theme.
`
`Axm. JANTSCH AND HANNu TBNHUNEN
`
`Page 5
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`Qualcomm Ex. 1014
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`

`

`Chapter 1
`
`WILL NETWORKS ON CHIP
`CLOSE THE PRODUCTIVITY GAP?
`
`Axel Jantsch and Hannu Tenhunen
`Royal Institute of Technology, Stockholm
`axelOimit,kth.se, hannu@imit.kth.se
`
`Abstract We introduce two properties of the design process called the arbitraf\l
`composability and the linear effort properties. We argue that a design
`paradigm, which has these two properties is scalable and has the poten(cid:173)
`tial to keep up with the pace of technology advances. Then we discuss
`some of the_ trends that will enforce significant changes on current de(cid:173)
`sign methodologies and techniques. Finally, we argue that the emerging
`Network-on-Chip (NoC) paradigm promises to address tbeBe trends and
`challenges and has all prerequisites to provide the arbitriu:y compo118obil(cid:173)
`ity and the linear effort properties. Consequently we conclude that NoC
`is a likely buis for future System-on-Chip platforms and methodologies,
`
`Keywords: Networks on chip, Productivity gap, System on chip design methodology
`
`Introduction
`1.
`To boost design productivity it is crucial that the effort to add new
`parts to a. given design does not depend on the size of the existing design
`but only on the size of the new parts, In other words, the design effort
`must be a. linear function of the size of the new parts. If this is the
`case, large parts and blocks of previous designs can be reused and the
`design effort can be invested into the new parts. This is also a necessary
`prerequisite to provide a. solid methodology, architecture, and thus a
`platform., that are sustainable over several technology generations.
`The central thesis of this chapter is that a Network-on-Chip (NoC) has
`the potential to provide such a sustainable platform a.nd, if successful,
`will incur such a significant change on the system-on-chip architecture
`3
`A .lancch ar,d H. le11hunm (eds.), Networkl on Chip, 3-18.
`0 2003 KlwNe_r Acadenuc· Publishen. Prinred bt the Netherlu,ul,,.
`
`Page 6
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`Qualcomm Ex. 1014
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`

`

`,...---
`
`..
`
`4
`
`NETWORKS ON CHIP
`
`Will Networb on Chip Close the Prod'UCtimty Gap?
`
`5
`
`and design process that •it can be called a paradigm change. On the other
`hand, if it fails to do so, NoC will be just one of several architectures
`· and platforms available to embedded system designers.
`
`Arbitrary composability property: Given a.set of components
`and a set of com1'inator operators which allow to co~nect and in(cid:173)
`tegrate fhe components into larger component assemblage.s. Com(cid:173)
`ponents and combinators together are arbitrorily oomposable if a
`given c.omponent assemblage A can be extended with any compo(cid:173)
`nent by using any of fhe combinators without changing the relevant
`behavior of A.
`
`Please note, that this and the following property are meant as en(cid:173)
`gineering heuristics, not as mathametical properties. As such they are
`ideals and can be achieved at higher or lower degrees.
`Note further, that this property is defined with respect to what is con(cid:173)
`sidered to be a relevant behavior. Thus depending on the given objectives
`and definition of behavior, the same components and combinators may
`or may not have the arbitrary composa.bility property.
`For instance, the standard logic gates NAND, NOR, INV, etc. have this
`property with respect to their logic level I/0 behavior because adding
`new gates to a netlist of gates will not change the behavior of the original
`netlist, unless old connections are broken. A given network of gates can
`be used in any context and will exhibit identical behavior whatever the
`surrounding netlist may be. New gate netlists can be added to existing
`ones, using the outputs and results produced by any other part of the
`circuit without changing the older parts. This is the foundation of our
`ability to build designs with millions of gates and to reuse large blocks
`in arbitrary environments.
`It should be noted that this nice property of gates is in part due to
`the implementation process which allows the sea.ling of transistor sizes,
`insertion of buffers, and sensible placement and routing by automatic
`tools.
`It is enlightening to see the effects when the arbitrary composition
`property is violated. Two of the most severe problems in today's designs
`stem from violations of this property. Timing closure, i.e. the problem
`to get the timing of the circuit implementation right, is difficult because
`small changes or addition to the gate netlist may change the timing of
`the entire system by adding to the critical path or due to an unexpected
`effect of placement and routing on the timing of seemingly unrelated
`circuit parts. The system verification problem is so hard because at the
`system level behaviors are not easily composahle and tiny changes in one
`pa.rt may have unexpected effects on seemingly u~elated other parts of ·
`
`the system. In both cases the design effort grows more than linear with
`the system sfa;e.
`If this property is guaranteed, the effort of adding new components to
`a working system only depends on the new components but not on the
`size of the reused system (figure 1.1). Thus, a corollary of the arbitrary
`s
`
`Figure 1.1. With the arbitrary oomposa.bility property the design effort to add new
`components to an existing system depends on the integration effort a.nd on the new
`components but not- on the size of A becl.\uSe the design effort to build A hllll al(cid:173)
`ready been spent and is reused BB well: Deffozt(S) = Deffort(B) + Deffort(C) +
`Ieffort(3)
`
`composability property is the following linear effort property.
`
`Linear Effort Property: Given is a set of components and a set
`of combinator operators which allow to connect and integrate the
`components into larger component assemblages. A design proress
`which builds a system from the components and combinators has
`the linear effort property if a given set of n assemblages A1, ... 1 An
`can be integrated into a system S by means of the combinators with
`an effort dependent on n but not on the size of the a3semblages:
`Ief fort( n). Thus the total design effort for S is
`Deffo:rt(S) = Deffort(A1) + · · · + Deffort(An) + Ieffort(n)
`
`Note, that this property implies that the interface complexity of an
`assemblage does not depend on the size of the assemblage. Obviously,
`this is not true in practice but it is equally obvious that this is a necessary
`precondition to build arbitrary large systems. Thus, we must approach
`this ideal as close as possible to be able to build larger and larger systems.
`The fact, that we have not been sufficiently close to this ideal is the
`fundamenta.l reason for the design productivity gap.
`We believe that NoC based platforms have a. good potential to provide
`both the arbitrary composition and the linear effort properties to a. high
`degree but they do not automatically guarantee them. We will keep
`these properties in mind throughout this chapter, but first we review
`
`Page 7
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`Qualcomm Ex. 1014
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`

`

`6
`
`NETWORKS ON CHIP
`
`Will Networks on Chip Close the Productivity Gap?
`
`7
`
`some of the underlying trends and challenges that lead to NoC and
`similar architectures.
`
`Trends and Challenges
`2.
`IC manufacturing technology will provide us with a"a few billi~n tran(cid:173)
`si_st~rs on a single chip within a few years [1]. Assuming that these pre(cid:173)
`d1ct1ons hold and that the market will continue to absorb ever higher
`volu~es of !Cs, the key questions are: how will the future chips be
`org?'mzed and how will future systems, which include these chips, be
`d~1~ed? There are a few trends which, if continued, will bring about
`a s1gmficant change for architecture and design of integrated circuits.
`
`Communication versus computation.
`Technology scaling works
`better for transistors than for interconnecting wires. This leads grad(cid:173)
`ually to a _domination of performance figures, power consumption and
`area by wires and make transistors of secondary importance. At the
`system level it has a profound effect by changing the focus from num(cid:173)
`ber crunching and computation to data transport and communication
`[2, 3, 4]. Commwtlcation becomes often the bottleneck because it seems
`much harder to design and get right.
`
`Deep submicron effects.
`Cross-coupling, noise and transient
`~rrors are only some of the wipleasant side-effects of technology seal(cid:173)
`mg [5, 6). It requires significant skills, experience, knowledge and time
`to k~p them under control while exploiting the limits of a technology.
`A. d~g1tal or system designer with an expected design productivity of
`mtlhons of transisto~ per day is not able to deal with these effects prop(cid:173)
`erly. The~efore, designers ~euse blocks which are carefully designed by
`experts with the proper skills, However, it is of critical importance that
`the deep submicron effects don't pop up again when predesigned blocks
`are combined in arbitrary ways. Consequently, at the physical design
`level the property of arbitrary composability means that the electrical
`and physical properties of blocks are not affected when combining them.
`
`Glob~ ~ynchr_ony.
`Physical effects of deep sub-micron technology
`make it 1ncrea:5mgly difficult to_ maintain global synchrony among all
`parts of the chip (7J, The clock signal will soon need several clock cycles
`t~ tr~ve~ the chip, clock skew becomes unmanageable, and the clock
`d1stnbut1on tree is already today a major source of power consumption
`~d cost. The trends of scaling to smaller geometric dimension and
`higher clock frequency make these problems more significant every year.
`
`Thus, it is unlikely that large chips will be synchronous designs with
`only one clock domain.
`
`Design productivity gap.
`Synthesis and compiler technology
`development do not keep pace with IC manufacturing technology de(cid:173)
`velopment [1]. As a consequence , we need either exponentially growing
`design teams or design time to design and implement systems which fit
`onto a. single IC. Since both alternatives are unrealistic we have in the
`past escaped from the problem by using ever more complex components
`a.s primitive design units. These primitive design units have evolved
`from individual transistors to logic gates to entire ALUs, multipliers,
`finite state machines and processor cores. In fa.ct reuse of ever more
`complex design elements has been the main device to increase produc(cid:173)
`tivity and will likely remain so in the years to come. It has a.lso kept
`us close enough to the ideal of the linear effort property to manage the
`increasing number of transistors.
`
`Heterogeneity of functions.
`Obviously, systems that can be
`implemented on a single chip become increasingly more complex. As a
`result different functions and features with vastly different characteris(cid:173)
`tics and history reside on the same chip. Signal processing algorithms,
`that recover and generate radio signals, will coexist with global control,
`maintenance and accounting functions as well as with natural language
`comprehension and generation functions. These functions are developed.
`in different contexts, by different teams, with different design languages
`and tools. However, they need to be integrated into a single chip.
`In order to lead a. concrete discussion we describe next a typical NoC
`architecture and in section 4 we investigate how a NoC approach could
`address the listed problems. To paint a fair picture section 5 illuminates
`the price to pay when adopting a NoC based approach. Finally, in
`section 6 we speculate how the design process will change.
`
`Network on Chip
`3.
`The Network-on-Chip (NcC) architecture, as outlined in figure 1.2,
`provides the communication infrastructure for the resources.
`In this
`way it is possible to develop the hardware of resources independently
`as stand-alone blocks and create the NoC by connecting the blocks as
`elements in the network. Moreover, the scalable and configurable net(cid:173)
`work is a. flexible platform that can be adapted to the needs of different
`workloads, while maintaining the generality of application development
`methods and practices.
`
`Page 8
`
`Qualcomm Ex. 1014
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`

`

`8
`
`NETWORKS ON CHIP
`
`Will Networks on Chip Close the Productivity Gap'?
`
`9
`
`...---
`
`Note, that this is one, fairly simple NoG variant described here only
`to substantiate the following discussion. Many other more sophisticated
`architectures have been proposed [8, 9, 10, 11, 12, 13, 14].
`
`How does NoC address the problems
`4.
`Although there are numerous factors and facets to. investigate, we
`focus on two mechanisms that work in favor of a NoC based approach:
`Reuse and Predictability. We believe these are by far the most important
`factors overshadowing other secondary effects.
`
`Reuse
`4.1
`As mentioned above, reuse has always been the primary means to
`bridge the technology gap (15, 16, 17]. More and more complex com(cid:173)
`ponents, from transistors to gates to functional blocks, such as ALUs
`and multipliers, to microprocessors and DSP cores, have become the
`primitive building blocks. In this way, the designers could move up
`the abstraction levels and describe the system's functionality in more
`and more abstract terms relying on more and more powerful "primitive"
`components. Curiously, synthesis technology has mostly been used to
`bridge one, relatively shallow, level of abstraction. This can be observed
`in both the hardware and the software domain. Technology mapping,
`logic and RTL synthesis are in principle straight forward steps with a well
`characterized optimization space. Synthesis techniques that attempted
`to bridge more abstraction levels and to make more profound design de(cid:173)
`cisions have typically failed. Examples are high level and architectural
`synthesis. In soaware the mapping from C to microprocessor instruction
`sets is more or less direct and the corresponding compiler technology is
`tremendously successful. In contrast, compilation from functional, logic
`and other higher level languages lacks efficiency and has never become
`mainstream. Thus, we believe that reuse by providing more complex
`components will continue to be the main mechanism to exploit the po(cid:173)
`tential of technology. Synthesis and compilation techniques will provide
`the surface mapping from more convenient descriptions onto the primi-
`tive components.
`However, as a difference to the past, communication "components'',
`or better, communication structures and services have also to become
`primitive design elements. And this is precisely what a NoC based ap(cid:173)
`proach is all about: The reuse of communication services.
`Let us briefly review what can be reused in a NoC based approach.
`
`Figure 1.2. Each node in the mesh contains a switch and a resource.
`
`A two dimensional mesh interconnection topology is simplest from
`a layout perspective and the local interconnections between resources
`and switches are independent of the size of the network. Moreover
`routing in a tw1>-dimensional mesh is easy resulting in potentially small
`switches, high bandwidth, short clock cycle, and overall scalability. A
`NoC consists of resources and switches that are directly connected such1
`that resources are able to communicate with each other by sending mes(cid:173)
`sages. A resource is a computation or storage unit. Switches route
`and buffer messages between resources. Each switch is connected to
`four other neighboring switch.es through input and output channels. A
`channel consists of two one-directional point-to-point buses between two
`switches or a resource and a switch. Switches may have internal queues
`to handle congestion. We expect that the area of a resource is either
`the maximal synchronous region in a given technology or a cluster of
`~mputing elements and memory connected via a bus. We expect the
`size of a resource to shrink with every new technology generation. Con(cid:173)
`sequently the number of resources will grow, the switch-to-switch and
`the switch-to-resource bandwidth will grow, but the network wide com(cid:173)
`munication protocols will be unaffected.
`
`Page 9
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`Qualcomm Ex. 1014
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`

`

`10
`
`NETWORKS ON CHIP
`
`Will Network! on Chip Close the Productivity Gap?
`
`11
`
`Components and resources.
`Arbitrary computation elements
`can be connected to the communication network. In fact we expect that
`typical NoC based systems may contain processor cores, DSP cores
`memory banks, specialized I/O blocks such as Ethernet or Bluetooth
`proto~ol stack implementations, graphics processors,.FPGA blocks, etc.
`The size of a resource can range from a bare processor core to a local
`cluster of several processors and memory connected via a local bus. Re(cid:173)
`~ources have to comply to the interfaces of the communication network
`m order to connect to it a.nd use its services.
`The reuse o! proces~r cores has been developed during the last ten
`yea.rs by_ definmg bus mterfa.ces. By defining network interfaces, NoC
`takes this concept further because it allows to integrate an arbitrary
`number of resources into a network. In a bus-based system adding
`a new resource has a profound impact on the performance of' the rest
`of the system because the same communication resource is now shared
`among more resources. In a NoC adding new resources also means to
`add new communication capacity by adding new switches and inter(cid:173)
`con~ects. This scal~?ility property is a necessary precondition for the
`arbitrary co~p~abil1ty property but it is not sufficient to guarantee it.
`The co~un1cat1on network must further be able to guarantee allocated
`b~dw1dth and to enforce a decent behaviour ofthe resources to avoid
`for ms_tance the monopolization of the entire communication bandwidth
`by a smgle resource.
`However, it ~s import~t to acknowledge, that a NoC baBed approach
`has the potential to provtde the arbitrary composability property with
`tremendous benefits for the design productivity.
`
`Communication infrastructure.
`The main immediate benefit
`from a NoC based approach is clearly due to the possibility to
`k
`t'
`reuse
`th
`·
`e commu.mca 10n networ . The switches, the interconnects and the
`'fi d
`lower level communication protocols can be desian opt1·...... d
`d ·
`...... ze , ver1 e
`-o&•,
`an _1mplemented once and reused in a large number of products. If
`r~wrements . on . performance) reliability and cost differ too much in
`different apphcat10n domains, domain specific communication networks
`can be reused at least for all products in the same domain For 1·nst
`li1• 1 h
`b'l
`·
`a.nee,
`'t .
`1 1s A€ Y t at mo 1 e, hand"held devices have so different de
`ds
`.
`man
`on po';'er consumption and performance than infra-structure equipment
`that different NoC platf~rms for theae two domains are well justified.
`Apart fro~ the hardwired communication infra-structure, higher level
`net~ork services can as well be reused. There is in fact a long list of
`services that would benefit many applications but can impossibly be
`developed from scratch for each new product. Examples are
`
`•
`
`the detection, monitoring and management of faults in the net(cid:173)
`work;
`
`■ the allocation and management of network resources and possibly
`task migration for load balancing and power optimization;
`
`■ the management of global and shared memory;
`
`■ the provision of sophisticated communication services such as chan(cid:173)
`nels with guaranteed bandwidth and quality of service, multi-cast
`and broadcast communication, etc.
`
`Most of these tasks are typically provided by the operating system
`in today's uniprocessor applications. Similarly, a NoC operating system
`will be very generic and can be reused for many products. Due to the
`increased complexity of future systems as compared to today's systemsi
`the operating system will be much more sophisticated and complex, thus
`making the case for reuse even stronger.
`
`Application parts and feature reuse.
`Reuse will not stop with
`components and generic services. New products can be composed of ex(cid:173)
`isting, complete features. Peeking into the future we can envision a tra(cid:173)
`ditional mobile phone which is enhanced by speech analysis subsystem,
`a speech synthesizer and a. language analysis and processing sub-system
`to provide a spoken language interface to the phone. The same modules
`or features are apparently useful in a wide range of products and should
`therefore be reused as much as possible. Obviously, the main challenge
`will be to define and standardize the high level interfaces between these
`features to allow for an efficient communication and sharing of informa,.
`tion. However, we can observe that a NoC provides an excellent ground
`for this kind of feature reuse. For optimized implementation a feature
`may come fully implemented either in software or partially as a dedi(cid:173)
`cated hardware block. Either wa.y1 the feature can be plugged into one
`or several resource slots and the NoC providf'J3 at lea.st the low level
`communication and network services for free for the interaction between
`the feature and the rest of the system.
`
`Design, simulation and prototype environment.
`A significant
`part of system development costs are typically spent in setting up simu(cid:173)
`lation environments and building prototypes. Since many products are
`based on the same NoC platform much of this investment can be shared
`by many products. Furthermore, even if different domain specific NoC
`platforms vary in their performance and power characteristics, they are
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`Qualcomm Ex. 1014
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`12
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`NETWORKS ON CHIP
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`Will Networks an Chip Close the Productivity Gap?
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`13
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`sufficiently similar to allow the reuse of much of the design and verifica,.
`tion environment across very different application domains. In contrast,
`- application specific platforms which are not derived from the same prin(cid:173)
`ciple concepts but are developed in an ad-hoc way to suit a particular
`application domain, will not provide as much potential for cross-domain
`reuse.
`
`Verification effort.
`The system verification effort is frequently as
`high as the design effort itself. Hence, by reusing predesigned and prever(cid:173)
`ified parts and services, verification time can be as drastically reduced
`as design time. But reuse is even more important for the verification
`than for the design activity because the uncertainty about the required
`verification time is much higher and more difficult to plan. Moreover,
`the uncertainty about the resulting product quality is high and the po(cid:173)
`tential cost of undetected errors in the final product can be enormous.
`Since risk and uncertainties around verification and verification effects
`are much higher, verification benefits more from reuse than the design
`activities. Reused components are typically much better verified, be(cid:173)
`cause they have already been used in other products. Moreover, system
`verification can be done much more effectively when correctness and re(cid:173)
`liability of the components can be assumed, because errors are identified
`faster.
`In swnmary, the usage of a NoC based platform boosts the potential
`for reuse in many ways.
`
`Predictability
`4.2
`The second ma.in aspect of our focus is predictability and it is in fact
`closely related to reuse.
`
`Communication performance.
`Due to its regular geometry and
`communication network, communication performance becomes poten(cid:173)
`tially much more predictable. "Potentially" and not "necessarily" be(cid:173)
`cause the regular communication hardware will significantly help to an(cid:173)
`alyze and assess performance but measures at higher protocol levels and
`network services have to realize this potential. Since the communication
`hardware is shared by many resources, the activity of one resource can
`delay the communication of other resources. One mis-behavi