(12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT)
`
`(19) World Intellectual Property Organization
`International Bureau
`
`( 43) International Publication Date
`24 April 2008 (24.04.2008)
`
`(51) International Patent Classification:
`HOIL 21144 (2006.01)
`
`1111111111111111 IIIIII IIIII 11111111111111111111111111111111111 lllll lllll llll 1111111111111111111
`
`PCT
`
`(10) International Publication Number
`WO 2008/049019 A2
`(74) Agents: FLEISCHUT, Paul, I.j. et al.; Senniger Powers,
`One Metropolitan Square, 16th Floor, St. Louis, Missouri
`63102 (US).
`
`iiiiiiii
`
`(21) International Application Number:
`PCT/US2007/081671
`
`(22) International Filing Date: 17 October 2007 (17.10.2007)
`
`(25) Filing Language:
`
`(26) Publication Language:
`
`English
`
`English
`
`(30) Priority Data:
`60/829,797
`60/887,233
`
`17 October2006 (17.10.2006) US
`30 January 2007 (30.01.2007) US
`
`(71) Applicant (for all designated States except US): EN(cid:173)
`THONE INC. [US/US]; 350 Frontage Road, West Haven,
`Connecticut 06516 (US).
`
`(72) Inventors; and
`LIN, Xuan
`(75) Inventors/Applicants (for US only):
`[CN/US]; c/o Enthone Inc., 350 Frontage Road, Wet
`Haven, Connecticut 06516 (US). HURTUBISE, Richard
`[US/US]; c/o Enthone Inc., 350 Frontage Road, West
`Haven, Connecticut 06516 (US). PANECCASIO, Vin(cid:173)
`cent [US/US]; c/o Enthone Inc., 350 Frontage Road,
`West Haven, Connecticut 06516 (US). CHEN, Qingyun
`[CN/US]; c/o Enthone Inc., 350 Frontage Road, West
`Haven, Connecticut 06516 (US).
`
`(81) Designated States (unless otherwise indicated, for every
`kind of national protection available): AE, AG, AL, AM,
`AT, AU, AZ, BA, BB, BG, BH, BR, BW, BY, BZ, CA, CH,
`CN, CO, CR, CU, CZ, DE, DK, DM, DO, DZ, EC, EE, EG,
`ES, Fl, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL,
`IN, IS, JP, KE, KG, KM, KN, KP, KR, KZ, LA, LC, LK,
`LR, LS, LT, LU, LY, MA, MD, ME, MG, MK, MN, MW,
`MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PG, PH, PL,
`PT, RO, RS, RU, SC, SD, SE, SG, SK, SL, SM, SV, SY,
`TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA,
`ZM, ZW.
`
`(84) Designated States (unless otherwise indicated, for every
`kind of regional protection available): ARIPO (BW, GH,
`GM, KE, LS, MW, MZ, NA, SD, SL, SZ, TZ, UG, ZM,
`ZW), Eurasian (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM),
`European (AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, Fl,
`FR, GB, GR, HU, IE, IS, IT, LT, LU, LV, MC, MT, NL, PL,
`PT, RO, SE, SI, SK, TR), OAPI (BF, BJ, CF, CG, CI, CM,
`GA, GN, GQ, GW, ML, MR, NE, SN, TD, TG).
`
`Published:
`without international search report and to be republished
`upon receipt of that report
`
`!!!!!!!! --iiiiiiii
`!!!!!!!! -
`-
`_---------------------------------------------
`(54) Title: COPPER DEPOSITION FOR FILLING FEATURES IN MANUFACTURE OF MICROELECTRONIC DEVICES
`
`!!!!!!!!
`iiiiiiii
`iiiiiiii
`
`,-...I
`
`°"
`Q °" "'1'
`Q ---QO
`Q
`(57) Abstract: A method for plating copper onto a semiconductor integrated circuit device substrate by forming an initial metal
`0
`deposit in the feature which has a profile comprising metal on the bottom of the feature and a segment of the sidewalls having
`M essentially no metal thereon, electrolessly depositing copper onto the initial metal deposit to fill the feature with copper. A method
`0 for plating copper onto a semiconductor integrated circuit device substrate by forming a deposit comprising a copper wettable metal
`
`: , in the feature, forming a copper-based deposit on the top-field surface, and depositing copper onto the deposit comprising the copper
`;;, wettable metal to fill the feature with copper.
`
`IPR2024-00534
`Samsung Electronics Co. Ltd. et al v. Chien-Min Sung
`Samsung's Exhibit 1007
`Ex. 1007, Page 1
`
`

`

`WO 2008/049019
`
`PCT/0S2007/081671
`
`COPPER DEPOSITION FOR FILLING FEATURES
`
`IN MANUFACTURE OF MICROELECTRONIC DEVICES
`
`FIELD OF THE INVENTION
`
`[0001] This invention relates to copper deposition for
`
`filling of features such as trenches and vias in
`
`microelectronic devices.
`
`BACKGROUND OF THE INVENTION
`
`[0002] An integrated circuit (IC) contains a collection
`
`of electrical devices, such as transistors, capacitors,
`
`resistors, and diodes, within a dielectric material on a
`
`semiconductor substrate. Conductive interconnects connecting
`
`discrete devices are referred to as trenches. Additionally,
`
`two or more conductive layers, each separated by a dielectric,
`
`are typically employed within a given IC to increase its
`
`overall performance.
`
`[0003] Conductive interconnects known as vias are used to
`
`connect these distinct conductive layers together. Currently,
`
`ICs typically have silicon oxide as the dielectric material
`
`and copper as the conductive material.
`
`[0004] The demand for manufacturing semiconductor IC
`
`devices such as computer chips with high circuit speed, high
`
`packing density and low power dissipation requires the
`
`downward scaling of feature sizes in ultra large scale
`
`integration (ULSI) and very large scale integration (VLSI)
`
`structures. The trend to smaller chip sizes and increased
`
`circuit density requires the miniaturization of interconnect
`
`features, which severely penalizes the overall performance of
`
`the structure because of increasing interconnect resistance
`
`and reliability concerns such as electromigration.
`
`[0005] Traditionally, such structures had used aluminum
`
`and aluminum alloys as the metallization on silicon wafers
`
`with silicon dioxide being the dielectric material.
`
`In
`
`Ex. 1007, Page 2
`
`

`

`WO 2008/049019
`
`2
`
`PCT/0S2007/081671
`
`general, openings are formed in the dielectric layer in the
`
`shape of vias and trenches after metallization to form the
`
`interconnects.
`
`Increased miniaturization is reducing the
`
`openings to submicron sizes (e.g., 0.5 micron and lower).
`
`[0006] To achieve further miniaturization of the device,
`
`copper has been introduced to replace aluminum as the metal to
`
`form the connection lines and interconnects in the chip.
`
`Copper metallization is carried out after forming the
`
`interconnects. Copper has a lower resistivity than aluminum
`
`and the thickness of a copper line for the same resistance can
`
`be thinner than that of an aluminum line.
`
`[0007] The use of copper has introduced a number of
`
`requirements into the IC manufacturing process. First, copper
`
`has a tendency to diffuse into the semiconductor's junctions,
`
`thereby disturbing their electrical characteristics. To
`
`combat this occurrence, a barrier layer, such as titanium
`
`nitride, tantalum, or tantalum nitride, is applied to the
`
`dielectric prior to the copper layer's deposition.
`
`It is also
`
`necessary that the copper be deposited on the barrier layer
`
`cost-effectively while ensuring the requisite coverage
`
`thickness for carrying signals between the IC's devices. As
`
`the architecture of ICs continues to shrink, this requirement
`
`proves to be increasingly difficult to satisfy.
`
`[0008] One conventional semiconductor manufacturing
`
`process is the copper damascene system. Specifically, this
`
`system begins by etching the circuit architecture into the
`
`substrate's dielectric material. The architecture is
`
`comprised of a combination of the aforementioned trenches and
`
`vias. Next, a barrier layer is laid over the dielectric to
`
`prevent diffusion of the subsequently applied copper layer
`
`into the substrate's junctions. Copper is then deposited onto
`
`the barrier layer using one of a number of processes,
`
`including, for example, chemical vapor deposition (CVD),
`
`physical vapor deposition (PVD), or electrochemical
`
`Ex. 1007, Page 3
`
`

`

`WO 2008/049019
`
`3
`
`PCT/0S2007/081671
`
`deposition. After the copper layer has been deposited, excess
`
`copper is removed from the facial plane of the dielectric,
`
`leaving copper in only the etched interconnect features of the
`
`dielectric. Subsequent layers are produced similarly before
`
`assembly into the final semiconductor package.
`
`[0009]
`
`In one process Cu or other metal seed is applied
`
`by PVD or CVD in a thin or discontinuous layer into features
`
`such as vias and trenches, and in some instances it is more in
`
`the nature of islands than a layer. This metal seed then
`
`provides electrical conductivity for electrodeposition of Cu
`
`to fill the features.
`
`[0010] Electrolytic Cu systems have been developed which
`
`rely on so-called "superfilling" or "bottom-up growth" to
`
`deposit Cu into high aspect ratio features. Superfilling
`
`involves filling a feature from the bottom up, rather than at
`
`an equal rate on all its surfaces, to avoid seams and pinching
`
`off that can result in voiding. Systems consisting of a
`
`suppressor and an accelerator as additives have been developed
`
`for superfilling. As the result of momentum of bottom-up
`
`growth, the Cu deposit is thicker on the areas of interconnect
`
`features than on the field area that does not have features.
`
`These overgrowth regions are commonly called overplating,
`
`mounding, bumps, or humps. Smaller features generate higher
`
`overplating humps due to faster superfill speed. The
`
`overplating poses challenges for later chemical and mechanical
`
`polishing processes that planarize the Cu surface. A third
`
`organic additive called a "leveler" is typically used to
`
`reduce the overgrowth.
`
`[0011] As chip architecture gets smaller, with
`
`interconnects having openings on the order of 100 nm and
`
`smaller through which Cu must grow to fill the interconnects,
`
`there is a need for enhanced bottom-up speed. That is, the Cu
`
`must fill "faster" in the sense that the rate of growth on the
`
`feature bottom must be substantially greater than the rate of
`
`Ex. 1007, Page 4
`
`

`

`WO 2008/049019
`
`4
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`PCT/0S2007/081671
`
`growth on the rest of areas, and even more so than in
`
`conventional superfilling of larger interconnects.
`
`[0012]
`
`In addition to superfilling and overplating
`
`issues, micro-defects may form when electrodepositing Cu for
`
`filling interconnect features. One defect that can occur is
`
`the formation of internal voids inside the features. As Cu is
`
`deposited on the feature side walls and top entry of the
`
`feature, deposition on the side walls and entrance to the
`
`feature can pinch off and thereby close access to the depths
`
`of the feature especially with features which are small (e.g.,
`
`<100 nm) and/or which have a high aspect ratio (depth:width)
`
`if the bottom-up growth rate is not fast enough. Smaller
`
`feature size or higher aspect ratio generally requires faster
`
`bottom-up speed to avoid pinching off. Moreover, smaller size
`
`or higher aspect ratio features tend to have thinner seed
`
`coverage on the sidewall and bottom of a via/trench where
`
`voids can also be produced due to insufficient copper growth
`
`in these areas. An internal void can interfere with
`
`electrical connectivity through the feature.
`
`[0013] Microvoids are another type of defect which can
`
`form during or after electrolytic Cu deposition due to uneven
`
`Cu growth or grain recrystallization that happens after Cu
`
`plating.
`
`[0014]
`
`In a different aspect, some local areas of a
`
`semiconductor substrate, typically areas where there is a Cu
`
`seed layer deposited by physical vapor deposition, may not
`
`grow Cu during the electrolytic deposition, resulting in pits
`
`or missing metal defects. These Cu voids are considered to be
`
`"killer defects," as they reduce the yield of semiconductor
`
`manufacturing products. Multiple mechanisms contribute to the
`
`formation of these Cu voids, including the semiconductor
`
`substrate itself. However, Cu electroplating chemistry has
`
`influence on the occurrence and population of these defects.
`
`Ex. 1007, Page 5
`
`

`

`WO 2008/049019
`
`5
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`PCT/0S2007/081671
`
`[0015] Other defects are surface protrusions, which are
`
`isolated deposition peaks occurring at localized high current
`
`density sites, localized impurity sites, or otherwise. Copper
`
`plating chemistry has influence on the occurrence of such
`
`protrusion defects. Although not considered as defects, Cu
`
`surface roughness is also important for semiconductor wafer
`
`manufacturing. Generally, a bright Cu surface is desired as
`
`it can reduce the swirl patterns formed during wafer entry in
`
`the plating solution. Roughness of Cu deposits makes it more
`
`difficult to detect defects by inspection, as defects may be
`
`concealed by peaks and valleys of rough surface topography.
`
`Moreover, smooth growth of Cu is becoming more important for
`
`flawlessly filling of fine interconnect structures as the
`
`roughness can cause pinch off of feature and thereby close
`
`access to the depths of the feature.
`
`It is generally
`
`recognized that Cu electroplating chemistry, including
`
`suppressor, accelerator, and leveler, has great influence on
`
`the roughness of Cu deposits, thus presenting challenges in
`
`chemistry formulation.
`
`SUMMARY OF THE INVENTION
`
`[0016] It is an object of the invention, therefore, to
`
`simplify deposition of copper into electrical interconnects,
`
`improve the quality of such copper deposition, and avoid
`
`certain of the challenges associated with electrolytic
`
`deposition of copper in this context.
`
`[0017] Briefly, therefore, the invention is directed to a
`
`method for plating Cu onto a semiconductor integrated circuit
`
`device substrate having an electrical interconnect feature
`
`having a bottom, sidewalls, and top opening in a dielectric
`
`material, the method comprising forming an initial metal
`
`deposit in the feature which has a profile comprising copper
`
`metal on the bottom of the feature and a segment of the
`
`sidewalls having essentially no copper metal thereon; and
`
`Ex. 1007, Page 6
`
`

`

`WO 2008/049019
`
`6
`
`PCT/0S2007/081671
`
`depositing copper onto the initial metal deposit to fill the
`
`feature with copper.
`
`[0018] Other objects and features of the invention will
`
`be in part apparent and in part pointed out hereinafter.
`
`BRIEF DESCRIPTION OF THE FIGURES
`
`[0019] FIGS.
`
`lA through lE are a schematic illustration
`
`of one distinct embodiments of the invention.
`
`[0020] FIGS. 2A through 2E are a schematic illustration
`
`of one distinct embodiments of the invention.
`
`[0021] FIGS. 3A through 3D are a schematic illustration
`
`of one distinct embodiments of the invention.
`
`[0022] FIGS. 4A through 4D are a schematic illustration
`
`of one distinct embodiments of the invention.
`
`[0023] FIGS. SA through SD are a schematic illustration
`
`of one distinct embodiments of the invention.
`
`[0024] FIG. 6 is a SEM image of a seeded test trench
`
`structure that has continuous copper seed coverage on a Ru/Ta
`
`barrier stack.
`
`[0025] FIG. 7 is a SEM image showing the same test
`
`trenches partially filled by electrolytic damascene plating
`
`process.
`
`[0026] FIG. 8 is a SEM image of the same test trenches
`
`wherein copper on feature sidewalls and top-field is removed
`
`by chemical etching.
`
`[0027] FIG. 9 is a SEM image showing the same test
`
`trenches filled by bottom-up electroless copper deposition.
`
`DETAILED DESCRIPTION OF THE EMBODIMENT(S) OF THE INVENTION
`
`[0028] The present invention is directed to a method of
`
`metallizing an interconnect feature located in a
`
`microelectronic device substrate. The interconnect feature is
`
`a trench or via located in a semiconductor substrate and has a
`
`bottom, a sidewall, and an opening. Typical dimensions of the
`
`Ex. 1007, Page 7
`
`

`

`WO 2008/049019
`
`7
`
`PCT/0S2007/081671
`
`opening, i.e., diameter of a via opening (commonly referred to
`
`as a node) or width of a trench, are typically less than about
`
`500 nm, but more typically nodes are less than about 250 nm
`
`and may be as little as about 10 nm, i.e., the opening
`
`dimension is typically between about 10 nm and about 500 nm.
`
`Common nodes include 130 nm, 90 nm, 65 nm, 45 nm, 32 nm, 22
`
`nm, and 15 nm. Typical depths may range from about 2000 nm to
`
`about 200 nm, such as about 1000 nm, about 700 nm, about 500
`
`nm, or about 300 nm.
`
`In view of these diameters and depths,
`
`interconnect features may be characterized as having aspect
`
`ratios in terms of depth:opening diameter between about 20:1
`
`and about 0.2:1, typically between about 10:1 and about 1:1,
`
`such as about 7:1, about 5:1, and about 3:1.
`
`[0029] These features are located in a dielectric layer,
`
`the dielectric layer located on a semiconductor substrate.
`
`The semiconductor substrate may be, for example, a
`
`semiconductor wafer or chip. The semiconductor substrate is
`
`typically a silicon wafer or silicon chip, although other
`
`semiconductor materials, such as germanium, silicon germanium,
`
`silicon carbide, silicon germanium carbide, and gallium
`
`arsenide are applicable to the method of the present
`
`invention.
`
`[0030] The semiconductor substrate may have deposited
`
`thereon a dielectric (insulative) layer, such as, for example,
`SiO 2
`oxides, or low-K dielectrics. The dielectric film is
`
`, silicon nitride, silicon oxynitride, carbon-doped silicon
`
`typically deposited by conventional methods on the surface of
`
`the semiconductor wafer or chip and then the top-field surface
`
`of the dielectric layer is etched, by conventional
`
`lithography, to achieve the circuitry pattern comprising the
`
`aforementioned vias and trenches. Low-K dielectric refers to
`
`a material having a smaller dielectric constant than silicon
`
`dioxide (dielectric constant= 3.9). Low-K dielectric
`
`materials are desirable since such materials exhibit reduced
`
`Ex. 1007, Page 8
`
`

`

`WO 2008/049019
`
`8
`
`PCT/0S2007/081671
`
`parasitic capacitance compared to the same thickness of Si0 2
`dielectric, enabling increased feature density, faster
`
`switching speeds, and lower heat dissipation. Low-K
`
`dielectric materials can be categorized by type (silicates,
`
`fluorosilicates and organo-silicates, organic polymeric etc.)
`
`and by deposition technique (CVD; spin-on). Dielectric
`
`constant reduction may be achieved by reducing polarizability,
`
`by reducing density, or by introducing porosity.
`
`[0031] Prior to copper metallization, a barrier layer is
`
`deposited onto the bottoms and sidewalls of interconnect
`
`features located in the substrate's dielectric layer. Barrier
`
`layer materials may be selected from among tantalum, tantalum
`
`nitrogen composite, titanium, titanium nitrogen composite,
`
`tungsten, tungsten nitrogen composite, titanium silicon
`
`nitride, and manganese oxide, among others. The barrier layer
`
`may comprise one or more than one layer comprising the above(cid:173)
`
`described materials, such as a layer of tantalum and a layer
`
`of tantalum-nitride composite, in one example. For 32nm
`
`generation node or below, a ruthenium layer may be applied on
`
`top of the barrier to allow for direct copper plating without
`
`copper seeds or with reduced amount of copper seeds. The
`
`ruthenium layer also promotes the adhesion between the barrier
`
`layer and copper metallization and thus it is often called a
`
`"glue layer". Barrier layers comprising these materials are
`
`known for effectively blocking copper diffusion into the
`
`semiconductor's junctions and thereby maintain the integrity
`
`of the copper fill.
`
`[0032] These diffusion barriers, the glue layer, and
`
`copper seeding may be deposited onto the bottom and sidewalls
`
`of the interconnect feature by methods known in the art, such
`
`as physical vapor deposition (PVD), plasma-enhanced physical
`
`vapor deposition (PE-PVD), chemical vapor deposition (CVD),
`
`plasma-enhanced chemical vapor deposition (PE-CVD), and atomic
`
`layer deposition (ALD). The diffusion barrier layer is
`
`Ex. 1007, Page 9
`
`

`

`WO 2008/049019
`
`9
`
`PCT/0S2007/081671
`
`typically deposited to a thickness between about 50 nm and
`
`about 5 nm, more typically deposited to a thickness between
`
`about 25 nm and about 15 nm.
`
`[0033] Copper seeding may be by conventional methods,
`
`such as chemical vapor deposition and physical vapor
`
`deposition. Copper seeding by CVD and PVD is typically non(cid:173)
`
`selective, such that copper is additionally deposited on the
`
`top-field surface of the dielectric film.
`
`In a typical
`
`seeding operation, conditions are generally controlled so as
`
`to deposit a copper seed having a thickness about 150 nm on
`
`the bottom and sidewall of the feature, while the thickness of
`
`the copper seed is generally about 30 nm on the top-field
`
`surface of the dielectric. However, the thickness of the
`
`copper seed inside the features can be much thinner than that
`
`on the field. In some extreme cases, the coverage on feature
`
`bottoms approaches zero and copper seeds become non-continuous
`
`there.
`
`[0034]
`
`In the method of the present invention, bottom-up
`
`filling of trench/via structures in microelectronic devices
`
`occurs by an electroless copper deposition process, by an
`
`electrolytic copper deposition process, or by a combination of
`
`electroless and electrolytic copper deposition processes.
`
`In
`
`one preferred embodiment, the invention employs electrolytic
`
`copper deposition, followed by removal of copper deposits from
`
`feature sidewall, followed by electroless copper deposition to
`
`bottom-up fill interconnect features.
`
`In one embodiment, the
`
`invention employs a copper seeded substrate and involves at
`
`least partial removal of the seeding from the feature sidewall
`
`followed by electroless and/or electrolytic copper deposition.
`
`In one embodiment, the invention employs electrolytic copper
`
`deposition followed by electroless copper deposition to
`
`bottom-up fill interconnect features.
`
`[0035] The process steps for one embodiment of the
`
`invention are illustrated in FIGS.
`
`lA through lE. FIG.
`
`lA
`
`Ex. 1007, Page 10
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`

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`WO 2008/049019
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`10
`
`PCT/0S2007/081671
`
`depicts a metal seeded semiconductor interconnect substrate 1
`
`such as copper seed 12 located on the bottom and sidewall of
`
`an interconnect feature and on the top-field surface of the
`
`dielectric layer 10.
`
`In all these images, the substrate is
`
`depicted in cross section. The cross section is a thin slice
`
`of the substrate such that the back sides of the features are
`
`not shown. Moreover, for the sake of clarity, certain
`
`features, such as the semiconductor substrate and the barrier
`
`layer, are not shown, but it should be understood that these
`
`features are part of the semiconductor interconnect substrate.
`
`With reference now to FIG. lB, in this process embodiment,
`
`copper is deposited electrolytically to yield a partially
`
`filled feature, wherein there is copper metallization located
`
`in the bottom, on the side walls 14, and on the top of the
`
`substrate. Preferably, conditions are optimized to deposit
`
`more copper on the bottom of the feature than on the sidewall
`
`of the feature and top-field surface.
`
`In a variation on this
`
`process embodiment, the interconnect feature may be partially
`
`filled by electroless copper deposition to yield the partially
`
`filled feature shown in FIG. lB. Copper is then removed from
`
`the side wall and top field by anodic dissolution or chemical
`
`etching to yield a partially etched feature, as shown in FIG.
`
`lC, wherein, preferably, the copper metal is located
`
`predominantly on the bottom of the feature. Electroless
`
`copper deposition is then used for bottom-up copper filling to
`
`yield the filled interconnect feature having some overgrowth,
`
`as shown in FIG. lD. Because the selected electroless process
`
`by its nature does not deposit copper onto dielectric, copper
`
`does not grow from the sidewalls or from the top-field, such
`
`that many of the issues of pinching and voiding from Cu growth
`
`in non-vertical directions are avoided.
`
`In a variation on
`
`this process embodiment, the interconnect feature may be
`
`filled by electrolytic copper deposition to yield the filled
`
`feature shown in FIG. lD. Then the workpiece is subjected to
`
`Ex. 1007, Page 11
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`

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`
`11
`
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`
`conventional finishing operations of annealing and chemical(cid:173)
`
`mechanical polishing (CMP)
`
`to yield a metallized interconnect
`
`feature in which the copper metallization is planar with the
`
`field of the dielectric, as shown in FIG. lE.
`
`[0036] The manner of deposition of the initial
`
`electrolytic copper partial fill is not critical to the
`
`performance of the invention. Conventional electrolytic
`
`copper chemistry such as ViaForm® available from Enthone Inc.
`
`of West Haven, CT may be employed and prepared according to
`
`the manufacturer's instructions. The chemistry and process
`
`parameters are, for example, akin to those disclosed in U.S.
`
`Pub. Nos. 2005/0045488; 2006/0141784; and 2007/0178697, the
`
`entire disclosures of which are incorporated by reference.
`
`Electrolytic copper deposition for filling interconnect
`
`features generally employs the three-additive system of
`
`leveler, suppressor, and accelerator. Levelers include, for
`
`example, those available from Enthone Inc. under the trade
`
`name ViaForm L700 or ViaForm NEXT(tm) Leveler. The leveler is
`
`incorporated, for example, in a concentration between about
`
`0.1 mg/Land about 25 mg/L. Accelerators are bath soluble
`
`organic divalent sulfur compounds as disclosed in U.S. Pat.
`
`6,776,893, the entire disclosure of which is expressly
`
`incorporated by reference. An example of a suitable
`
`accelerator is ViaForm Accelerator also available from Enthone
`
`Inc. The accelerator is incorporated typically in a
`
`concentration between about 0.5 and about 1000 mg/L, more
`
`typically between about 2 and about 50 mg/L, such as between
`
`about 5 and 30 mg/L. Suppressors typically comprise a
`
`polyether group covalently bonded to a base moiety. One class
`
`of applicable suppressors comprises a polyether group
`
`covalently bonded to an amine moiety. Exemplary suppressors
`
`include ViaForm Suppressor or ViaForm Extreme Suppressor.
`
`These suppressor compounds described above can be present in
`
`Ex. 1007, Page 12
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`WO 2008/049019
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`12
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`PCT/0S2007/081671
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`an overall bath concentration between about 10 mg/L to about
`
`1000 mg/L, preferably between about 50 mg/L to about 200 mg/L.
`
`[0037] A wide variety of copper sources and acids are
`
`potentially applicable, with copper sulfate/sulfuric acid and
`
`copper methanesulfonate/methanesulfonic acid systems currently
`
`preferred.
`
`In embodiments wherein the copper source is a
`
`sulfate-based source, the concentration of copper typically
`
`ranges from about 5 g/L to about 75 g/L, such as between about
`
`5 g/L and about 30 g/L or between about 30 g/L and about 75
`
`g/L. Copper methanesulfonate is a more soluble source of
`
`copper, and the copper concentration may range more widely,
`
`such as from about 5 g/L to about 135 g/L, such as between
`
`about 75 g/L and about 135 g/L copper.
`
`[0038] Chloride ion may also be used in the bath at a
`
`level up to 200 mg/L, preferably about 10 to 90 mg/L.
`
`Chloride ion is added in these concentration ranges to enhance
`
`the function of other bath additives. Other additives
`
`(usually organic additives) may be employed for grain
`
`refinement, suppression of dendritic growth, and improved
`
`covering and throwing power. Typical additives used in
`
`electrolytic plating are discussed in a number of references
`
`including Modern Electroplating, edited by F. A. Lowenheim,
`
`John Reily & Sons, Inc., 1974, pages 183-203.
`
`[0039] Electrolysis conditions such as electric current
`
`concentration, applied voltage, electric current density, and
`
`electrolytic solution temperature are essentially the same as
`
`those in conventional electrolytic copper plating methods.
`
`For example, the bath temperature is typically about room
`
`temperature such as about 20-27°C, but may be at elevated
`
`temperatures up to about 40°C or higher. An external source
`
`of electrons is applied to yield an electrical current density
`
`2
`typically up to about 100 mA/cm, typically between about 2
`2
`2
`mA/cm to about 60 mA/cm .
`
`It is preferred to use an anode to
`
`cathode ratio of about 1:1, but this may also vary widely from
`
`Ex. 1007, Page 13
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`WO 2008/049019
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`13
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`PCT/0S2007/081671
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`about 1:4 to 4:1. The process also uses mixing in the
`
`electrolytic plating tank which may be supplied by agitation
`
`or preferably by the circulating flow of recycle electrolytic
`
`solution through the tank. The flow through the electrolytic
`
`plating tank provides a typical residence time of electrolytic
`
`solution in the tank of less than about 1 minute, more
`
`typically less than 30 seconds, e.g., 10-20 seconds.
`
`[0040] Since, in one embodiment of the invention,
`
`electrolytic copper deposition may be utilized to partially
`
`fill the interconnect feature, the duration and current
`
`density are controlled to prevent full electrolytic fill. For
`
`example, in partially filling an interconnect trenches having
`
`an opening width of 140 nm and a depth of 600 nm (aspect ratio
`
`= 4:1), employing a conventional electrolytic copper
`
`deposition chemistry at a current density of about 100 A/dm2
`
`for between about 15 seconds and about 30 seconds, may be
`
`expected to fill about 30% and about 80% of the volume of the
`
`feature. Stated another way, the conditions are generally
`
`controlled to yield a partially filled interconnect feature in
`
`which the thickness of the copper deposit on the bottom
`
`typically between about 50 nm and about 600 nm, while the
`
`thickness of the copper seed is generally between about 50 nm
`
`and about 1 nm on the sidewalls of the feature. Conditions,
`
`i.e., current density and plating chemistry, are preferably
`
`optimized to deposit copper according to a bottom-up growth
`
`mechanism, such that copper deposits preferably on the bottom
`
`of the feature as opposed to the feature sidewall.
`
`[0041] As stated above, anodic dissolution or chemical
`
`etching may be employed to remove from the plane of the wafer
`
`and on the feature sidewall to yield a partially filled
`
`feature as shown in FIG. lC, in which copper remains
`
`essentially on the bottom of the feature only, while the
`
`sidewalls are essentially free of copper deposit. Chemical
`
`etching involves contacting the partially filled interconnect
`
`Ex. 1007, Page 14
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`WO 2008/049019
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`14
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`PCT/0S2007/081671
`
`feature with a conventional corrosive, etching solution. This
`
`results in dissolution of copper from the top-field surface,
`
`sidewall of the feature, and bottom of the feature. The
`
`dissolution is stopped once all copper is removed from the
`
`sidewalls. Since the copper thickness on the sidewall is much
`
`less than on the bottom, the exposure duration may be
`
`controlled to leave copper on the bottom as shown in FIG. lC.
`
`[0042] Such contact may be by immersion, spraying,
`
`flooding, etc., with the proviso that the contact method is
`
`sufficient to etch copper from the feature sidewall. There is
`
`a wide selection of chemicals that can be used for copper
`
`removal, such as many kinds of acids, oxidizers, alkaline
`
`solution, carbonates, etc. The process parameters are best
`
`determined empirically, such that actual values necessary to
`
`achieve sufficient copper deposition on the bottom of the
`
`feature and copper cleaning from the sidewalls may vary from
`
`those exemplified herein.
`
`[0043] Alternatively, copper may be removed from the
`
`wafer plane and sidewall by anodic dissolution involving
`
`reversing the polarization so as to make the substrate the
`
`anode. This results in dissolution of Cu from top, sidewalls,
`
`and bottom. The dissolution is stopped once a substantial
`
`portion of copper is removed from the sidewalls. Since the
`
`copper thickness on the sidewalls is greater than on the
`
`bottom in the second image, stopping the dissolution at this
`
`point leaves copper on the bottom as shown in FIG. lC.
`
`In one
`
`example, anodic dissolution at a reverse current density
`between about 500 A/dm2 and about 100 A/dm2 may be expected to
`
`remove copper (by oxidation) at a rate of about 185
`
`angstroms/second and about 37 angstroms/second. Generally,
`
`the conditions used for electrolytic copper metallization
`
`sufficient to achieve an acceptable copper deposit on the
`
`bottom and sidewalls of the feature and chemical etching or
`
`anodic dissolution of copper on the sidewalls of the feature
`
`Ex. 1007, Page 15
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`15
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`PCT/0S2007/081671
`
`are best determined empirically, taking into account factors
`
`such as feature diameter and depth, the rate of copper
`
`metallization, and the rate of copper dissolution. The
`
`numbers provided above are exemplary, and it should be
`
`understood that actual values of current density, etc., will
`
`depend upon the above-described process parameters.
`
`[0044]
`
`In either embodiment, it is preferred that
`
`electrolytic copper deposition on the bottom of the feature
`
`fills between about 5% and about 100% of the feature depth,
`
`more preferably