(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2008/0137753 A1
`(43) Pub. Date:
`Jun. 12, 2008
`He
`
`US 20080 137753A1
`
`(54) SYSTEMAND METHOD OF DETERMINING
`DEBLOCKING CONTROL FLAG OF
`SCALABLEVIDEO SYSTEM FOR
`INDICATING PRESENTATION OF
`DEBLOCKING PARAMETERS FOR
`MULTIPLE LAYERS
`
`(75) Inventor:
`
`Zhongli He, Austin, TX (US)
`
`Correspondence Address:
`THE LAW OFFICES OF GARY R. STANFORD
`33OW. OVERLOOK MOUNTAIN RD.
`BUDA, TX 78610
`
`(73) Assignee:
`
`FREESCALE
`SEMICONDUCTOR, INC.,
`Austin, TX (US)
`
`(21) Appl. No.:
`
`11/608,690
`
`(22) Filed:
`
`Dec. 8, 2006
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`H04N 7/24
`(52) U.S. Cl. ............................ 375/240.24; 375/E07.004
`(57)
`ABSTRACT
`A method of generating a video sequence including setting a
`state of a deblocking control flag in a frame header of a frame
`to indicate that a deblocking parameter is presented for some
`but not all layers. A method of processing a received video
`sequence including determining a state of a deblocking con
`trol flag of a frame header and retrieving a deblocking param
`eter for some but not all layers. A scalable video system
`including a deblocking control circuit which sets a state of a
`deblocking control flag in a frame header to indicate that a
`deblocking parameter is presented for some but not all layers.
`A scalable video system including a deblocking control cir
`cuit which determines the state of a deblocking control flag in
`a frame header of a received video sequence and which
`retrieves a deblocking parameter for some but not all layers of
`the frame.
`
`125
`
`OUTPUT
`
`PWR
`
`
`
`els.
`
`
`
`MODE
`DECISION
`
`INTRAFRAME
`PREDICTION
`
`
`
`135
`
`MW
`PSF
`MINSAD
`URF
`
`
`
`
`
`
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`|
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`
`
`
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`RF
`(RECONSTRUCTED)
`
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`D
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`13
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`1
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`SAMSUNG-1008
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`

`

`Patent Application Publication
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`Jun. 12,2008 Sheet 1 of 7
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`US 2008/0137753 Al
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`Patent Application Publication
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`Jun. 12, 2008 Sheet 2 of 7
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`US 2008/O137753 A1
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`Patent Application Publication
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`Jun. 12, 2008 Sheet 3 of 7
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`US 2008/O137753 A1
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`
`AVG.. 4
`
`
`
`409
`PSF AND L/C
`
`
`
`TH = MINSADAVG THC1s (PSF/4+1
`TH2 = MINSADAVG THL (PSF/4+1
`
`TH1 = MINSADAVG THC2
`TH2 = MINSADAVG THL2
`
`419
`
`MNSADAWG >
`TH1?
`421-
`)
`MINSADAWG K p-1
`
`
`
`
`
`DISABLE
`DEBLOCKING FILTER
`(LUMA AND CHROMA)
`
`DISABLE CHROMA
`DEBLOCKING FILTER
`(LUMA ENABLED)
`
`ENABLE DEBLOCKINC - 431
`FILTER (LUMA
`AND CHROMA)
`
`435
`
`
`
`END OF
`SEQUENCE?
`
`
`
`
`
`4
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 4 of 7
`
`US 2008/0137753 A1
`
`
`
`503
`
`SWC WIDEO ENCODER
`601
`MINSAD, MV
`
`EFC
`
`CHANNEL
`602
`
`SVC VIDEO DECODER
`603
`
`OUTPUT
`VIDEO
`
`5
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 5 of 7
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`US 2008/0137753 A1
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`
`
`|
`0
`8
`
`6
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 6 of 7
`
`US 2008/0137753 A1
`
`INITIALIZATION
`BEGIN NEXT FRAME
`QL = 0;
`GO TO NEXT SLICE GROUP
`OF CURRENT FRAME
`
`(C)
`905
`(B)
`
`Q AVG. 9
`9 27
`Stated Y
`903
`N
`SE
`O
`N
`931
`DETERMINEX USING OL
`DETERMINE X USING OL
`
`E.G.,
`X=A FOR QL=1;
`X=B FOR QL=2;
`ETC.
`
`Y
`
`933
`
`
`
`
`
`
`
`
`
`919
`
`ENABLE
`DEBLOCK
`FILTERING
`
`MSTH = Xi QL:TH
`935
`CINSADAVGNY
`909
`s32 > MSTH
`N
`11
`APPLY BASE LAYER
`SET IDCO = 1
`DEBLOCK FILTER
`DETERMINATION SET IDCO
`915
`Sid 9 39
`95
`cope on Ayer slice of
`CURRENT SLICE GROUP
`941
`Sgt. EdFRAME?
`Y
`GO TO NEXT FRAME
`9
`953
`DETERMINE PMINSADAWG AS AVERACE
`OF CMINSADAVG OF LAST FRAME, IF
`LAST FRAME WAS I-FRAME, USE
`DEFAULT WALUE
`
`DISABLE DEBLOCK
`FILTERING
`
`
`
`
`
`ENABLE
`DEBLOCK
`FILTERING
`
`N
`
`949
`
`51
`9
`
`FILTERING
`
`917
`CODE BASE LAYER SLICE OF
`CURRENT SLICE GROUP, IF NOT
`I-FRAME DETERMINE CMINSADAVG
`
`921
`
`ANOTHER
`LAYER
`Y
`
`947
`ANOTHER
`SLICE GROUP
`Y
`
`N
`
`923
`
`
`
`N
`
`FLAG = 3
`
`Y
`
`955
`OVERRIDE?
`
`INCREMENT QL
`GO TO SLICE LAYER QL-925
`OF CURRENT SLICE GROUP
`OF CURRENT SLICE
`G.)
`
`(C)
`
`(B) s 959
`PMINSADAVG
`FLAG = 1
`t
`K TH
`963
`965
`N
`PMINSADAWG
`Y
`FLAG = 2 SE
`FLAG = 0
`N
`
`7
`
`

`

`Patent Application Publication
`
`Jun. 12, 2008 Sheet 7 of 7
`
`US 2008/0137753 A1
`
`START
`
`INITIALIZATION
`
`1001
`
`A77G. ZO
`
`1003 NRETRIEVE SEQUENCE HEADER
`
`BEGIN NEXT FRAME
`
`1005
`
`(C)
`
`1006
`
`1007
`(B)
`
`RETRIEVE FRAME HEADER
`INCLUDING FLAG
`
`QL = 0;
`CO TO NEXT SLICE GROUP
`OF CURRENT FRAME
`1009
`Y SSR.Ed
`
`
`
`
`
`1011 sid 1013
`
`RETRIEVE QL LAYER
`DEBLOCK PARAMETER
`IDCO
`
`
`
`1041
`
`
`
`RETRIEVE BASE LAYER
`N
`1021
`DEBLOCK PARAMETER IDC
`DISABLE DEBLOCK
`FILTERING
`ENABLE
`1015
`DEBLOCK Stop- 1037
`FILTERING
`1017
`DECODE QL LAYER SLICE
`DISABLE DEBLOCK FILTERING
`OF CURRENT SLICE GROUP
`1019
`1039
`DECODE BASE LAYER SLICE OF
`CURRENT SLICE CROUP
`
`
`
`ENABLE
`DEBLOCK
`FILTERING
`
`1023
`
`ANOTHER
`LAYER
`Y
`INCREMENT QL
`
`N
`
`1025
`
`1045
`
`ANOTHER
`SLICE GROUP
`Y
`(B)
`
`GO TO SLICE LAYER QL-1027
`(A)-OFCURRENTSICE GROUP
`OF CURRENT FRAME
`
`N
`
`ANOTHER
`FRAME?
`Y
`GO
`
`104.7
`
`N
`
`END
`
`8
`
`

`

`US 2008/O 137753 A1
`
`Jun. 12, 2008
`
`SYSTEMAND METHOD OF DETERMINING
`DEBLOCKING CONTROL FLAG OF
`SCALABLEVIDEO SYSTEM FOR
`INDICATING PRESENTATION OF
`DEBLOCKING PARAMETERS FOR
`MULTIPLE LAYERS
`
`BACKGROUND OF THE INVENTION
`1. Field of the Invention
`0001
`0002 The present invention relates in general to video
`information processing, and more specifically to a system and
`method of determining a deblocking control flag of Scalable
`Video system for indicating presentation of deblocking
`parameters for multiple layers for reducing bits in the bit
`Stream.
`0003 2. Description of the Related Art
`0004. The Advanced Video Coding (AVC) standard, Part
`10 of MPEG4 (Motion Picture Experts Group), otherwise
`known as H.264, includes advanced compression techniques
`that were developed to enable transmission of video signals at
`a lower bit rate or storage of video signals using less storage
`space. The newer standard outperforms video compression
`techniques of prior standards in order to Support higher qual
`ity streaming video at lower bit-rates and to enable internet
`based video and wireless applications and the like. The stan
`dard does not define the CODEC (encoder/decoder pair) but
`instead defines the syntax of the encoded video bitstream
`along with a method of decoding the bitstream. Each video
`frame is subdivided and encoded at the macroblock (MB)
`level, where each MB is a 16x16 block of pixels. Each MB is
`encoded in intraframe mode in which a prediction MB is
`formed based on reconstructed MBs in the current frame, or
`interframe mode in which a prediction MB is formed based
`on the MBs of the reference frames. The intraframe coding
`mode applies spatial information within the current frame in
`which the prediction MB is formed from samples in the
`current frame that have previously encoded, decoded and
`reconstructed. The interframe coding mode utilizes temporal
`information from previous and/or future reference frames to
`estimate motion to form the prediction MB. The video infor
`mation is typically processed and transmitted in slices, in
`which each video slice incorporates one or more macrob
`locks.
`0005 Scalable Video Coding (SVC) is an extension of the
`H.264 standard which addresses coding schemes for reliably
`delivery of video to diverse clients over heterogeneous net
`works using available system resources, particularly in sce
`narios where the downstream client capabilities, system
`resources, and network conditions are not known in advance,
`or dynamically changing from time to time. SVC provides
`multiple levels or layers of scalability including temporal
`Scalability, spatial scalability, complexity Scalability and
`quality Scalability. Temporal scalability generally refers to
`the number of frames per second (fps) of the video stream,
`such as 7.5fps, 15fps, 30fps, etc. Spatial scalability refers to
`the resolution of each frame. Such as common interface for
`mat (CIF) with 352 by 288 pixels per frame, or quarter CIF
`(QCIF) with 176 by 144 pixels per frame, although other
`spatial resolutions are contemplated, such as 4CIF, QVGA,
`VGA, SVGA, D1, HDTV, etc. Complexity scalability gener
`ally refers to the various computational capabilities and pro
`cessing power of the devices processing the video informa
`tion. Quality Scalability generally refers to the visual quality
`layers of the coded video by using different bitrates. Objec
`
`tively, visual quality is measured with a peak signal-to-noise
`(PSNR) metric defining the relative quality of a reconstructed
`image compared with an original image.
`0006. A deblocking filter is a formative part of the H.264
`standard and SVC extension, and an informative part (as a
`post processing block) of the earlier H.263 standard and
`MPEG4-Part2. The deblocking filter performs both luma and
`chroma filtering as known by those of ordinary skill in the art.
`The deblocking filter is used either as an in-loop filter as part
`of the standard (e.g., H.264/AVC), or as a post-processor for
`video decoder (e.g., H.263, MPEG4-part2, MPEG-2, etc.).
`The deblocking filter enhances the decoded picture quality
`and increases the encoding efficiency by removing the block
`effects in the boundary of each 4x4, 8x8, and/or 16x16
`block. The deblocking filter, however, also consumes a sig
`nificant amount of power and processing cycles. Generally
`speaking, the entire deblocking filter (both luma and chroma)
`consumes approximately 8% of the computations at the
`encoder and approximately 35% at the decoder for H.264/
`AVC. Disabling the entire deblocking filter, therefore, pro
`vides a significant reduction of power and processing com
`plexity, especially in the decoder. A conventional
`configuration according to H.264/AVC includes the ability to
`turn on and off the entire deblocking filter (including both
`luma and chroma deblock filtering). Disabling the entire
`deblocking filter, however, potentially causes degradation of
`both objective PSNR and subjective visual quality especially
`for video information having a relatively high level of motion.
`In most conventional configurations, therefore, the ability to
`completely disable the deblocking filter has not been used.
`0007. The bitstream carrying the video sequence gener
`ated and transmitted by an SVC video encoder is organized
`into multiple frames in which each frame includes multiple
`slices. Each frame header includes a frame header and the
`slices of the frame include base layer slices and enhanced
`layer slices, where each slice includes a slice header. The
`frame header includes a deblocking control flag indicating
`whether deblocking parameters are presented within the slice
`headers of the base layer slices and the enhanced layer slices.
`The deblocking parameters determine whether deblock filter
`ing is enabled or disabled and additional deblocking settings
`when enabled. A deblocking enable/disable parameter is set
`to “0” to enable deblock filtering and to “1” to disable deblock
`filtering.
`0008. In conventional SVC configurations, the deblocking
`control flag is limited to the values “0” and “1”, in which “0”
`indicates that deblocking parameters are not presented for
`any layers and “1” in which deblocking parameters are pre
`sented for all layers. If the deblocking control flag is “1”, then
`deblock filtering may be disabled for the base layer (by setting
`the deblocking enable/disable parameter for the base layer to
`“1”) or may be disabled for the enhanced layers to reduce
`processing cycles and/or power consumption. If deblock fil
`tering is not needed for the base layer but is needed for the
`enhanced layer or if needed at the base layer but not the
`enhanced layers, then the deblocking control flag must be set
`to “1” at the expense of additional bits in the bitstream. The
`additional bits for the deblocking parameters had to be pre
`sented even if deblocking is not to be disabled and could
`otherwise be set to the default value of “0”. The deblocking
`control flag could be set to “0” to reduce the bits in the
`bitstream since the deblocking parameters are not presented
`in the slice headers, yet this is at the expense of additional
`
`9
`
`

`

`US 2008/O 137753 A1
`
`Jun. 12, 2008
`
`processing cycles and/or power consumption required for
`deblock filtering. The conventional syntax thus wastes bits in
`the bitstream.
`0009. It is desired to reduce the number of bits in the
`bitstream by allowing the encoder designer the option of not
`having to present deblocking parameters for either the base
`layer slices or the enhanced layer slices while disabling
`deblock filtering of at least one layer.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`0010. The benefits, features, and advantages of the present
`invention will become better understood with regard to the
`following description, and accompanying drawings where:
`0011
`FIG. 1 is a block diagram of a video encoder imple
`mented according to an exemplary embodiment for generat
`ing and transmitting video information in a bitstream (BTS);
`0012 FIG. 2 is a block diagram of a video decoder imple
`mented according to an exemplary embodiment for receiving
`and decoding video information incorporated into a bitstream
`BTS:
`0013 FIG.3 is a simplified block diagram of a deblocking
`filter that may be used as either or both of the deblocking
`filters of the encoder of FIG. 1 and/or the decoder of FIG. 2;
`0014 FIG. 4 is a flowchart diagram illustrating operation
`of the deblock control circuit of FIG. 1 implemented accord
`ing to an exemplary embodiment for adaptively disabling
`deblock filtering based on content of the video information
`and also based on power savings considerations;
`0015 FIG.5 is a block diagram depicting deblocking filter
`control information provided in the bitstream BTS output
`from the video encoder of FIG. 1 or provided to the video
`decoder of FIG. 2 according to an exemplary embodiment of
`a non-scalable configuration;
`0016 FIG. 6 is a simplified block diagram of an SVC
`Video system implemented according to an exemplary
`embodiment including both an SVC video encoder and
`decoder;
`0017 FIG. 7 is a block diagram depicting deblocking filter
`control information provided in an output bitstream BTS
`from the SVC video encoder of FIG. 6 or provided in an input
`bitstream BTS to the video decoder of FIG. 6 according to an
`exemplary embodiment;
`0018 FIG. 8 is a block diagram depicting deblocking filter
`control information provided in the bitstream BTS substan
`tially identical to that shown in FIG. 7 except illustrating a
`specific case of the deblocking filter control present flag:
`0019 FIG.9 is a flowchart diagram illustrating exemplary
`operation of the SVC video encoder of FIG. 6 while encoding
`each slice layer of each slice group of each frame of a video
`sequence incorporated into the output bitstream OBTS, for
`determining and setting the state of the deblocking filter con
`trol present flag for each video frame, and for setting the IDC
`deblocking disable control parameter for each layer of each
`slice of each frame; and
`0020 FIG. 10 is a flowchart diagram illustrating exem
`plary operation of the SVC video decoder of FIG. 6 for
`decoding each slice layer of each slice group of each frame of
`a video sequence received from the input bitstream IBTS.
`
`DETAILED DESCRIPTION
`0021. The following description is presented to enable one
`of ordinary skill in the art to make and use the present inven
`tion as provided within the context of a particular application
`
`and its requirements. Various modifications to the preferred
`embodiment will, however, be apparent to one skilled in the
`art, and the general principles defined herein may be applied
`to other embodiments. Therefore, the present invention is not
`intended to be limited to the particular embodiments shown
`and described herein, but is to be accorded the widest scope
`consistent with the principles and novel features herein dis
`closed.
`0022. The present disclosure describes video information
`processing systems according to exemplary embodiments of
`the present invention. It is intended, however, that the present
`disclosure apply more generally to any of various types of
`“video information' including video sequences (e.g. MPEG),
`image information, or image sequencing information, Such
`as, for example, JPEG (Joint Photographic Experts Group),
`motion JPEG (MJPEG), JPEG2000, motion JPEG2000
`(MJPEG2000), etc. The term “video information” as used
`herein is intended to apply to any video or image or image
`sequence information.
`(0023 FIG. 1 is a block diagram of a video encoder 100
`implemented according to an exemplary embodiment for
`generating and transmitting video information in a bitstream
`(BTS). A frame buffer 101 provides, for purposes of encod
`ing, current frame information F to one input of a motion
`estimation (ME) circuit 103, to one input of an intraframe
`prediction circuit 105, to a positive input of a combiner 107
`(e.g., adder or Subtractor or the like), to one input of a motion
`compensation (MC) circuit 111, and to an input of a mode
`decision circuit 113. Another frame buffer 109 provides ref
`erence information (REF) to another input of the ME circuit
`103 and to another input of the MC circuit 111. The encoder
`100 is typically configured to process information one mac
`roblock at a time, so that the frame information F is usually
`processed one macroblock at a time, although alternative
`configurations are contemplated. The reference information
`REF includes information from one or more previously
`encoded and decoded frames that have further been filtered,
`such as by a deblocking filter 131.
`0024. The ME circuit 103 provides motion estimation
`information at its output, which is provided to another input
`of the MC circuit 111 and to another input of the mode
`decision circuit 113. As shown, the ME circuit 103 provides
`motion vector (MV) information to the MC circuit 111 and to
`the mode decision circuit 113, and the ME circuit 103 pro
`vides minimum sum of absolute differences (MINSAD)
`information to the mode decision circuit 113. The mode deci
`sion circuit 113 has one output providing an intraframe enable
`signal INTRAE to an enable input of the intraframe predic
`tion circuit 105, and another output providing a motion com
`pensation enable signal MCE to an enable input of the MC
`circuit 111. The MC circuit 111 provides motion compen
`sated prediction information (e.g., interframe prediction) MC
`to a first input terminal S1 of a selector switch 115, illustrated
`as a single-pole, double-throw (SPDT) switch having input
`terminals S1 and S2, control input terminal C and a common
`terminal CP. The common terminal CP provides information
`from a selected input (S1 or S2) as its output as controlled by
`the control input terminal C. The intraframe prediction circuit
`105 provides intraframe prediction information (e.g.,
`intraframe prediction) IP to an input of the mode decision
`circuit 113 and to the input terminal S2 of the switch 115. The
`mode decision circuit 113 provides a mode decision select
`signal MSEL to the control terminal C of the switch 115 for
`
`10
`
`

`

`US 2008/O 137753 A1
`
`Jun. 12, 2008
`
`selecting between the motion compensated prediction infor
`mation MC or the intraframe prediction information IP.
`0025. The CP terminal of the switch 115 provides selected
`prediction information P to a negative input of the combiner
`107 and to a positive input of another combiner 117, which is
`an adder in the illustrated embodiment. The combiner 107
`subtracts the selected prediction information P from the cur
`rent information F of a current frame to provide residual
`information R to the input of a transform circuit 119. The
`transform circuit 119 performs a block transform, such as
`discrete cosine transform (DCT) or the like, and outputs the
`transform result B. The transform result B is provided to a
`quantization (Q) circuit 121, which outputs quantized trans
`form coefficients X. The X coefficients are provided to the
`input of an output processing circuit 125, which provides a
`compressed bitstream (BTS) for transmission or storage. The
`output processing circuit 125 performs additional functions
`for converting the X coefficients into the bitstream BTS, such
`as Scanning, reordering, entropy encoding, etc., as known to
`those skilled in the art.
`0026. The X coefficients are fed back to the input of an
`inverse quantization (Q) circuit 127, which outputs esti
`mated transformed information B' representing an estimated
`or reconstructed version of the transform result B. The esti
`mated transformed information B' is provided to the input of
`an inverse transform (T) circuit 129, which outputs esti
`mated residual information R representing a reconstructed
`version of the residual information R. The reconstructed
`residual information R is provided to another positive input
`of the combiner 117. In the embodiment shown, the combiner
`117 adds P to R' to generate unfiltered reconstructed infor
`mation URF. The unfiltered reconstructed frame information
`URF is provided to another input of the intraframe prediction
`circuit 105 and to an input of the deblocking filter 131. The
`deblocking filter 131, when enabled, filters the unfiltered
`reconstructed frame information URF and provides filtered
`reconstructed information RF to an RF buffer 133. One or two
`previously encoded and decoded frames from the RF buffer
`133 are provided to the frame storage 109 to serve as the
`reference frame information REF as previously described.
`0027. A deblock control circuit 135 provides an encoder
`filter control (EFC) signal to the deblocking filter 131. In one
`embodiment, the deblocking filter 131 is turned completely
`on or completely off (or otherwise fully enabled or disabled)
`by the EFC signal. If the deblocking filter 131 is turned off or
`fully disabled, then the unfiltered reconstructed frame infor
`mation URF is passed as the reconstructed information RF in
`which deblock filtering is bypassed (i.e., RF is the same as
`URF). In another embodiment, the EFC signal is configured
`to partially disable the deblocking filter 131 so that it only
`performs luma or chroma deblock filtering. The EFC signal
`may be a single binary signal or bit if only enabling or dis
`abling luma or chroma deblock filtering. Alternatively, the
`EFC signal includes multiple signals or bits for selecting
`between fully enabled, fully disabled, or for disabling either
`one of luma and chroma deblock filtering.
`0028 Disabling the entire deblocking filter 131 provides a
`significant reduction of computational complexity and power
`consumption, especially in the decoder of a video processing
`system. Disabling the entire deblocking filter, however,
`potentially causes degradation of both objective PSNR and
`subjective visual quality especially for a relatively high level
`of motion in the video information. As described herein, the
`content of the video information is examined to determine
`
`whether to disable the deblock filtering. The content of the
`Video information is examined to determine a characteristic
`indicative of a relative amount of content complexity and/or a
`relative amount of motion of the video information. If the
`video information content exhibits a relatively low amount of
`motion or is relatively simple content (e.g., not complex),
`then the deblocking filter 131 may be fully disabled without
`significant degradation in visual quality. Simulation results
`have revealed that disabling luma deblocking filter alone
`(while enabling the chroma deblocking filter) normally
`causes a relatively large degradation in both objective PSNR
`and Subjective visual quality especially for video with a rela
`tively large level of motion. The luma deblocking filter is
`particularly useful for low bit rate video applications or video
`having a relatively high compression ratio. The simulation
`results have also revealed, however, that disabling the chroma
`deblocking filter alone (while enabling the luma deblocking
`filter) results in a relatively small or negligible degradation in
`both objective and subjective visual quality. In various
`embodiments, the content characteristic is the content com
`plexity or level of motion, which is compared with a threshold
`for enabling or disabling the entire deblocking filter 131. In
`another embodiment, separate thresholds are provided for
`luma and chroma deblock filtering.
`(0029. The ME circuit 103 performs a motion search and
`determines a MINSAD value for each macroblock of each
`slice of the current frame or picture. In particular, the absolute
`values of the differences between each pixel value of the
`current macroblock of the current frame being encoded and
`the corresponding pixel value of a search macroblock in the
`reference frame are added together to determine a corre
`sponding SAD value. This calculation is repeated for each
`reference search macroblock in the search window (accord
`ing to the selected motion search pattern) and the lowest or
`lease SAD value is determined as the minimum SAD or
`MINSAD value. The reference search macroblock corre
`sponding to the MINSAD value is used for determining the
`motion vector (MV) information. Each MINSAD value is
`provided from the ME circuit 103 to the deblock control
`circuit 135 for the purpose of measuring the relative complex
`ity of the video content. As described further below, in one
`embodiment multiple MINSAD values are averaged for
`determining a complexity value or complexity factor of the
`video information. Other methods may be used to determine
`the relative complexity of the content of video information,
`Such as mean square error, a number of bits used for coding
`the video information of a slice/picture, statistics of an indi
`vidual frame or picture, etc. The mean square error may also
`be determined by the ME circuit 103 in which each pixel
`difference is squared and multiple squared values (for each
`macroblock or each slice, etc.) are Summed together. Calcu
`lating each MINSAD value is less computationally complex
`than calculating the mean square error and an average of
`MINSAD values provides a sufficiently accurate measure of
`content complexity. In an alternative embodiment, the
`amount of motion is determined by the motion vectors, which
`are also shown provided to the deblock control circuit 135.
`Although the deblock control circuit 135 may utilize multiple
`content characteristics of the video information, Such as, for
`example, both MV and MINSAD information, usually one
`characteristic is selected for particular configurations to
`reduce computational complexity.
`0030. In one embodiment, the deblock control circuit 135
`determines an average of MINSAD values of a group or block
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`of previously encoded information. The group or block of
`previously encoded information is usually a slice (on or more
`macroblocks) or a frame of encoded information. The deter
`mined average of MINSAD values is referred to as a MIN
`SADAVG value. A relatively small MINSADAVG value sug
`gests less change within a frame or between frames and thus
`Suggests relatively simple video content. On the other hand, a
`relatively high MINSADAVG value suggests relatively com
`plex video content. In certain embodiments, the MINSA
`DAVG value is the average MINSAD value of the previously
`encoded frame. In one embodiment, for example, the deblock
`control circuit 135 maintains a running average of MINSAD
`values for each video frame and stores the average of MIN
`SAD values of the previous frame as the MINSADAVG
`value. In other embodiments, the MINSADAVG value is the
`average MINSAD value of a corresponding video slice within
`the previously encoded frame. A video slice incorporates one
`or more macroblocks, and a "corresponding video slice is
`the video slice of the previous frame that is in the same
`relative position of the current video slice of the frame cur
`rently being encoded. In one embodiment, for example, the
`deblock control circuit 135 maintains a running average of
`MINSAD values for each video slice and stores an average
`MINSAD value for each slice of the previously encoded
`frame to provide multiple MINSADAVG values per video
`frame. In still other embodiments, the MINSADAVG value is
`the average MINSAD value of a previously encoded video
`slice within the current frame. In one embodiment, for
`example, the deblock control circuit 135 maintains a running
`average of MINSAD values for each video slice being
`encoded in the current frame and stores an average of MIN
`SAD values as the MINSADAVG value for the previously
`encoded video slice of the current frame. In this latter
`embodiment, the MINSADAVG value used for the first video
`slice (in which there is no previous slice in the current frame)
`is either the MINSADAVG value of the last encoded video
`slice of the previous frame or the average of MINSAD values
`of the entire previous frame.
`0031. The video encoder 100 includes a power manage
`ment circuit 137, which monitors a variety of power-related
`factors and provides a power saving factor (PSF) based on the
`monitored factors. The monitored factors include, for
`example, power level or available power (e.g., battery level)
`via a power metric PWR, available processing resources via a
`processing metric PROC, a signal strength metric SIG indi
`cating the signal strength of the bitstream BTS transmitted in
`a channel (e.g., see exemplary channel 602 of FIG. 6), and one
`or more user settings collectively indicated by a user metric
`USER. The USER metric may incorporate manual settings or
`adjustments made by the user or other manual or automatic
`power settings. The PSF is provided to the deblock control
`circuit 135. In one embodiment, the deblock control circuit
`135 uses the PSF and the MINSADAVG values to control the
`state of the deblocking filter 131 via the EFC signal as further
`described below. In one embodiment, the PSF signal ranges
`from Zero (0) to sixteen (16), in which PSF-0 indicates maxi
`mum available power and processing resources such that
`Sufficient energy and processing power are deemed to be
`available for full deblock filtering. As PSF increases, it is
`desired to conserve power consumption and processing
`cycles as much as possible. Such as by disabling at least a
`portion of deblock filtering.
`0032 FIG. 2 is a block diagram of a video decoder 200
`implemented according to an exemplary embodiment for
`
`receiving and decoding video information incorporated into a
`bitstream BTS. The video decoder 200 may be implemented
`in a different system (e.g., communicating with the video
`encoder 100) or may be incorporated into the same system as
`the video encoder 100 in which the encoder/decoder combi
`nation is used to communicate with similar type devices
`across the channel. The compressed bitstream BTS generated
`by the video encoder 100 is transmitted through the channel
`and provided to the input of an input processing circuit 201,
`which performs inverse processing functions of the output
`processing circuit 125 of the encoder 100, such as inverse
`scanning, reordering, entropy decoding, etc., as known to
`those skilled in the art. The input processing circuit 201
`outputs quantized transform coefficients X' coefficients,
`which are intended to duplicate the X coefficients of the
`encoder 100. The X coefficients are provided to the input of
`an inverse quantization circuit 203, which outputs estimated
`transformed information B'. The estimated transformed
`information B' is provided to the input of an inverse transform
`circuit 205, which outputs reconstructed residual information
`R" to a positive input of a combiner 207. In the embodiment
`shown, the combiner 207 adds selected prediction informa
`tion P' to R' to generate unfiltered reconstructed information
`URF". The unfiltered reconstructed frame information URF"
`is provided to an input of an intraframe prediction circuit 209
`and to an input of a deblocking filter 211. The deblocking
`filter 211 filters the unfiltered reconstructed frame informa
`tion URF" and provides filtered reconstructed information RF
`to an RF buffer 213.
`0033. One or two previously encoded and decoded (and
`selectively filtered) frames from