Paper No. 1
`
`UNITED STATES PATENT AND TRADEMARK OFFICE
`
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`
`
`
`
`MICRON TECHNOLOGY, INC., MICRON SEMICONDUCTOR PRODUCTS,
`INC., and MICRON TECHNOLOGY TEXAS LLC,
`Petitioners,
`v.
`NETLIST, INC.,
`Patent Owner.
`
`
`Case IPR2024-00370
`
`Patent 10,268,608
`
`Inventors: Hyun Lee and Jayesh R. Bhakta
`
`Title: MEMORY MODULE WITH TIMING-CONTROLLED DATA PATHS IN
`DISTRIBUTED DATA BUFFERS
`
`PETITION FOR INTER PARTES REVIEW OF
`U.S. PATENT NO. 10,268,608
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`I.
`
`TABLE OF CONTENTS
`PETITIONER’S MANDATORY NOTICES ............................................xv
`A.
`Real Party-in-Interest (37 C.F.R. § 42.8(b)(1)) ...................................xv
`B.
`Related Matters (37 C.F.R. § 42.8(b)(2)) ............................................xv
`C.
`Lead and Back-up Counsel (37 C.F.R. § 42.8(b)(3)) ........................ xvi
`D.
`Service Information (37 C.F.R. § 42.8(b)(4)) ................................... xvi
`INTRODUCTION ......................................................................................... 1
`II.
`III. COMPLIANCE WITH IPR REQUIREMENTS ....................................... 1
`A. Grounds for Standing (§42.104(a)) ....................................................... 1
`B.
`Identification of Challenge (§42.104(b)) .............................................. 1
`IV. RELEVANT
`INFORMATION
`CONCERNING
`THE
`CONTESTED PATENT ................................................................................ 1
`A.
`Effective Filing Date ............................................................................. 1
`B.
`Person of Ordinary Skill in the Art (“POSITA”) .................................. 2
`C.
`The ʼ608 Patent ..................................................................................... 2
`1.
`Overview ..................................................................................... 2
`2.
`Prosecution History ..................................................................... 6
`Construction of Claim Terms ................................................................ 7
`D.
`PRIOR ART OVERVIEW ............................................................................ 8
`A. Hiraishi (EX1005) ................................................................................. 8
`B.
`Tokuhiro (EX1006) .............................................................................10
`C.
`Ellsberry (EX1007) ............................................................................. 11
`D.
`Butt (EX1029) .....................................................................................12
`E.
`Kim (EX1008) .....................................................................................13
`VI. PRECISE REASONS FOR RELIEF REQUESTED ...............................13
`A. Ground 1: Hiraishi + Butt (claims 1-12) .............................................14
`
`V.
`
`
`
`i
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`1.
`
`2.
`
`Claim 1 ......................................................................................14
`a)
`1[pre] ...............................................................................14
`b)
`1[a]: module board ..........................................................17
`c)
`1[b]: module control device ............................................19
`d)
`1[c]: memory devices .....................................................25
`e)
`1[d]: buffer circuits .........................................................28
`f)
`1[e]: first wherein clause; module control signals ..........31
`g)
`1[f]: second wherein clause: tristate buffer and
`delay circuit configured to delay a signal .......................39
`Claim 2 ......................................................................................53
`a)
`2[a]: first and second memory operations ......................53
`b)
`2[b]: first and second set of command signals ...............53
`c)
`2[c]: first and second set of control signals ....................54
`d)
`2[d]: signal associated with the second memory
`operation .........................................................................55
`Claim 3 ......................................................................................56
`a)
`3[a]: different ranks ........................................................56
`b)
`3[b]: module command signals ......................................56
`c)
`3[c]: chip select ...............................................................57
`Claim 4: x8 buffers and memory devices .................................58
`Claim 5: x8 buffer; x4 memory devices ...................................59
`Claim 6: metastability detection circuit ....................................60
`Claims 7-8 .................................................................................62
`Claim 9: .....................................................................................63
`a)
`9[a]: clock regeneration circuit .......................................63
`b)
`9[b]: output local clock to memory devices ...................64
`Claim 10: claim 9 + sampler .....................................................66
`9.
`10. Claims 11-12 .............................................................................71
`Ground 2: Ground 1 + Tokuhiro (claims 1-12) ...................................72
`1. Motivations to Combine ...........................................................72
`ii
`
`3.
`
`4.
`5.
`6.
`7.
`8.
`
`B.
`
`
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`a)
`
`b)
`
`First motivation: Tokuhiro teaches calculating read
`delays based on delays for write operations, which
`is more efficient than Hiraishi’s technique of read
`leveling independent of write delays ..............................73
`Second motivation: Tokuhiro provides simple
`techniques for removing fly-by delays, while
`Hiraishi does not disclose how
`its memory
`controller re-times read data received with fly-by
`delays ..............................................................................78
`Third motivation: Tokuhiro discloses simple
`solutions for fly-by delays greater than one clock
`cycle, while Hiraishi does not.........................................79
`The combination of Ground 1 in further view of Tokuhiro
`relied upon here .........................................................................81
`a)
`It would have been obvious
`to
`implement
`Tokuhiro’s delay elements in Hiraishi’s data register
`buffers .............................................................................81
`It would have been obvious for either Hiraishi’s
`memory controller or module controller to program
`Tokuhiro’s delay elements in Hiraishi’s data buffers
` ........................................................................................90
`(1)
`First implementation of the combination
`(system memory controller determines the
`read delay) ............................................................91
`Second implementation of the combination
`(module controller determines the read delay)
` ..............................................................................93
`Claim 1 ......................................................................................97
`Claim 2 ....................................................................................101
`a)
`2[a]: first and second memory operations ....................101
`b)
`2[b]: first and second set of command signals .............102
`c)
`2[c]: first and second set of control signals ..................104
`d)
`2[d]: signal associated with the second memory
`operation .......................................................................106
`Claims 3-12 .............................................................................107
`iii
`
`c)
`
`b)
`
`(2)
`
`2.
`
`3.
`4.
`
`5.
`
`
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`Ground 3: Ground 1 or Ground 2 + Ellsberry (claims 5 and 12) ......107
`C.
`D. Ground 4: Ground 1 or Ground 2 + Kim (claims 6-8) ......................108
`E.
`Ground 5: Ground 1 or 2 + Kim and Ellsberry (claim 8) ................. 110
`VII. DISCRETIONARY DENIAL IS INAPPROPRIATE ............................ 110
`A.
`35 U.S.C. § 325(d)............................................................................. 110
`B.
`35 U.S.C. § 314(a) ............................................................................. 110
`1.
`Fintiv ....................................................................................... 110
`2.
`General Plastic ....................................................................... 111
`VIII. CONCLUSION .......................................................................................... 115
`
`
`
`
`iv
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`

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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`TABLE OF AUTHORITIES
`
` Page(s)
`
`Cases
`Advanced Bionics, LLC v. Med-El Elektromedizinische Geräte GmbH,
`IPR2019-01469, Paper 6 (PTAB Feb. 13, 2020) (precedential) ...................... 110
`Apple Inc. v. Fintiv, Inc.,
`IPR2020-00019, Paper 11 (PTAB Mar. 20, 2020) (precedential) .............. 110-11
`Apple Inc. v. Uniloc 2017 LLC,
`IPR2020-00854, Paper 8 (June 22, 2020), Paper 9 (PTAB Oct. 28,
`2020) (precedential) .................................................................................... 114-15
`CODE200, UAB et al. v. Bright Data LTD.,
`IPR2022-00861, Paper 18 (PTAB Aug. 23, 2022) (precedential) ............. 111-13
`Gen. Plastic Indus. Co. v. Canon Kabushiki Kaisha,
`IPR2016-01357, Paper 19 (PTAB Sept. 6, 2017) (precedential) ............... 111-15
`Google LLC v. Express Mobile Inc.,
`IPR2022-00791, Paper 15 (PTAB Oct. 7, 2022) .............................................. 114
`Intel Corporation v. VLSI Technology LLC,
`IPR2022-00366, Paper 14 (PTAB June 8, 2022) ............................................. 112
`MaxLinear, Inc. v. CF CRESPE LLC,
`880 F.3d 1373, 1377-78 (Fed. Cir. 2018) ......................................................... 108
`Federal Statutes
`35 U.S.C. §102(a) .............................................................................................. 10, 13
`35 U.S.C. §102(b) .................................................................................... 8, 11, 12, 13
`35 U.S.C. §102(e) .................................................................................................... 10
`35 U.S.C. § 103(a) ..................................................................................................... 1
`35 U.S.C. § 314(A) ................................................................................................ 110
`35 U.S.C. § 315(b) ................................................................................................. 113
`
`
`
`v
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`

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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`35 U.S.C. § 316(a)(11) ........................................................................................... 113
`35 U.S.C. § 325(D) ................................................................................................ 110
`Regulations
`37 C.F.R. § 42.100(b) ................................................................................................ 7
`37 C.F.R. §42.104(a) .................................................................................................. 1
`37 C.F.R. §42.104(b) ................................................................................................. 1
`37 C.F.R. §42.122(b) ............................................................................................. 113
`37 C.F.R. § 42.8(b)(1) .............................................................................................. xv
`37 C.F.R. § 42.8(b)(2) .............................................................................................. xv
`37 C.F.R. § 42.8(b)(3) ............................................................................................. xvi
`37 C.F.R. § 42.8(b)(4) ............................................................................................. xvi
`
`
`
`
`
`vi
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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`Exhibit #
`
`EXHIBIT LIST
`
`Description
`
`1001
`
`1002
`
`1003
`
`1004
`
`1005
`
`1006
`
`1007
`
`1008
`
`1009
`
`1010
`
`1011
`
`1012
`
`1013
`
`1014
`
`1015
`
`1016
`
`1017
`
`U.S. Patent No. 10,268,608
`
`File History of U.S. Patent No. 10,268,608
`
`Declaration of Dr. Robert Wedig
`
`Curriculum Vitae of Dr. Robert Wedig
`
`U.S. Patent Pub. No. US2010/0312956 to Hiraishi
`
`U.S. Patent No. 8,020,022 to Tokuhiro
`
`U.S. Patent Pub. No. 2006/0277355 by Ellsberry
`
`U.S. Patent No. 6,184,701 to Kim
`
`U.S. Patent No. 8,566,516 to Schakel
`
`File History of U.S. Patent No. 9,128,632
`
`File History of U.S. Patent No. 9,563,587
`
`SK Hynix Inc. et al. v. Netlist, Inc., IPR2017-00730, Paper No. 1
`(PTAB January 20, 2017) (632 Petition)
`
`SK Hynix Inc. et al. v. Netlist, Inc., IPR2017-00730, Paper No. 1
`(PTAB January 20, 2017) (632 Patent Owner Preliminary Response)
`
`SK Hynix Inc. et al. v. Netlist, Inc., IPR2017-00730, Paper No. 8
`(PTAB July 21, 2017) (632 Decision Denying Institution)
`
`SK Hynix Inc. et al. v. Netlist, Inc., IPR2018-00362, Paper No. 29
`(PTAB June 27, 2019) (907 Final Written Decision)
`
`U.S. Patent Pub. No. 2011/0062999 to Nimaiyar
`
`Declaration of Julie Carlson for JEDEC Standard 21-C
`
`
`
`vii
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`Exhibit #
`
`Description
`
`1018
`
`1019
`
`1020
`
`1021
`
`JEDEC Standard 21-C, DDR SDRAM Registered DIMM Design
`Specification (January 2002)
`
`Declaration of Julie Carlson for JESD79-3C
`
`JEDEC DDR3 SDRAM Standard, JESD79-3C (April 2008)
`
`Bruce Jacob et al., Memory Systems: Cache, DRAM, Disk (2008)
`(excerpts)
`
`1022
`
`Harold S. Stone, Microcomputer Interfacing (1982)
`
`1023 Microsoft Computer Dictionary (5th ed. 2002)
`
`1024
`
`1025
`
`1026
`
`1027
`
`1028
`
`1029
`
`1030
`
`1031
`
`1032
`
`1033
`
`1034
`
`1035
`
`U.S. Patent No. 9,263,103 to Giovannini
`
`U.S. App. No. 61/676,883 (provisional application to ʼ632 Patent)
`
`U.S. Patent No. 8,565,033 to Manohararajah
`
`U.S. Patent No. 7,808,849 to Swain
`
`U.S. Patent No. 6,906,555 to Ma
`
`U.S. Patent Pub. No. 2007/0008791 to Butt
`
`U.S. Patent No. 7,036,053 to Zumkehr
`
`U.S. Patent No. 9,824,035
`
`File History of U.S. Patent No. 9,824,035
`
`U.S. Patent No. 5,036,221 to Brucculeri
`
`U.S. Patent No. 9,536,579 to Iijima
`Complaint, Netlist, Inc. v. Micron Technology, Inc. et al., No. 1:22-
`cv-00136 (W.D. Tex. filed Apr. 28, 2021) (asserting U.S. Patent No.
`10,268,608)
`
`
`
`viii
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`Exhibit #
`1036
`
`Description
`Order Transferring Cases to the Austin Division, Netlist, Inc. v.
`Micron Technology, Inc. et al., No. 1:22-cv-00136 (W.D. Tex. Feb.
`14, 2022)
`
`1037
`
`1038
`
`1039
`
`1040
`
`1041
`
`1042
`
`1043
`
`1044
`
`1045
`
`1046
`
`1047
`
`Joint Claim Construction Statement, Netlist, Inc. v. Micron
`Technology, Inc. et al., No. 1:22-cv-00136 (W.D. Tex. Apr. 14,
`2022)
`
`Order on Motion to Stay, Netlist, Inc. v. Micron Technology, Inc. et
`al., No. 1:22-cv-00136 (W.D. Tex. May 11, 2022), Dkt. 69.
`
`[intentionally omitted]
`
`Final Written Decision in Inter Partes Review, Micron Tech, Inc. et
`al. v. Netlist, Inc., IPR2022-00236, Paper 34 (PTAB June 20, 2023)
`(U.S. Patent No. 9,824,035)
`
`Decision Denying Institution of Inter Partes Review, Micron Tech,
`Inc. et al. v. Netlist, Inc., IPR2022-00237, Paper 15 (PTAB July 19,
`2022) (U.S. Patent No. 10,268,608)
`
`Decision Granting Petitioner’s Request on Rehearing of Final Written
`Decision, Micron Tech, Inc. et al. v. Netlist, Inc., IPR2022-00236,
`Paper 36 (PTAB August 16, 2023) (U.S. Patent No. 9,824,035)
`[intentionally omitted]
`
`Complaint, Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:21-cv-00463 (E.D. Tex. filed Dec. 20, 2021) (asserting U.S. Patent
`No. 10,860,506)
`
`First Amended Complaint, Netlist, Inc. v. Samsung Electronics Co.,
`Ltd. et al., No. 2:21-cv-00463 (E.D. Tex. May 3, 2022)
`
`U.S. Patent No. 10,860,506
`
`Final Written Decision in Inter Partes Review, Samsung
`Electronics Co., Ltd. et al. v. Netlist, Inc., IPR2022-00711,
`Paper 42 (PTAB Oct. 17, 2023) (U.S. Patent No. 10,860,506)
`
`
`
`ix
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`Exhibit #
`1048
`
`Description
`Joint 4-3 Claim Construction and Prehearing Statement, Netlist, Inc.
`v. Samsung Electronics Co., Ltd. et al., No. 2:21-cv-00463 (E.D. Tex.
`Aug. 19, 2022 and Aug. 23, 2022)
`
`1049
`
`1050
`
`1051
`
`1052
`
`1053
`
`1054
`
`1055
`
`1056
`
`1057
`
`Joint Claim Construction Chart Pursuant to P.R. 4-5(d), Netlist, Inc.
`v. Samsung Electronics Co., Ltd. et al., No. 2:21-cv-00463 (E.D. Tex.
`Sept. 30, 2022)
`
`Claim Construction Order, Netlist, Inc. v. Samsung Electronics Co.,
`Ltd. et al., No. 2:21-cv-00463 (E.D. Tex. Dec. 14, 2022)
`
`Defendants’ Objections to Claim Construction Memorandum Order,
`Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No. 2:21-cv-
`00463 (E.D. Tex. Dec. 29, 2022)
`
`File History of U.S. Patent No. 10,860,506
`
`Complaint, Netlist, Inc. v. Micron Technology, Inc. et al., No. 2:22-
`cv-00203 (E.D. Tex. filed June 10, 2022) (asserting U.S. Patent No.
`10,860,506)
`
`Complaint, Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:22-cv-00293 (E.D. Tex. filed Aug. 1, 2022)
`
`First Amended Complaint, Netlist, Inc. v. Samsung Electronics Co.,
`Ltd. et al., No. 2:22-cv-00293 (E.D. Tex. Aug. 15, 2022)
`
`Netlist’s motion to amend its complaint to assert U.S. Patent No.
`10,268,608, Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No.
`2:22-cv-00293 (E.D. Tex. Jan. 20, 2023)
`
`Netlist’s proposed Second Amended Complaint asserting U.S. Patent
`No. 10,268,608 in Netlist, Inc. v. Samsung Electronics Co., Ltd. et
`al., No. 2:22-cv-00293 (E.D. Tex. Jan. 20, 2023)
`
`1058
`
`JEDEC DDR4DB02 Data Buffer Definition Standard, JESD82-32A
`(Aug. 2019)
`
`1059
`
`[intentionally omitted]
`
`
`
`x
`
`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`Exhibit #
`1060
`
`1061
`
`1062
`
`1063
`
`1064
`
`1067
`
`1068
`
`Description
`
`[intentionally omitted]
`
`[intentionally omitted]
`
`[intentionally omitted]
`
`Interim Procedure for Discretionary Denials in AIA Post-Grant
`Proceedings with Parallel District Court Litigation (June 21, 2022)
`
`Federal Court Management Statistics (June 30, 2022), available at
`<https://www.uscourts.gov/statistics/table/na/federal-court-
`management-statistics/2022/06/30-2>
`
`Samsung Petition, Samsung Electronics Co., Ltd. v. Netlist, Inc.,
`IPR2023-00847, Paper 1 (PTAB April 27, 2023) (U.S. Patent No.
`10,268,608)
`
`Decision Granting Institution of Inter Partes Review, Samsung
`Electronics Co., Ltd. v. Netlist, Inc., IPR2023-00847, Paper 13
`(PTAB December 12, 2023) (U.S. Patent No. 10,268,608)
`
`1069 Micron Petition, Micron Tech, Inc. et al. v. Netlist, Inc., IPR2022-
`00237, Paper 1 (PTAB July December 23, 2021) (U.S. Patent No.
`10,268,608)
`
`
`
`
`
`xi
`
`
`
`
`
`

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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
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`CLAIM LISTING
`
`1[a]
`
`1[b]
`
`Listing of Challenged Claims
`Ref. #
`1[pre] 1. A memory module operable to communicate with a memory
`controller via a memory bus, the memory bus including signal lines, the
`signal lines including a set of control/address signal lines and a plurality
`of sets of data/strobe signal lines, the memory module comprising:
`a module board having edge connections for coupling to respective
`signal lines in the memory bus;
`a module control device mounted on the module board and configured
`to receive system command signals for memory operations via the set of
`control/address signal lines and to output module command signals and
`module control signals in response to the system command signals, the
`module control device being further configured to receive a system
`clock signal and output a module clock signal; and
`1[c] memory devices mounted on the module board and configured to
`receive the module command signals and the module clock signal, and
`to perform the memory operations in response to the module command
`signals, the memory devices including a plurality of sets of memory
`devices corresponding to respective sets of the plurality of sets of
`data/strobe signal lines; and
`a plurality of buffer circuits corresponding to respective sets of the
`plurality of sets of data/strobe signal lines,
`1[e] wherein each respective buffer circuit of the plurality of buffer circuits
`is mounted on the module board, coupled between a respective set of
`data/strobe signal lines and a respective set of memory devices, and
`configured to receive the module control signals and the module clock
`signal, the each respective buffer circuit including a data path
`corresponding to each data signal line in the respective set of
`data/strobe signal lines, and a command processing circuit configured to
`decode the module control signals and to control the data path in
`accordance with the module control signals and the module clock
`signal,
`1[f] wherein the data path corresponding to the each data signal line includes
`at least one tristate buffer controlled by the command processing circuit
`and a delay circuit configured to delay a signal through the data path by
`an amount determined by the command processing circuit in response to
`at least one of the module control signals.
`
`1[d]
`
`
`
`xii
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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`Ref. #
`2[a]
`
`3[a]
`
`Listing of Challenged Claims
`2. The memory module of claim 1, wherein the memory operations
`include a first memory operation and a second memory operation
`subsequent to the first memory operation,
`2[b] wherein the command signals include a first set of command signals for
`the first memory operation and a second set of command signals for the
`second memory operation,
`2[c] wherein the module control signals include a first set of module control
`signals output by the module control device in response to the first set of
`command signals and a second set of module control signals output by
`the module control device in response to the second set of command
`signals,
`2[d] wherein the at least one of the module control signals include at least
`one of the first set of module control signals, and
`2[e] wherein the signal through the data path is a signal associated with the
`second memory operation.
`3. The memory module of claim 2, wherein the memory devices are
`arranged in a plurality of ranks and the respective set of memory devices
`include at least one memory device from each of the plurality of ranks,
`3[b] wherein the module command signals include a first set of module
`command signals output by the module control device in response to the
`first set of command signals and a second set of module command
`signals output by the module control device in response to the second
`set of command signals, and
`3[c] wherein the second set of module command signals include chip select
`signals that select the at least one memory device in the respective set
`of memory devices from one of the plurality of ranks to perform the
`second memory operation.
`4. The memory module of claim 1, wherein each of the plurality of
`buffer circuits has a data width of 1 byte, and wherein each of the
`memory devices has a data width of 1 byte.
`5. The memory module of claim 1, wherein each of the plurality of
`buffer circuits has a data width of 1 byte, and wherein each of the
`memory devices has a data width of 4 bits.
`
`4
`
`5
`
`
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`xiii
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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`Ref. #
`6
`
`7
`
`8
`
`9[a]
`
`Listing of Challenged Claims
`6. The memory module of claim 1, wherein the each respective buffer
`circuit further includes a receiver circuit for each of the module control
`signals, the receiver circuit including a metastability detection circuit
`configured to determine a metastability condition in the each of the
`module control signals with respect to the module clock signal.
`7. The memory module of claim 6, wherein each of the plurality of
`buffer circuits has a data width of 1 byte, and wherein each of the
`memory devices has a data width of 1 byte.
`8. The memory module of claim 6, wherein each of the plurality of
`buffer circuits has a data width of 1 byte, and wherein each of the
`memory devices has a data width of 4 bits.
`9. The memory module of claim 1, wherein the each respective buffer
`circuit further includes a clock regeneration circuit configured to
`generate a local clock signal having a programmable phase relationship
`with the module clock signal,
`9[b] wherein the each respective buffer circuit is further configured to output
`the local clock signal to the respective set of memory devices.
`10[a] 10. The memory module of claim 9, wherein the each respective buffer
`circuit includes a first data path for transmitting a strobe signal
`associated with the second memory operation and a second data path for
`transmitting a first data signal associated with the second memory
`operation,
`the first data path including a sampler that samples the strobe signal in
`accordance with the local clock signal, and the second data path
`including a sampler that samples the first data signal in accordance with
`the sampled strobe signal.
`11. The memory module of claim 10, wherein each of the plurality of
`buffer circuits has a data width of 1 byte, and wherein each of the
`memory devices has a data width of 1 byte.
`12. The memory module of claim 10, wherein each of the plurality of
`buffer circuits has a data width of 1 byte, and wherein each of the
`memory devices has a data width of 4 bits.
`
`10[b]
`
`11
`
`12
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`
`
`
`
`
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`xiv
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`I.
`
`PETITIONERS’ MANDATORY NOTICES
`A. Real Party-in-Interest (37 C.F.R. § 42.8(b)(1))
`The real parties in interest of this Petition are the Petitioners Micron
`
`Technology, Inc.; Micron Semiconductor Products, Inc., and Micron Technology
`
`Texas LLC.
`
`B. Related Matters (37 C.F.R. § 42.8(b)(2))
`The following judicial or administrative matters would affect, or be affected
`
`by, a decision in this proceeding concerning U.S. Patent No. 10,268,608 (“’608
`
`Patent”).
`
`• Samsung Electronics Co., Ltd. v Netlist, Inc., IPR2023-00847 (“Samsung
`
`IPR”)
`
`• Netlist, Inc. v. Micron Technology, Inc. et al., No. 1:22-cv-00136 (W.D.
`
`Tex. filed Apr. 28, 2021)
`
`• Netlist, Inc. v. Micron Technology, Inc. et al., No. 2:22-cv-00203 (E.D.
`
`Tex. filed June 10, 2022)
`
`• Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No. 2:22-cv-00293
`
`(E.D. Tex. filed August 1, 2022); Netlist, Inc. v. Micron Technology, Inc.
`
`et al., 2:22-cv-00294 (E.D. Tex. filed August 1, 2022)
`
`• Netlist, Inc. v. Samsung Electronics Co., Ltd. et al., No. 2:21-cv-00463
`
`(E.D. Tex. filed Dec. 20, 2021)
`
`
`
`xv
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`

`

`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`• Micron Technology, Inc. et al. v. Netlist, Inc., IPR2022-00237
`
`• Micron Technology, Inc. et al. v. Netlist, Inc., IPR2022-00236
`
`• Samsung Electronics Co., Ltd. v Netlist, Inc., IPR2022-00711
`
`• Micron Technology, Inc. et al. v. Netlist, Inc., IPR2023-00205
`
`• SK hynix Inc. et al. v. Netlist, Inc., IPR2017-00730
`
`C. Lead and Back-up Counsel (37 C.F.R. § 42.8(b)(3))
`Lead Counsel
`is: Matthew A. Hopkins
`(Reg. No. 76, 273),
`
`MHopkins@winston.com, (202) 282-5862, 1901 L Street NW, Washington, D.C.
`
`20036.
`
`Backup Lead Counsel are: Michael R. Rueckheim (Pro Hac Vice to be
`
`submitted) and Ryuk Park (Pro Hac Vice to be submitted), (650) 858-6000,
`
`MRueckheim@winston.com, RPark@winston.com, 255 Shoreline Dr., Suite 520,
`
`Redwood Shores, CA 94065. The fax number for lead and backup counsel is (202)
`
`282-5100.
`
`Service Information (37 C.F.R. § 42.8(b)(4))
`D.
`Petitioners consent to service of all documents via electronic mail to Winston-
`
`IPR-NetList@winston.com.
`
`
`
`xvi
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`

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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
`
`II.
`
`INTRODUCTION
`Petitioners respectfully request trial on claims 1-12 of U.S. Patent 10,268,608
`
`(“ʼ608 Patent”) (EX1001) based on Hiraishi (EX1005) in combination with various
`
`secondary references, none considered during prosecution.
`
`III. COMPLIANCE WITH IPR REQUIREMENTS
`A. Grounds for Standing (§42.104(a))
`Petitioners certify that the ʼ608 Patent is available for IPR and that Petitioners
`
`are not barred or estopped from requesting an IPR on the grounds below.
`
`Identification of Challenge (§42.104(b))
`B.
`Petitioners challenge claims 1-12 of the ʼ608 Patent under §103(a) as follows:
`
`
`
`Ground
`
`Claims
`
`1 Hiraishi + Butt
`
`2 Ground 1 + Tokuhiro
`
`3
`
`4
`
`5
`
`(Ground 1 or 2) + Ellsberry
`
`(Ground 1 or 2) + Kim
`
`(Ground 1 or 2) + Kim and Ellsberry
`
`1-12
`
`1-12
`
`5, 12
`
`6-8
`
`8
`
`
`IV. RELEVANT INFORMATION CONCERNING THE CONTESTED
`PATENT
`A. Effective Filing Date
`The ʼ608 Patent claims priority to a provisional application filed July 27,
`
`2012, EX1001; EX1025, which is after Petitioners’ prior art. For IPR purposes only,
`
`Petitioners assume this date as the effective filing date.
`1
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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
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`Person of Ordinary Skill in the Art (“POSITA”)
`B.
`A POSITA in the ʼ608 Patent’s field in July 2012 would have been someone
`
`with an advanced electrical or computer engineering degree and at least two years
`
`of work experience in the field of memory module design and operation, or a
`
`bachelor’s degree in such engineering disciplines and at least three years of field
`
`work experience. EX1003, ¶37. A POSITA would have been familiar with the
`
`JEDEC industry standards, and knowledgeable about the design and operation of
`
`computer memories, including standard-compliant DRAM and SDRAM devices,
`
`and their interaction with computer components, such as memory controllers. Id. A
`
`POSITA would also have been familiar with the structure and operation of circuitry
`
`used to access and control computer memories and other memory components. Id.
`
`C. The ʼ608 Patent
`1. Overview
`The ʼ608 Patent discloses a memory module (110) including memory devices
`
`(112, green) organized in groups, each group with an associated data buffer (118,
`
`blue) and one module control device (116, red). EX1003, ¶38; EX1001, 3:25-27,
`
`3:51-54, FIG.2C (below).1
`
`
`1 All emphasis and color highlighting has been added unless otherwise noted.
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`
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`2
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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
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`As shown below, the memory module (110) is connected to a memory
`
`controller (MCH) (101) with a bus including control/address (C/A) signal lines (120,
`
`purple) to the module controller (116, red) and data/strobe signal lines (130, orange)
`
`to the data buffers (118, blue) which communicate data with respective groups of
`
`memory devices 112 (green). EX1003, ¶¶39-40; EX1001, 3:29-34, 4:20-32, FIG.1
`
`(below).
`
`
`
`The module controller (116, red) receives system commands from the memory
`
`controller (101) and generates from them module command signals for the memory
`
`devices and module control signals for the data buffers. EX1003, ¶¶41- 42; EX1001,
`
`4:27-30, 4:65-5:7, 5:57-65, see also id. FIGS. 2A-2B, 6:12-29, 4:60-64.
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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
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`Because the data buffers (blue) and associated memory devices (green) are
`
`distributed across the memory module, “a same set of module control signals may
`
`reach different [data buffers (blue)] at different times across more than one clock
`
`cycle of the system clock.” EX1003, ¶43; EX1001, 9:52-10:6, 10:7-21. The ʼ608
`
`Patent purports to solve this “fly-by” problem by each data buffer determining a time
`
`interval based on signal timing during a write operation—in particular, the difference
`
`(EWD) between reception of a write command (W/C) and reception of the
`
`corresponding data strobe (DQS1) (FIG.12A, below)—which is then used to adjust
`
`signal timing during memory read operations (FIG.12B, below). EX1003, ¶44;
`
`EX1001, 15:27-50, 15:66-16:9, FIGS. 12A-12B.
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`
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`Petition for Inter Partes Review of U.S. Patent No. 10,268,608
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`
`
`Prosecution History
`2.
`The ʼ608 Patent claims are not patentably distinct from the claims of parent
`
`U.S. Patent No. 9,824,035 (“the ʼ035 Patent”) and child U.S. Patent No. 10,860,506
`
`(“the ‘506 Patent”). EX1003, ¶¶54-64, 67-69; EX1031; EX1046; EX1052, pp.140-
`
`51, 185-86; EX1002, pp.83-91, 102-03. The Board found all ’506 claims and most
`
`’035 claims unpatentable in final written decisions involving Petitioner