`
`
`
`I III IIIIIIII 111111111114I3FIIMIIIIIII 111111 IIII
`
`(12) United States Patent
`Iijima et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 9,536,579 B2
`Jan. 3, 2017
`
`(54) SEMICONDUCTOR INTEGRATED CIRCUIT
`CAPABLE OF PRECISELY ADJUSTING
`DELAY AMOUNT OF STROBE SIGNAL
`
`(75)
`
`Inventors: Masaaki Iijima, Kawasaki (JP);
`Mitsuhiro Deguchi, Kawasaki (JP)
`
`(73) Assignee: RENESAS ELECTRONICS
`CORPORATION, Tokyo (JP)
`
`( * ) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 6 days.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`6,205,086 B1
`6,222,792 B1
`
`3/2001 Hanzawa et al.
`4/2001 Hanzawa et al.
`(Continued)
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`
`11/2000
`2000-311028 A
`11/2000
`2000-323969 A
`(Continued)
`
`(21)
`
`Appl. No.:
`
`14/369,501
`
`(22)
`
`PCT Filed:
`
`Dec. 29, 2011
`
`(86)
`
`PCT No.:
`
`PCT/JP2011/080532
`
`§ 371 (c)(1),
`(2), (4) Date:
`
`Jun. 27, 2014
`
`(87) PCT Pub. No.: WO2013/099035
`
`PCT Pub. Date: Jul. 4, 2013
`
`(65)
`
`Prior Publication Data
`
`US 2015/0029800 Al
`
`Jan. 29, 2015
`
`(51) Int. Cl.
`G11C 7/22
`H03K 19/00
`H03K 19/096
`(52) U.S. Cl.
`CPC
`
`(2006.01)
`(2006.01)
`(2006.01)
`
` G11C 7/222 (2013.01); H03K 19/0016
`(2013.01); HO3K 19/096 (2013.01)
`(58) Field of Classification Search
`CPC .... G11C 7/222; H03K 19/0016; H03K 19/096
`See application file for complete search history.
`
`OTHER PUBLICATIONS
`
`English translation of International Search Report PCT/JP2011/
`080532 dated Jan. 31, 2012.
`(Continued)
`
`Primary Examiner — J. H. Hur
`(74) Attorney, Agent, or Firm — McDermott Will &
`Emery LLP
`
`ABSTRACT
`(57)
`An interface circuit provided in a semiconductor device
`supplies an operation clock to an external memory device
`based on a clock signal and receives a data signal and a
`strobe signal from the external memory device. The inter-
`face circuit includes a delay circuit delaying the received
`strobe signal. The delay circuit includes a first adjustment
`circuit and a second adjustment circuit connected in series
`with the first adjustment circuit. The first adjustment circuit
`is capable of adjusting a delay amount of the strobe signal
`in a plurality of steps in accordance with the set frequency
`of the clock signal. The second adjustment circuit is capable
`of adjusting the delay amount of the strobe signal with a
`higher precision than the first adjustment circuit.
`
`6 Claims, 17 Drawing Sheets
`
`DQ
`
`20
`
`21
`
`DOS Li]
`
`( -22
`
`I/O
`
`(-23
`I/O
`
`24
`
`("26
`
`OFFSET
`ADJUSTMENT
`CIRCUIT
`A
`
`14
`
`MEMC
`(TABLE)
`
`OFFSET
`CONTROL
`CIRCUIT
`\ 30
`
`14: OFFSET
`SETTING
`VALUE
`
`34 PULSE GENERATOR
`(LAUNCH F/F)
`
`(-5
`
`(- 28
`
` >•READ DATA
`
`DQS90 r
`
`,-25:DQS DELAY CIRCUIT
`( -27
`DELAY AMOUNT
`- ADJUSTMENT
`CIRCUIT
`A
`-41 :DELAY
`CODE
`32
`
`CONTROL MODULE
`
`33
`
`-- 31 : CALIBRATION
`CONTROL
`CIRCUIT
`
`: PHASE
`COMPARATOR
`(CAPTURE F/F)
`
`CLKa
`
`CLKb
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 1
`
`

`

`US 9,536,579 B2
`Page 2
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`
`JP
`JP
`JP
`
`2009-021706 A
`2009-212735 A
`2011-188042 A
`
`1/2009
`9/2009
`9/2011
`
`2002/0149967 Al * 10/2002 Borkenhagen
`
`2003/0070052 Al *
`
`4/2003 Lai
`
`2005/0047192 Al
`2008/0276112 Al
`2009/0039930 Al
`2012/0194248 Al *
`
`3/2005 Matsui et al.
`11/2008 Matsui et al.
`2/2009 Kuroki et al.
`8/2012 Magee
`
` G11C 7/1078
`365/189.05
` G06F 13/4243
`711/167
`
` G11C 7/04
`327/262
`
`FOREIGN PATENT DOCUMENTS
`
`JP
`JP
`JP
`JP
`
`2005-078547 A
`2006-099244 A
`2007-226308 A
`2008-311999 A
`
`3/2005
`4/2006
`9/2007
`12/2008
`
`OTHER PUBLICATIONS
`
`Taiwanese Office Action dated Jan. 29, 2016 issued in Taiwanese
`Patent Application No. 101147529 (English translation).
`Japanese Office Action dated Sep. 29, 2015, issued in corresponding
`Japanese Patent Application No. 2013-551167. (w/ English trans-
`lation).
`Japanese Office Action dated Sep. 29, 2015 issued in Japanese
`Patent Application No. 2013-551167 (English translation).
`Chinese Office Action dated May 3, 2016 issued in Chinese Patent
`Application No. 201180076035.8 (English translation).
`Taiwanese Office Action dated Sep. 9, 2016 issued in Taiwanese
`Patent Application No. 101147529 (English translation).
`
`* cited by examiner
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 2
`
`

`

`lualud °S11
`
`LI JO 1 WIN
`
`ZS 6LS`9£S% Sfl
`
`FIG. 1
`
`61
`
`11 :CONTROL SIGNAL
`
`PLL
`
`<
`1 2 : Os IOGNNTARLO L
`
`
`
`CLOCK
`GENERATOR
`
`c
`
`SYSTEM
`CLOCK CK
`
`CPU
`
`-x-13 : CLOCK
`INFORMATION
`
`4A
`
`•
`
`
`
` TABLE MEMC
`
`14: OFFSET-- --
`SETTING VALUE
`
`A
`
`V
`
`DDR-PHY
`
`A
`
`•
`
`•
`
`•
`
`-5
`
`Q VDQS
`
`DRAM
`
`CLOCK
`COMMAND
`ADDRESS
`2 DATA MASK
`
`-3
`
`- -1:SoC
`
`(- 8: BUS
`
`4
`
`COMMAND
`ADDRESS
`WRITE DATA
`READ DATA
`OPERATION SETTING
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 3
`
`

`

`lualud °S11
`
`LI JO Z WIN
`
`ZS 6LS`9£S% Sfl
`
`FIG.2
`
`20
`
`DQ
`
`
`
`21
`
`DQS th]
`
`1
`MEMC
`(TABLE)
`
`( -22
`
`I/O
`
`(-23
`
`/O
`
`1
`4: OFFSET
`SETTING
`VALUE
`
`24
`
`26
`
`OFFSET
`ADJUSTMENT
`CIRCUIT
`--"A
`--14
`OFFSET
`CONTROL
`CIRCUIT
`--30
`
`5
`
`(-28
`
` > READ DATA
`
`-I
`
`,- 25:DQS DELAY CIRCUIT
` 1
`( -27
`DQS90
`DELAY AMOUNT
`ADJUSTMENT
`CIRCUIT
`
`/.
`
`-41 :DELAY
`CODE
`( -32
`
`CONTROL MODULE
`
`-- 31:CAL1BRATION
`CONTROL
`CIRCUIT
`
`3
`
`34: PULSE GENERATOR
`(LAUNCH F/F)
`
`____<<-
`
`----1--- 35: PHASE
`COMPARATOR
`(CAPTURE F/F)
`
`CLKa
`
`CLKb
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 4
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 3 of 17
`
`US 9,536,579 B2
`
`FIG.3
`
`DQS
`
`DQ
`
`DQS90
`
`Pi D2 D3
`
`t1
`
`t3
`
`t5
`
`t7
`
`t2
`
`t4
`
`t6
`
`t8
`
`TIME
`
`6<— 90°
`
`FIG.4
`
`CLKa (LAUNCH F/F)
`
`DQS90
`
`CLKb (CAPTURE F/F)
`
`t2
`
`TIME
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 5
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 4 of 17
`
`US 9,536,579 B2
`
`FIG.5
`
`60--
`
` ,NAND
`
`NOR
`--,
`
`-27
`
`-61
`
`I-co-rxtx›.-L
`
`
`
`1-,
`.-1-,
`
`IN
`
`INV
`
`
`
`41—{'r
`
`1
` L - -:7--- - 62
`
`OUT
`
`67
`
`---66
`
`r---65
`
`---64
`-63
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 6
`
`

`

`lualud °S11
`
`LI JO S WIN
`
`ZS 6LS`9£S% Sfl
`
`FIG.6
`
`21
`
`DQS l', 1--Di"
`
`( -23
`I/O
`
`,-25
`DQS DELAY
`CIRCUIT
`
`4:-26
`OFFSET ADJUSTMENT
`CIRCUIT
`N STAGES DE N2 N3 59
`
`52-- _,-
`
`51--
`-......
`
`->.
`
`-->. -r NI
`
`24
`
`'-50
`
`NO N1
`
`( -4
`
`MEMO
`
`i
`14:OFFSET
`SETTING
`VALUE
`
`-14
`
`OFFSET
`CONTROL
`CIRCUIT
`
`30
`
`( -27
`
`DELAY
`AMOUNT
`ADJUSTMENT
`CIRCUIT
`
`DQS90
`
`-41:DELAY
`CODE
`( -32
`
`CONTROL MODULE
`
`("3
`
`34
`
`<--
` <
`LAUNCH CAPTURE
`F/F
`F/F
`
`-Th-- 35
`
`T
`
`'31:CALIBRATION
`CONTROL CIRCUIT
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 7
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 6 of 17
`
`US 9,536,579 B2
`
`FIG.7
`
`BIT RATE (OPERATION FREQUENCY) f OFFSET SETTING VALUE
`≤
`
`f
`
`266Mbps
`≤
`
`266Mbps < f
`333Mbps
`333Mpbs < f 5 400Mbps
`≤
`
`400Mbps < f
`
`533Mbps
`
`3
`
`2
`
`0
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 8
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 7 of 17
`
`US 9,536,579 B2
`
`FIG.8
`
`TG90
`
`DELAY AMOUNT
`
`FIG.9
`
`TG90
`
`DELAY AMOUNT
`
`FIG.10
`
`TG90
`
`DELAY AMOUNT
`
`TARGET DELAY
`
`f
`
`A DELAY IS LARGE
`
`DELAY CODE
`
`TARGET DELAY
`
`t
`A DELAY IS SMALL
`
`DELAY CODE
`
`TARGET-DELAY
`SETTING RANGE
`,
`I TARGET DELAY A DELAY
`
`S SMALL
`
`OFFSET=3
`
`OFFSET=2
`
`OFFSET = 1
`
`OFFSET=0
`
`DELAY CODE
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 9
`
`

`

`lualud °S11
`
`LI Jo 8 WIN
`
`ZS 6LS`9£S% Sfl
`
`FIG.11
`
`133
`
`200
`
`66
`
`33
`400
`
`DELAY AMOUNT
`
`TARGET-DELAY
`SETTING RANGE
`
`3) OFFSET=3 (E.G. 266Mbps)
`2) OFFSET=2 (E.G. 333Mbps)
`1) OFFSET=1 (E.G. 400Mbps)
`0) OFFSET=0 (E.G. 533Mbps)
`
`.1-t- r.- -
`
`•-r-r
`
`533
`666
`800
`
`DELAY CODE
`
`3)
`2)
`1)
`0)
`
`3)
`2)
`1)
`
`4
`
`0)
`
`MAX CONDITION
`
`MIN CONDITION
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 10
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 9 of 17
`
`US 9,536,579 B2
`
`FIG.1 2
`
`OFFSET ADJUSTMENT
`CIRCUIT
`
`12.5%
`
`DECODE CIRCUIT
`
`35.5%
`
`DELAY AMOUNT
`ADJUSTMENT CIRCUIT
`(SELECTOR)
`
`24.1%
`
`100%
`
`DELAY AMOUNT
`ADJUSTMENT CIRCUIT
`(DELAY LINE)
`
`28.1%
`
`,
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 11
`
`

`

`lualud °S11
`
`LI JO OT WIN
`
`ZS 6LS`9£S% Sfl
`
`FIG.13
`
`(1)
`FREQUENCY fo
`
`/
`
`- 1 F r
`
`CK
`
`—.1_1
`
`CKE
`
`DRAM COMMAND
`
`I SREF1-<
`SELF REFRESH
`ENTRY
`
`SELF REFRESH
`PERIOD
`
`OFFSET SETTING
`
`OFFSET (X)
`
`CALIBRATION SIGNAL
`
`to
`
`t 1
`
`t2
`
`FREQUENCY f1
`
`L
`i
`
`DRAM PROCESSING
`
`REF
`
`SRE
`SELF REFRESH
`EXIT
`
`OFFSET (Y)
`
`L
`_1
`i==>,
`
`START
`ORDINARY
`ACCESS
`
`15 OR MORE CYCLES
`
`t5
`
`t6
`
`Pj,
`
`17
`
`\
`t3
`
`t4
`
`TIME
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 12
`
`

`

`lualud °S11
`
`LI JO II WIN
`
`ZS 6LS`9£S% Sfl
`
`FIG.14
`
`L.'-26A
`OFFSET ADJUSTMENT
`CIRCUIT
`DE
`53A
`
`59
`....is_
`
`52A
`
`1
`
`,-25A
`DQS DELAY
`CIRCUIT
`
`DQS90
`
`27
`
`DELAY
`AMOUNT
`ADJUSTMENT
`CIRCUIT
`A
`
`41:DELAY
`CODE
`( -32
`
`NUMBER OF
`BUFFERS (E.G.)
`
`N STAGES ---------,J___,
`2N STAGES -----...., -L,....,
`4N STAGES
`
`......
`
`24
`
`51A
`
`-14
`
`23
`
`DQS
`
`I/O
`
`-->
`
`21
`
`( -4
`
`MEMC
`
`14: OFFSET
`SETTING
`VALUE
`
`OFFSET
`CONTROL -30
`CIRCUIT
`
`CONTROL MODULE
`
`( -3
`
`34-1--
`
`''*-35
`<
`<-
`LAUNCH CAPTURE
`F/F
`F/F
`
`T
`
`31:CALIBRATION
`CONTROL CIRCUIT
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 13
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 12 of 17
`
`US 9,536,579 B2
`
`FIG.15
`
`BIT RATE (OPERATION FREQUENCY) f OFFSET SETTING VALUE
`f ≤ 200Mbps
`≤
`
`3
`
`2
`
`200Mbps < f
`
`266Mbps
`
`-.≤
`-. 333Mbps
`266Mpbs < f
`333Mbps < f -,_.≤- 800Mbps
`
`0
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 14
`
`

`

`lualud °S11
`
`LI JO £1 WIN
`
`ZS 6LS`9£S% Sfl
`
`FIG.16
`
`3) OFFSET=3 (E.G. 200Mbps)
`2) OFFSET=2 (E.G. 266Mbps)
`1) OFFSET=1 (E.G. 333Mbps)
`0) OFFSET=0 (E.G. 800Mbps)
`
`133
`
`DELAY AMOUNT
`
`,
`
`R3_
`R2
`
`R1
`
`.*.•
`
`R0
`
`.2.
`
`266
`
`333
`
`TARGET-DELAY
`SETTING RANGE
`
`47.
`
`166'
`
`800
`
`DELAY CODE
`
`• .•
`
`3)
`2)
`
`1) > MAX CONDITION
`
`0),
`3)
`2)
`1) MIN CONDITION
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 15
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 14 of 17
`
`US 9,536,579 B2
`
`FIG.1 7
`(A)
`
`DELAY AMOUNT
`
`R0
`
`0)
`MAX CONDITION
`
` 0)
`MIN CONDITION
`
`DELAY CODE
`
`(B)
`
`ADDED OFFSET VALUE
`
`DELAY AMOUNT
`
`R2
`
`R
`
`MAX CONDITION
`
`1)
`
`MIN CONDITION
`
`DELAY CODE
`
`(C)
`
`ADDED OFFSET VALUE
`
`2)
`
`DELAY AMOUNT
`
`R1
`
`R2
`
`R0
`
`DELAY CODE
`
`MAX CONDITION
`
`2Y
`1) MIN CONDITION
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 16
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 15 of 17
`
`US 9,536,579 B2
`
`FIG.1 8
`(A)
`
`DELAY AMOUNT
`
`A
`R0
`V
`
`0)
`MAX CONDITION
`. 0)
`MIN CONDITION
`
`DELAY CODE
`
`(B)
`
`ADDED OFFSET VALUE
`
`DELAY AMOUNT
`
`R1_
`
`R0
`
`DELAY CODE
`
`(C)
`
`ADDED OFFSET VALUE
`
`DELAY AMOUNT
`v R2
`R1
`A
`
`R0
`
`DELAY CODE
`
`MAX CONDITION
`
`MIN CONDITION
`
`0)
`1)
`0)
`
`2)
`1)
`
`MAX CONDITION
`
`(2)
`=;1) MIN CONDITION
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 17
`
`

`

`lualud °S11
`
`LI JO 91 WIN
`
`ZS 6LS`9£S% Sfl
`
`FIG.19
`
`,-26B
`OFFSET ADJUSTMENT CIRCUIT
`
`,-25B
`,
`DQS DELAY
`CIRCUIT
`
`21
`
`DQS
`
`--23
`
`I/O
`
`(--4
`
`MEMC
`
`14,43
`
`53-- _,
`
`N STAGES DE DE
`
`
`0
`1
`
`52--
`
`-H4>q)---
`
`51--
`
`--;
`
`50-
`
`
`
`,
`
`0
`1
`
`0
`1
`
`0
`
`57
`
`56
`
`55
`
`54
`
`59
`
`3
`
`2
`
`0
`
`r 27
`
`DELAY
`AMOUNT
`ADJUSTMENT
`CIRCUIT
`
`DQS90
`I
`
`24
`
`143 :BYPASSEN
`
`-14: OFFSET
`SETTING
`VALUE
`-30A
`
`OFFSET
`BYPASS
`CONTROL
`CIRCUIT
`
`-41 :DELAY
`CODE
`i -32
`
`CONTROL MODULE
`
`1
`
`/ 1
`
`34--i--
`
`,_,,
`___C--
`LAUNCH CAPTURE
`F/F
`F/F
`
`-35
`
`T
`
`31:CALIBRATION
`CONTROL CIRCUIT
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 18
`
`

`

`U.S. Patent
`
`Jan. 3, 2017
`
`Sheet 17 of 17
`
`US 9,536,579 B2
`
`FIG.20
`
`OFFSET = 0
`
`BYPASS_EN = 0
`
`DELAY AMOUNT
`
`BYPASS_EN = 1
`
`1MAX CONDITION
`
`TG90
`
`TG45
`
`}MIN CONDITION
`\ ---90° DELAY
` 45° DELAY
`
`DELAY CODE
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 19
`
`

`

`US 9,536,579 B2
`
`1
`SEMICONDUCTOR INTEGRATED CIRCUIT
`CAPABLE OF PRECISELY ADJUSTING
`DELAY AMOUNT OF STROBE SIGNAL
`
`2
`PTD 3: Japanese Patent Laying-Open No. 2009-21706
`PTD 4: Japanese Patent Laying-Open No. 2000-311028
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`5
`
`SUMMARY OF INVENTION
`
`Technical Problem
`
`This application is the U.S. National Phase of PCT/
`JP2011/080532 filed Dec. 29, 2011, the subject matter of
`which is incorporated herein by reference in entirety.
`
`TECHNICAL FIELD
`
`The present invention relates to a semiconductor device
`including an interface circuit to/from which data is input/
`output from/to a memory device, and particularly relates to
`a semiconductor device to/from which data is input/output
`from/to a double data rate (DDR) synchronous memory.
`
`BACKGROUND ART
`
`As a synchronous memory to/from which data is input/
`output at a double data rate, a DDR-SDRAM (Synchronous
`Dynamic Random Access Memory) for example is known.
`For the purpose of high-speed clock synchronous commu-
`nication, the DDR-SDRAM outputs a data signal and a
`strobe signal synchronized with the data signal. The data
`signal and the strobe signal which are output from the
`DDR-SDRAM have respective edges that coincide with
`each other.
`In the interface circuit receiving the data signal and the
`strobe signal which are output from the DDR-SDRAM, a
`delay circuit is necessary that delays the received strobe
`signal by a 1/4 period. Delay of the input strobe signal by a
`1/4 period (corresponding to a phase of 90 degrees) enables
`the data signal to be taken at both the rising edge and the
`falling edge of the strobe signal.
`As a circuit for adjusting the amount of delay of the strobe
`signal, a circuit disclosed in Japanese Patent Laying-Open
`No. 2008-311999 (PTD 1) for example is known. This
`circuit includes a variable delay unit providing a variable
`amount of delay, a phase comparison unit, and a delay
`control unit. The phase comparison unit compares the phase
`of the strobe signal given from an input buffer gate with the
`phase of a delay signal given from the variable delay unit.
`Based on the result of comparison by the phase comparison
`unit, the delay control unit sets the amount of delay of the
`variable delay unit.
`An operation clock of the DDR-SDRAM is supplied as an
`external clock from the aforementioned interface circuit.
`Input/output of data to/from the DDR-SDRAM is synchro-
`nized with the external clock. Therefore, the DDR-SDRAM
`is provided with a regeneration circuit for regenerating an
`internal clock that is correctly synchronized with the exter-
`nal clock. As such a regeneration circuit, a PLL (Phase Lock
`Loop) circuit (see for example Japanese Patent Laying-Open
`No. 2000-323969 (PTD 2)), or a DLL (Delay Lock Loop)
`circuit (see for example Japanese Patent Laying-Open No.
`2009-21706 (PTD 3)), or an SMD (Synchronous Mirror
`Delay) circuit (see for example Japanese Patent Laying-
`Open No. 2000-311028 (PTD 4)) is used, for example.
`
`CITATION LIST
`
`Patent Document
`
`PTD 1: Japanese Patent Laying-Open No. 2008-311999
`PTD 2: Japanese Patent Laying-Open No. 2000-323969
`
`It is necessary for the delay circuit provided in the
`interface circuit to make the delay amount of the delay
`10 circuit correctly identical to a target delay which is deter-
`mined in accordance with the frequency of the strobe signal,
`namely the operation frequency of the memory device.
`Particularly in recent memory devices, the operation fre-
`quency of the memory device may be changed for use in
`15 order to reduce power consumption. Therefore, the delay
`amount must be adjusted for a wider frequency range than
`the conventional one.
`The delay circuit is usually made up of many cascade-
`connected delay elements (inverters for example). The delay
`20 amount of the strobe signal is adjusted by changing the
`number of stages of delay elements through which the strobe
`signal is passed. Therefore, for accommodation to a wider
`frequency range, an increase of the number of delay ele-
`ments has conventionally been unavoidable, which leads to
`25 an increase of the area occupied by the delay circuit.
`Meanwhile, if the delay amount of each delay element is
`simply increased, an error relative to a target delay which is
`determined in accordance with the operation frequency of
`the memory device increases, resulting in a problem of a
`30 reduced margin of a setup time or hold time when data is
`read from the memory device.
`An object of the present invention is to provide a semi-
`conductor device including an interface circuit which
`receives a data signal and a strobe signal from a memory
`35 device, in such a manner that makes the delay amount
`correctly adjustable for a wider frequency range while
`reducing area penalty.
`
`40
`
`Solution to Problem
`
`A semiconductor device according to an embodiment of
`the present invention includes a clock generator generating
`a clock signal having a set frequency, and an interface
`circuit. The interface circuit supplies an operation clock to
`45 an external memory device based on the clock signal, and
`receives a data signal and a strobe signal from the external
`memory device. The interface circuit includes a delay circuit
`delaying the received strobe signal, and a data detection
`circuit sampling the data signal at a timing of an edge of the
`50 delayed strobe signal. The delay circuit includes a first
`adjustment circuit and a second adjustment circuit connected
`in series with the first adjustment circuit. The first adjust-
`ment circuit is capable of adjusting a delay amount of the
`strobe signal in a plurality of steps in accordance with the set
`55 frequency of the clock signal. The second adjustment circuit
`is capable of adjusting the delay amount of the strobe signal
`with a higher precision than the first adjustment circuit.
`
`Advantageous Effects of Invention
`
`60
`
`In accordance with the above-described embodiment, the
`delay circuit for delaying the strobe signal includes the first
`adjustment circuit and the second adjustment circuit capable
`of making adjustment with a higher precision than the first
`65 adjustment circuit. The delay amount of the first adjustment
`circuit is adjusted in a plurality of steps in accordance with
`the set frequency of the clock signal. Therefore, the delay
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 20
`
`

`

`US 9,536,579 B2
`
`3
`amount can accurately be adjusted for a wider frequency
`range while reducing area penalty.
`
`BRIEF DESCRIPTION OF DRAWINGS
`
`FIG. 1 is a block diagram showing a configuration of a
`semiconductor device 1 according to a first embodiment of
`the present invention.
`FIG. 2 is a block diagram showing a configuration of a
`part of an interface circuit 5 in FIG. 1.
`FIG. 3 is a diagram schematically showing respective
`waveforms of a strobe signal DQS, a data signal DQ, and a
`delayed strobe signal DQS90.
`FIG. 4 is a diagram schematically showing respective
`waveforms of clock signals CLKa, CLKb and a delayed
`pulse DQS90.
`FIG. 5 is a diagram showing an example configuration of
`a delay amount adjustment circuit 27 in FIG. 2.
`FIG. 6 is a diagram showing an example configuration of
`an offset adjustment circuit 26 in FIG. 2.
`FIG. 7 is a diagram showing an example conversion table
`stored in a memory controller 4 in FIG. 1.
`FIG. 8 is a diagram schematically showing a relationship
`between a delay code and a delay amount of a DQS delay
`circuit in a comparative example (in the case where the unit
`of change of the delay amount is relatively large).
`FIG. 9 is a diagram schematically showing a relationship
`between the delay code and the delay amount of the DQS
`delay circuit in a comparative example (in the case where the
`unit of change of the delay amount is relatively small).
`FIG. 10 is a diagram schematically showing a relationship
`between delay code 41 and the delay amount of a DQS delay
`circuit 25 in FIG. 6.
`FIG. 11 is a diagram showing a relationship between the
`delay code and the delay amount of DQS delay circuit 25 in
`the case where the delay amount of each delay element DE
`is varied.
`FIG. 12 is a diagram showing an example of the ratio of
`the area of each circuit which is a constituent element of
`DQS delay circuit 25.
`FIG. 13 a diagram showing an example operation
`sequence of semiconductor device 1 in FIG. 1.
`FIG. 14 is a diagram showing a configuration of a DQS
`delay circuit 25A provided in a semiconductor device
`according to a second embodiment of the present invention.
`FIG. 15 is a diagram showing an example conversion
`table stored in memory controller 4 for offset adjustment
`circuit 26A in FIG. 14.
`FIG. 16 is a diagram showing a relationship between the
`delay code and the delay amount of DQS delay circuit 25A
`in FIG. 14.
`FIG. 17 is a diagram for illustrating a procedure of
`determining the number of stages of delay elements pro-
`vided in each delay line.
`FIG. 18 is a diagram of a comparative example relative to
`FIG. 17, for illustrating a case where the number of stages
`of delay elements provided in each delay line is inappropri-
`ate.
`FIG. 19 is a diagram showing a configuration of a DQS
`delay circuit 25B provided in a semiconductor device
`according to a third embodiment of the present invention.
`FIG. 20 is a diagram showing, regarding DQS delay
`circuit 25B in FIG. 19, a relationship between the delay code
`and the delay amount of the whole delay circuit when the
`offset value is 0.
`
`DESCRIPTION OF EMBODIMENTS
`
`In the following, embodiments of the present invention
`will be described in detail with reference to the drawings.
`
`4
`The same or corresponding parts are denoted by the same
`reference characters, and a description thereof will not be
`repeated.
`
`5
`
`First Embodiment
`
`25
`
`[Overall Configuration of Semiconductor Device 1]
`FIG. 1 is a block diagram showing a configuration of a
`semiconductor device 1 according to a first embodiment of
`10 the present invention. Referring to FIG. 1, semiconductor
`device 1 is configured in the form of SoC (System on Chip)
`where many functional blocks are integrated onto a semi-
`conductor substrate. Specifically, semiconductor device 1
`includes a central processing unit (CPU) 3 controlling the
`15 whole semiconductor device, an interface circuit 5, a
`memory controller (MEMC) 4, a PLL circuit 6, and a clock
`generator 7, for example.
`Interface circuit 5 is connected with an external DRAM
`(Dynamic Random Access Memory) device 2 (DDR-
`2o SDRAM). Interface circuit 5 is a physical interface (DDR-
`PHY) for accessing DRAM device 2 at a double data rate.
`Specifically, interface circuit 5 outputs, to DRAM device 2,
`a clock, various commands, address signals (row address,
`column address), and a data mask signal, for example.
`Further, between interface circuit 5 and DRAM device 2,
`data signal DQ and strobe signal DQS are input/output
`to/from each other. When data is read from DRAM device
`2 into interface circuit 5, DRAM device 2 outputs data signal
`DQ and strobe signal DQS with respective edges coincident
`30 with each other. In this case, interface circuit 5 delays the
`phase of strobe signal DQS by 90 degrees (1/4 period) so that
`data is sampled at both the rising edge and the falling edge
`of strobe signal DQS. On the contrary, when data is written
`from interface circuit 5 into DRAM device 2, interface
`35 circuit 5 outputs strobe signal DQS to DRAM device 2 with
`the edge of strobe signal DQS located at the center of a data
`eye.
`Memory controller 4 is connected to interface circuit 5
`and also to CPU 3 through a bus 8. Memory controller 4
`40 controls the operation of interface circuit 5 in accordance
`with instructions from CPU 3. Specifically, memory con-
`troller 4 outputs, to interface circuit 5, a command, an
`address, write data, and a signal for operation setting, for
`example, and receives read data from interface circuit 5.
`45 Memory controller 4 further outputs an offset setting value
`14 to an offset adjustment circuit 26 (described later herein
`in connection with FIG. 2) provided in interface circuit 5.
`PLL circuit 6 generates a reference clock, and clock
`generator 7 generates a system clock CK based on the
`so reference clock which is output from PLL circuit 6. The
`operations of PLL circuit 6 and clock generator 7 are
`controlled by control signals 11, 12 from CPU 3. Accord-
`ingly, the frequency of system clock CK is set. The gener-
`ated system clock CK is supplied to each part (such as CPU
`55 3, memory controller 4, and interface circuit 5) of semicon-
`ductor device 1. Interface circuit 5 supplies an operation
`clock of DRAM device 2 based on system clock CK. Thus,
`the operation frequency of DRAM device 2 is determined in
`accordance with the set frequency of system clock CK.
`Information regarding the set frequency of system clock
`CK (clock information) 13 is supplied from clock generator
`7 to memory controller 4. In memory controller 4, a con-
`version table 4A is stored for converting the set frequency of
`system clock CK (operation frequency of DRAM device 2)
`65 into the offset setting value 14. Based on conversion table
`4A, memory controller 4 determines the offset setting value
`14 corresponding to the set frequency, and outputs the
`
`60
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 21
`
`

`

`US 9,536,579 B2
`
`5
`determined offset setting value 14 to offset adjustment
`circuit 26 in FIG. 2 provided in interface circuit 5.
`[Configuration and General Operation of Interface Circuit
`5]
`FIG. 2 is a block diagram showing a part of the configu-
`ration of interface circuit 5 in FIG. 1. FIG. 2 shows the
`configuration of interface circuit 5 in FIG. 1, particularly the
`configuration relevant to reading of data from DRAM device
`2. FIG. 2 further shows memory controller 4 in FIG. 1 as
`well as terminals 20 and 21 through which data signal DQ
`and strobe signal DQS are input/output, respectively.
`Referring to FIG. 2, interface circuit 5 includes input/
`output (I/O) buffer amplifiers 22, 23, a selector circuit 24, a
`DQS delay circuit 25, a data detection circuit 28, an offset
`control circuit 30, and a calibration control circuit 31.
`Data signal DQ which is input to terminal 20 from DRAM
`device 2 in FIG. 1 is input through buffer amplifier 22 to data
`detection circuit 28. Strobe signal DQS which is input to
`terminal 21 from DRAM device 2 is input through buffer
`amplifier 23 to selector circuit 24.
`While interface circuit 5 performs a normal operation,
`selector circuit 24 selects strobe signal DQS which has been
`input through buffer amplifier 23 and outputs strobe signal
`DQS to DQS delay circuit 25 in the subsequent stage. In
`contrast, while interface circuit 5 performs a calibration
`operation, selector circuit 24 outputs a pulse signal which is
`output from calibration control circuit 31, to DQS delay
`circuit 25 in the subsequent stage.
`The above-described operation modes (normal mode and
`calibration mode) of interface circuit 5 and the selecting
`operation of selector circuit 24 in accordance with the
`operation mode are controlled by memory controller 4. In
`the calibration mode, the delay amount of DQS delay circuit
`25 is adjusted. In the normal mode, strobe signal DQS is
`delayed by the delay amount adjusted in the calibration
`mode.
`DQS delay circuit 25 is provided for delaying the phase
`of strobe signal DQS by 90 degrees (1/4 wavelength). DQS
`delay circuit 25 includes an offset adjustment circuit (first
`adjustment circuit) 26 and a delay amount adjustment circuit
`(second adjustment circuit) 27 connected in series to each
`other. Offset adjustment circuit 26 is capable of making a
`coarse adjustment, in multiple steps, of the delay amount of
`strobe signal DQS, in accordance with the offset setting
`value 14 (corresponding to the set frequency of system clock
`CK). Delay amount adjustment circuit 27 is capable of
`making a fine adjustment, with a higher precision than offset
`adjustment circuit 26, of the delay amount of strobe signal
`DQS, in accordance with a delay code 41 which is output
`from calibration control circuit 31. The order in which offset
`adjustment circuit 26 and delay amount adjustment circuit
`27 are connected to each other may be reversed relative to
`that shown in FIG. 2, namely offset adjustment circuit 26
`may be in the stage subsequent to delay amount adjustment
`circuit 27.
`Data detection circuit 28 receives data signal DQ and
`strobe signal DQS90 having been delayed by DQS delay
`circuit 25. Data detection circuit 28 samples data signal DQ
`at both timings of the rising edge and the falling edge of
`strobe signal DQS90 having been delayed.
`FIG. 3 is a diagram schematically showing respective
`waveforms of strobe signal DQS, data signal DQ, and strobe
`signal DQS90 which has been delayed.
`Referring to FIGS. 2 and 3, data signal DQ which is input
`from DRAM device 2 in FIG. 1 has edges (time tl, t3, t5, t7)
`that coincide with the edges of strobe signal DQS. DQS
`delay circuit 25 delays strobe signal DQS90 by a 1/4 period
`
`6
`(a phase of 90 degrees). Data detection circuit 28 samples
`data signal DQ based on the delayed strobe signal DQS90
`which is output from DQS delay circuit 25 in FIG. 2.
`Accordingly, data detection circuit 28 can take each of data
`5 DO, Dl, D2, D3 at the central position (time t2, t4, t6, t8) of
`a data eye.
`Referring again to FIG. 2, offset control circuit 30 outputs,
`to offset adjustment circuit 26, the offset setting value 14
`corresponding to the set frequency of system clock CK. As
`10 described above, the correlation between the set frequency
`of system clock CK (the operation frequency of DRAM
`device 2 in FIG. 1) and the offset setting value 14 is stored
`in the form of conversion table 4A in memory controller 4.
`The offset setting value 14 based on conversion table 4A is
`15 input to offset adjustment circuit 26. The delay amount of
`offset adjustment circuit 26 is determined in accordance with
`the offset setting value 14.
`After the delay amount of offset adjustment circuit 26 is
`set in accordance with the offset setting value 14, calibration
`20 control circuit 31 adjusts, in the calibration mode, the delay
`amount of delay amount adjustment circuit 27 so that the
`delay amount of DQS delay circuit 25 as a whole is identical
`to a target delay (specifically 1/4 of the period corresponding
`to the operation frequency of DRAM device 2) which is
`25 determined in accordance with system clock CK.
`Specifically, calibration control circuit 31 includes a sig-
`nal processing unit 33 having a pulse generator 34 and a
`phase comparator 35, as well as a control module 32. Clock
`signal CLKa acts as a trigger to cause pulse generator 34 to
`30 generate one-shot pulse. Phase comparator 35 compares the
`phase of delayed pulse DQS90 resulting from the pulse
`which is output from pulse generator 34 and passes through
`DQS delay circuit 25, with the phase of clock signal CLKb.
`Pulse generator 34 and phase comparator 35 can each be
`35 formed by a D flip-flop (F/F). A D flip-flop which forms
`pulse generator 34 is herein also referred to as launch flip
`flop (F/F), and a D flip-flop which forms phase comparator
`35 is herein also referred to as capture flip-flop (F/F).
`The phase of clock signal CLKb is adjusted so that it is
`40 delayed by 90 degrees relative to the phase of clock signal
`CLKa. Clock signals CLKa, CLKb may be supplied from
`clock generator 7 in FIG. 1 or generated by interface circuit
`5 based on system clock CK. System clock CK may be used
`as clock signal CLKa.
`In the calibration mode, control module 32 adjusts delay
`code 41 based on the result of comparison by phase com-
`parator 35, so that the phase of delayed pulse DQS90 which
`is output from DQS delay circuit 25 and the phase of clock
`signal CLKb coincide with each other. Delay code 41
`so corresponds to the delay amount of delay amount adjustment
`circuit 27.
`FIG. 4 is a diagram schematically showing respective
`waveforms of clock signals CLKa, CLKb and delayed pulse
`DQS90.
`Referring to FIGS. 2 and 4, the phase of clock signal
`CLKb is delayed by 90 degrees relative to the phase of clock
`signal CLKa. Namely, clock signal CLKb rises at t2 delayed
`by a phase of 90 degrees relative to time tl at which clock
`signal CLKa rises.
`The phase of the output pulse from pulse generator 34
`coincides with the phase of clock signal CLKa. Meanwhile,
`the phase of delayed pulse DQS90 which is output from
`DQS delay circuit 25 is delayed, in accordance with delay
`code 41, relative to the output pulse from pulse generator 34.
`Phase comparator 35 compares the phase of delayed pulse
`DQS90 with the phase of clock signal CLKb. In the case of
`FIG. 4, the output of phase comparator 35 is determined in
`
`45
`
`55
`
`60
`
`65
`
`Micron Technology Inc. et al.
`Ex. 1034, p. 22
`
`

`

`US 9,536,579 B2
`
`7
`accordance with the logic level of delayed pulse DQS90 at
`time t2. When the delay amount of delay amount adjustment
`circuit 27 is relatively small, the output of phase comparator
`35 is high level (H level). In contrast, when the delay amount
`of delay amount adjustment circuit 27 is relatively l