(19) United States
`(12) Patent Application Publication (10) Pub. No.: US 2007/0008791 A1
`Butt et al.
`(43) Pub. Date:
`Jan. 11, 2007
`
`US 2007000 8791A1
`
`(54) DQS STROBE CENTERING (DATA EYE
`TRAINING) METHOD
`
`(75) Inventors: Derrick Sai-Tang Butt, San Leandro,
`CA (US); Hui-Yin Seto, San Jose, CA
`(US)
`
`Correspondence Address:
`LSI LOGC CORPORATION
`1621 BARBER LANE
`MS: D-106
`MILPITAS, CA 95035 (US)
`
`(73) Assignee: LSI LOGIC CORPORATION
`
`(21) Appl. No.:
`
`11/176,041
`
`(22) Filed:
`
`Jul. 7, 2005
`
`
`
`Publication Classification
`
`(51) Int. Cl.
`(2006.01)
`GITC 7700
`2006.O1
`GLIC 8/00
`308:
`G06F 3/00
`(2006.01)
`G06F 3/28
`(2006.01)
`G06F 12/00
`(2006.01)
`G06F L/12
`(2006.01)
`H04L 700
`(2006.01)
`G06F 3/42
`(2006.01)
`H04L 5/00
`(52) U.S. Cl. ......................... 365/193; 365/194; 365/233;
`711/167; 713/401
`
`ABSTRACT
`(57)
`A method for calibrating a data valid window including the
`steps of: (A) setting a base delay of one or more datapaths
`to a predetermined value. (B) determining an optimum offset
`delay value for each of the one or more datapaths based upon
`actual memory accesses and (C) delaying a read data strobe
`signal based upon the base delay and the optimum offset
`delay value for each of the one or more datapaths.
`
`108
`I/O BUFFERS
`
`8
`
`DDR PHY
`
`1
`DR PDQ OUT
`CDR NDa out
`ASYNC
`FIFO C PDas out
`NDQSOUT
`DR PDQ OUT
`C DR NDQ OUT
`ASYNC
`FFO C PDQS OUT
`NDCRS OUT
`
`4.
`
`PHY
`OP
`
`PHY
`DP
`
`GATEON (TO
`EACHDP)
`
`114
`DR PDQ OUT
`DR NDOR OUT
`PHY
`-
`ASYNC C
`PDQSOUT | DP
`FIFO
`C NDas out
`BASE DELAY
`MASTER (TO EACHDP)
`DELAY
`MDELAY DOSINTN
`LOCK (FROMEACH
`DP)
`RD GATE
`
`CONTROL
`
`GATEON
`CIRCUIT
`
`e
`T
`3.
`O
`-
`c
`O
`2
`-
`O
`-
`-
`t
`
`MC X4 MEM SEL
`
`N PRPDO
`a
`N P R NDQ
`P R VALID
`
`CLK 1X
`
`MC CMD
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 1
`
`

`

`Patent Application Publication Jan. 11, 2007 Sheet 1 of 8
`
`US 2007/0008791 A1
`
`100
`
`
`
`MEMORY
`CONTROLLER
`
`DO
`
`IO
`BUFFERS
`
`DDR
`DOS SDRAM
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 2
`
`

`

`8JO7904SLOOT‘TT“UREUOHvITGngUOHRdTddyJude
`
` 108~
`
`DDR PHY
`
`DR_PDQ_OUT \
`DR_NDQ_OUT
`
`VO BUFFERS
`
`MC_X4_MEM_SEL
`
`AYOWSWYad
`
`N,
`
`N,.
`
`PLR_PDQ
`
`PILR_NDQ
`
`PI_R_VALID
`
`DR_NDQ_OUT
`
`PDQS_OUT
`NDQS_OUT
`
`PHY
`DP
`
`=m=O
`
`Q
`aD
`
`<QO
`
`oz4aO
`
`oec
`rc
`mM
`Dd
`
`MC_CMD
`
`117
`
`DQS_INTN
`(FROM EACH
`DP)
`RD_GATE
`
`GATEON
`CIRCUIT
`
`FIG. 2
`
`TV1628000/L007SN.
`
`BASE_DELAY
`CLK_1X
`GATEON (TO
`MASTER|(TO EACH DP)
`DELAY
`EACH DP)
`MDELAY
`Lock
`=
`CONTROL
`
`PHY
`PDQS_OUT|pp
`NDQS_OUT
`
`
`
`
`
`
`
`
`
`
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 3
`
`

`

`Patent Application Publication Jan. 11, 2007 Sheet 3 of 8
`
`US 2007/0008791 A1
`
`
`
`114
`
`120a
`
`- -
`
`DR PDQ OUT7:4)
`
`121 a
`
`(7:4)
`
`DQ (READ DATA)
`
`PDQS OUT UN
`
`C
`
`-1
`STORED SLAVE
`DELAY ADJUSTMENT
`
`7
`
`124a -122a
`-
`
`DOS INTN UN
`
`DR NDQ OUT7:4
`
`125a
`
`7:4)
`
`BASE DELAY UN
`
`OFFSET P UN
`
`DOS/DQS UN
`GATEON UN
`
`DQ (READ DATA)
`
`BASE DELAY UN
`
`OFFSET N UN
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 4
`
`

`

`Patent Application Publication Jan. 11, 2007 Sheet 4 of 8
`
`US 2007/000.8791 A1
`
`
`
`114
`120b N.
`DR PDQ OUT3:O
`
`PDOS OUT LN
`
`121b.
`
`3:0
`
`C
`
`74 1
`
`STORED SLAVE
`DELAY ADJUSTMENT
`
`DQS INTN LN
`
`-
`
`DQ (READ DATA)
`
`124b -122b
`
`BASE DELAYLN
`
`OFFSET PLN
`
`DOS/DOS LN
`GATEONLN
`
`DR NDQ OUT3:0)
`
`DQ (READ DATA)
`
`BASE DELAY LN
`
`OFFSET_N.LN
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 5
`
`

`

`
`
`
`
`TV1628000/L007SN.
`
`VALID DATA E
`
`YE WINDOW
`
`MIN
`
`oe,
`
`Ss>x<
`
`WG
`
`|
`
`|
`
`I
`
`lIIl
`
`CK/CK#
`
`||
`
`pa f
`
`DQS
`
`INCREMENT DELAY
`
`| ||
`
`EARLY DELAYED DQS
`
`|l|
`
`|
`
`CORRECT DELAYED DQS
`
`LATE DELAYED DQS
`
`140
`
`144
`
`Ch
`
`Ch
`
`142
`
`CASE 1: DELAYED DQS IS
`EARLIER THAN THE MIN.
`‘BOUNDARYOF VALID
`DATA EYE WINDOW
`
`CASE 2: DELAYED
`DQS IS WITHIN VALID
`DATA EYE WINDOW
`
`CASE 3: DELAYED DQSIS
`LATER THAN THE MAX.
`BOUNDARYOF VALID
`DATA EYE WINDOW
`
`—O
`
`O
`
`YY
`
`DECREMENT DELAY*———
`
`FIG. 4
`
`CLOCKCYCLES |—1; —_}|__ 2 __| __3__| _, —|
`
`
`
`
`
`
`
`8JOS1904SLOOT‘TT“UREUOHvITGngUOHedTddyJude
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 6
`
`

`

`Patent Application Publication Jan. 11, 2007 Sheet 6 of 8
`
`US 2007/0008791 A1
`
`200 N
`
`202
`
`
`
`SET BASE DELAYS
`FOR DATAPATHS AND
`SET OFFSET DELAY-O
`FOREACH DATAPATH
`
`DETERMINE MAXIMUM -
`OFFSET DELAY FOR
`EACH DATAPATH
`
`DETERMINE MINIMUM
`OFFSET DELAY FOR
`EACH DATAPATH
`
`DETERMINE OPTIMUM
`OFFSET DELAY FOR
`EACH DATAPATH
`
`204
`
`2O6
`
`208
`
`FIG. 5
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 7
`
`

`

`Patent Application Publication Jan. 11, 2007 Sheet 7 of 8
`
`US 2007/0008791 A1
`
`204 N
`
`220
`
`PROGRAM DP WITH
`PREDETERMINED
`OFFSET DELAY VALUES
`
`TEST MEMORYACCESS
`
`INCREMENT
`OFFSET DELAY
`VALUE
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`234
`
`
`
`TEST NEXT DP
`
`
`
`LAST
`DELAY
`VALUE
`
`
`
`
`
`SET MAXIMUM VALUE TO
`LAST VALUE TO PASS
`MEMORY TEST
`
`
`
`FIG. 6
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 8
`
`

`

`Patent Application Publication Jan. 11, 2007 Sheet 8 of 8
`
`US 2007/0008791 A1
`
`206 N
`
`240
`
`
`
`PROGRAM DP WITH
`PREDETERMINED
`OFFSET DELAY VALUES
`
`242
`
`TEST MEMORY ACCESS
`
`TEST PASSED?
`
`DECREMENT
`OFFSET DELAY
`VALUE
`
`LAST
`DELAY
`VALUE2
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`
`254
`
`TEST NEXT DP
`
`
`
`
`
`SET MNIMUM VALUE TO
`LAST VALUE TO PASS
`MEMORY TEST
`
`FIG. 7
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 9
`
`

`

`US 2007/000 8791 A1
`
`Jan. 11, 2007
`
`DQS STROBE CENTERING (DATA EYE
`TRAINING) METHOD
`CROSS REFERENCE TO RELATED
`APPLICATIONS
`0001. The present application may relate to co-pending
`U.S. application Ser. No. 11/097,903, filed Apr. 1, 2005,
`U.S. application Ser. No. 11/154.401, filed Jun. 16, 2005,
`U.S. application Ser. No.
`(Attorney Docket No.
`1496.00415/04-2000), filed Jun. 24, 2005, and U.S. appli
`cation Ser. No.
`(Attorney Docket No. 1496.00419/
`04-2044), filed Jul. 1, 2005, which are each hereby incor
`porated by reference in their entirety.
`FIELD OF THE INVENTION
`0002 The present invention relates to memory systems
`generally and, more particularly, to a method and/or appa
`ratus DQS Strobe centering (or data eye training) that may be
`suitable for a DDR memory application.
`BACKGROUND OF THE INVENTION
`0003) A double data rate (DDR) synchronous dynamic
`random access memory (SDRAM) interface receives
`aligned data (DQ) and read data strobe (DQS) signals from
`a DDR SDRAM device. The DDR SDRAM interface is
`responsible for providing the appropriate DQ-DQS relation
`ship. A conventional approach performs system-level timing
`analysis using a simulation program for integrated circuit
`emphasis (SPICE) to determine a timing that yields adequate
`setup and hold time margin within a data valid window. The
`conventional approach is not programmable and can vary for
`different hardware implementations. The conventional
`approach does not calibrate the actual data valid window in
`silicon. The conventional approach relies heavily on the
`pre-silicon, system-level, SPICE timing analysis.
`0004. It would be desirable to have a read data strobe
`centering (or data eye training) method for calibrating the
`actual data valid window.
`
`SUMMARY OF THE INVENTION
`0005 The present invention concerns a method for cali
`brating a data valid window comprising the steps of: (A)
`setting a base delay of one or more datapaths to a predeter
`mined value, (B) determining an optimum offset delay value
`for each of the one or more datapaths based upon actual
`memory accesses and (C) delaying a read data strobe signal
`based upon the base delay and the optimum offset delay
`value for each of the one or more datapaths.
`0006 The objects, features and advantages of the present
`invention include providing a method for read data strobe
`centering (data eye training) that may (i) provide a system
`atic process for calibrating the center of a data valid window,
`(ii) enable an upper level memory controller function to
`perform run time calibration of the data valid window, (iii)
`be flexible and adaptable to various different system imple
`mentations, and/or (iv) eliminate reliance on a system level.
`pre-silicon, SPICE timing analysis on the data valid window.
`BRIEF DESCRIPTION OF THE DRAWINGS
`0007. These and other objects, features and advantages of
`the present invention will be apparent from the following
`detailed description and the appended claims and drawings
`in which:
`
`0008 FIG. 1 is a block diagram illustrating a memory
`system in which an embodiment of the present invention
`may be implemented;
`0009 FIG. 2 is a more detailed block diagram of a read
`data logic and signal paths of a memory interface of FIG. 1;
`0010 FIG. 3 (A-B) are more detailed block diagrams
`illustrating details of read data latching and gating;
`0011 FIG. 4 is a timing diagram illustrating various data
`and strobe signals of a DDR SDRAM interface;
`0012 FIG. 5 is a flow diagram illustrating a training
`process in accordance with a preferred embodiment of the
`present invention;
`0013 FIG. 6 is a more detailed flow diagram illustrating
`a process for determining a maximum offset delay value; and
`0014 FIG. 7 is a more detailed flow diagram of a process
`for determining a minimum offset delay value.
`
`DETAILED DESCRIPTION OF THE
`PREFERRED EMBODIMENTS
`0015 Referring to FIG. 1, a block diagram is shown
`illustrating a system 100 in which one or more preferred
`embodiments of the present invention may be implemented.
`In one example, the system 100 may comprise a circuit (or
`block) 102, a circuit (or block) 104, a circuit (or block) 106
`and a circuit (or block) 108. The circuit 102 may be
`implemented as a memory controller. The circuit 104 may be
`implemented as a memory interface. In one example, the
`circuit 104 may be implemented as a double data rate (DDR)
`physical layer (PHY) core. The circuit 106 may be imple
`mented as one or more double data rate (DDR) synchronous
`dynamic random access memory (SDRAM) devices. The
`circuit 108 may be implemented, in one example, as stub
`series terminated logic (SSTL) IO buffers. The circuit 104
`may be coupled between the circuit 102 and the circuit 106.
`In one example, the circuit 104 may be coupled to the circuit
`106 by the circuit 108. The circuit 104 may be configured to
`receive a plurality of data signals (e.g., DQ) and a plurality
`of read data strobe signals (e.g., DQS). In one example, the
`plurality of read data strobe signals may comprise a single
`read data strobe for each byte of the signals DQ. In another
`example (e.g., an X4 mode), the plurality of data strobe
`signals DQS may comprise a separate strobe signal (e.g.,
`DQS UN and DQS LN, respectively) for each nibble (e.g.,
`upper and lower) of the signal DQ.
`0016.
`In one example, the circuits 102, 104 and 108 may
`be implemented (or instantiated) on an application specific
`integrated circuit (ASIC) 110. However, the circuit 102 may
`be implemented separately and mounted on a common
`printed circuit board (PCB) along with the circuits 104, 106
`and 108. The ASIC 110 may be implemented, in one
`example, as a platform (or structured) ASIC. In one
`example, the circuit 104 may be implemented based on
`diffused datapath (DP) and master delay modules. In another
`example, the circuit 104 may be implemented based on
`R-cell datapath and master delay modules. In one example,
`the circuit 104 may be implemented in an R-cell transistor
`fabric of the ASIC 110. As used herein, R-cell generally refer
`to an area of silicon containing one or more diffusions for
`forming the parts of N and/or P type transistors and the
`contact points where wires may be attached in Subsequent
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 10
`
`

`

`US 2007/000 8791 A1
`
`Jan. 11, 2007
`
`manufacturing steps (e.g., to power, ground, inputs and
`outputs). Wire layers may be added to the R-cell transistor
`fabric to make particular transistors, logic gates, soft and
`firm IP blocks and/or storage elements.
`0017 Referring to FIG. 2, a more detailed block diagram
`of the circuit 104 is shown illustrating example read data
`logic and signal paths in which a preferred embodiment of
`the present invention may be implemented. In one example,
`the circuit 104 may comprise a number of asynchronous
`(ASYNC) first-in first-out (FIFO) buffers 112, FIFO syn
`chronization logic 113, a number of physical read datapaths
`(DPs) 114, a master delay (MDELAY) logic 116, a control
`logic 117 and a programmable gating signal generator 118.
`Each of the physical read datapaths 114 may be configured
`to receive (i) a respective portion of the read data signals DQ
`from the DDR memory 106, (ii) a respective read data strobe
`signal or signals DQS associated with the respective portion
`of the received read data signals and (iii) a gating signal
`(e.g., GATEON) from the programmable gating signal gen
`erator 118. Each of the physical read datapaths 114 may
`communicate with a corresponding one of the asynchronous
`FIFOs 112 via a number of signals (e.g., DR PDQ OUT.
`DR NDQ OUT, PDQS OUT, and NDQS OUT). In one
`example, separate signals (e.g., PDQS OUT UN, NDQ
`S OUT UN, PDQS OUT LN, and NDQS OUT LN) may
`be generated for each nibble of the DPs 114. In one example,
`the asynchronous FIFOs 112 may be configured to interface
`the physical read datapaths 114 with the memory controller
`102.
`0018. In general, the signals DQ and DQS may be
`presented to the DDR PHY 104 on a number of buses. The
`signals DQ and DQS may be broken out to multiple instan
`tiations of DP hardmacros. The DPs may be configured via
`internal settings to delay the read data strobe signals DQS
`based on one or more control signals (or values) from the
`MDELAY circuit 116. Each of the DPs 114 may be config
`ured to present the DQ data to a respective asynchronous
`FIFO 112 via
`the
`signals DR PDQ OUT and
`DR NDQ OUT, after the data is sampled using the delayed
`read data strobe signals DQS.
`0019. The FIFOs 112 are generally configured to transfer
`the read data DQ from the read data strobe (or DQS) domain
`to the CLK 1X domain for presentation to the memory
`controller 102. The read data DR PDQ OUT and
`DR NDQ OUT are generally written to the FIFOs 112 in
`response to (e.g., clocked by) the signals PDQS OUT and
`NDQS OUT, respectively). The memory controller 102
`may be configured to read the data DQ (e.g., via signals
`PI R PDQ and P R NDQ) from the FIFOs 112 in
`response to the clock signal CLK 1X. In one example, the
`FIFOs 112 may be implemented as eight words deep.
`0020. As briefly described above, the read datapaths 114
`are generally programmable from when the data/strobe pairs
`DQ/DQS are received at the input to the circuit 104, to
`sampling the read data with the read data Strobe signal DQS,
`and passing the data to the memory controller 102. The
`programmability of the read datapaths 114 generally pro
`vides flexibility for handling different column address strobe
`(CAS) latencies, burst lengths, device process variation,
`and/or propagation delays.
`0021. The master delay (MDELAY) logic 116 is gener
`ally configured to calculate a delay value for generating a
`
`one-quarter cycle or one-fifth cycle delay with respect to the
`device reference clock (e.g., the signal CLK 1X). The
`calculated delay is generally used by the datapaths 114 to
`center a read data capture clock (e.g., the signal DQS) in a
`valid DDR device read data window. The calculated delay
`generally tracks process, Voltage and temperature (PVT)
`corners for reliable read data latching. The MDELAY logic
`116 may be configured to generate the one-quarter cycle or
`one-fifth cycle delay using a delay lock loop (DLL). Once
`the DLL is locked to the clock signal CLK 1X, a signal
`(e.g., MDELAY LOCK) may be generated indicating the
`locked state. The signal MDELAY LOCK may be presented
`to an input of the control logic 117 and/or the memory
`controller 102.
`0022. The MDELAY logic 116 may be configured to
`generate one or more control signals (or values) for trans
`ferring the delay settings (or values) to one or more slave
`delay cells (describe in more detail in connection with FIGS.
`3A and 3B) in each of the DPs 114. The delay values, when
`transferred to each of the DPs 114, are generally referred to
`as base delays. In one example, a base delay may be
`implemented for each nibble of each DP byte. For example,
`a first base delay value (e.g., BASE DELAY UN) may be
`implemented for each upper nibble and a second base delay
`value (e.g., BASE DELAY LN) may be implemented for
`each lower nibble. The DPs 114 may also be programmed
`with offset delay values corresponding to each nibble (e.g.,
`OFFSET P UN, OFFSET N UN, OFFSET PLN and
`OFFSET N LN). In one example, each of the DPs 114 may
`have a set of base delays that are independent of the other
`DPs 114. The offset delay values may be added to or
`subtracted from the respective base delay values.
`0023 The control circuit 117 may be configured to gen
`erate one or more control signals for controlling and/or
`configuring the FIFOs 112 and datapaths 114. In one
`example, the control circuit 117 may be configured to
`generate a gating signal (e.g., RD GATE) in response to a
`signal (e.g., MC CMD) received from the controller 102. In
`one example, the circuit 117 may be configured to generate
`the signal RD GATE in response to decoding a READ
`command in the signal MC CMD. The signal RD GATE is
`generally configured to prevent invalid states (e.g., when
`DQS is in a 3-state, or OFF, mode) from entering the circuit
`113. The signal RD GATE may be used to generate one or
`more gating signals.
`0024. The programmable gateon generating circuit 118
`may be configured to generate the signal GATEON in
`response to the signal RD GATE, a first clock signal (e.g.,
`CLK 1X), a second clock signal (e.g., CLK 2X) and a data
`strobe signal (e.g., DQS INTN) received from the DPs 114.
`The signal GATEON may be used to gate the read data
`strobe signal DQS received from the memory device 106. In
`one example, separate gating signals (e.g., GATE.ON UN,
`GATEON LN, etc.) may be generated for each nibble of the
`DPs 114. The signal DQS INTN may be used to de-assert
`the signal GATEON. In one example, separate signals (e.g.,
`DQS INTN UN and DQS INTN LN) may be generated
`for each nibble of the DPs 114. Although the circuit 118 is
`shown implemented separately from the DPs 114, it will be
`understood by those skilled in the art that the circuit 118 may
`be implemented as part of the DPs 114 (e.g., the signal
`GATEON may be generated within the DPs 114 or external
`to the DPs 114).
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 11
`
`

`

`US 2007/000 8791 A1
`
`Jan. 11, 2007
`
`0025 Referring to FIGS. 3(A-B), more detailed block
`diagrams of a datapath 114 of FIG. 2 are shown illustrating
`an example read data latching and gating circuit in accor
`dance with a preferred embodiment of the present invention.
`In one example, each datapath 114 may comprise an upper
`nibble pathway 120a (FIG. 3A) and a lower nibble pathway
`120b (FIG. 3B). The upper nibble pathway 120a may have
`a first input that may receive a number of bits of the signal
`DQ (e.g., bits 7:4), a second input that may receive the signal
`BASE DELAY UN, a third input that may receive the
`signal OFFSET P UN, a fourth input that may receive the
`signal OFFSET N UN, a fifth input that may receive the
`signal DQS (or the signal DQS UN in the X4 mode), a sixth
`input that may receive a signal (e.g., GATE.ON UN). The
`upper nibble pathway 120a may also have a first output that
`may present a number of bits (e.g., the signal DR P
`DQ OUTT:4), a second output that may present a number
`of bits (e.g., the signal DR NDQ OUTT:4), a third output
`that may present a signal (e.g., PDQS OUT UN), a fourth
`output that may present a signal (e.g., NDQS OUT UN)
`and a fifth output that may present a signal (e.g., DQS INT
`N UN).
`0026. The upper nibble pathway 120a may comprise a
`circuit (or block) 121a, a circuit (or block) 122a, a circuit (or
`block) 123a, a circuit (or block) 124a, a circuit (or block)
`125a, a circuit (or block) 126a, a circuit (or block) 127a and
`a circuit (or block) 128a. The circuit 121a may be imple
`mented as one or more registers. The circuit 122a may be
`implemented as an adder block. The circuit 123a may be
`implemented as a multiplexercircuit. The circuit 124a may
`be implemented as a slave delay adjustment block. The
`circuit 125a may be implemented as one or more registers.
`The circuit 126a may be implemented as an adder block. The
`circuit 127a may be implemented as an inverter circuit. The
`circuit 128a may be implemented as a slave delay adjust
`ment block.
`0027. The circuit 121a may be configured to latch an
`upper nibble (e.g., bits 7:4) of the read data signal DQ in
`response to a clock input. The circuit 121a may be further
`configured to present the latched read data as the signal
`DR PDQ OUTT:4). The circuit 122a may be configured to
`generate a sum (or difference) of the signals BASE DELA
`Y UN and OFFSET P UN. The circuit 123a may be con
`figured to select either the signal DQS (or the signal
`DQS UN in the X4 mode) or a predetermined logic level
`(e.g., a LOW or logic 0) in response to the signal GATEO
`N UN. The circuit 124a may be configured to delay the
`signal presented by the circuit 123a based on the sum (or
`difference) generated by the circuit 122a. An output of the
`circuit 124a may present the signal PDQS OUT UN to the
`clock input of the circuit 121a and the third output of the
`upper nibble pathway 120a.
`0028. The circuit 125a may be configured to latch an
`upper nibble (e.g., bits 7:4) of the read data signal DQ in
`response to a clock input. The circuit 125a may be further
`configured to present the latched read data as the signal
`DR NDQ OUTT:4). The circuit 126a may be configured
`to generate a sum (or difference) of the signals BASE DE
`LAY UN and OFFSET. UN. The circuit 127a may be
`configured to generate the signal DQS INTN UN as a
`digital complement of the signal presented by the circuit
`123a. The signal DQS INTN UN may be presented to an
`input of the circuit 128a and the fifth output of the upper
`
`nibble pathway 120a. The circuit 128a may be configured to
`generate the signal NDQS OUT UN by delaying the signal
`DQS INTN UN based on the sum (or difference) generated
`by the circuit 126a. An output of the circuit 128a may
`present the signal NDQS OUT UN to the clock input of the
`circuit 125a and the fourth output of the upper nibble
`pathway 120a.
`0029. The lower nibble pathway 120b may have a first
`input that may receive a number of bits (e.g., bits 3:0) of the
`signal DQ, a second input that may receive the signal
`BASE DELAY LN, a third input that may receive the
`signal OFFSET P LN, a fourth input that may receive the
`signal OFFSET N LN, a fifth input that may receive the
`signal DQS (or the signal DQS LN in the x4 mode), a sixth
`input that may receive a signal (e.g., GATEON LN). The
`lower nibble pathway 120b may also have a first output that
`may present a number of bits (e.g., the signal DR P
`DQ OUT3:0), a second output that may present a number
`of bits (e.g., the signal DR NDQ OUT3:0), a third output
`that may present the signal PDQS OUT LN, a fourth output
`that may present the signal NDQS OUT LN and a fifth
`output that may present the signal DQS INTN LN.
`0030) The lower nibble pathway 120b may comprise a
`circuit (or block) 121b, a circuit (or block) 122b, a circuit (or
`block) 123b, a circuit (or block) 124b, a circuit (or block)
`125b, a circuit (or block) 126b, a circuit (or block) 127b and
`a circuit (or block) 128b. The circuit 121b may be imple
`mented as one or more registers. The circuit 122b may be
`implemented as an adder block. The circuit 123b may be
`implemented as a multiplexercircuit. The circuit 124b may
`be implemented as a slave delay adjustment block. The
`circuit 125b may be implemented as one or more registers.
`The circuit 126b may be implemented as an adder block. The
`circuit 127b may be implemented as an inverter circuit. The
`circuit 128b may be implemented as a slave delay adjust
`ment block.
`0031. The circuit 121b may be configured to latch a lower
`nibble (e.g., bits 3:0) of the read data signal DQ in response
`to a clock input. The circuit 121b may be further configured
`to present the latched read data as the signal DR PDQ OUT
`3:0). The circuit 122b may be configured to generate a sum
`(or difference) of the signals BASE DELAY LN and OFF
`SET P LN. The circuit 123b may be configured to select
`either the signal DQS (or the signal DQS LN in the X4
`mode) or a predetermined logic level (e.g., a LOW or logic
`O) in response to the signal GATEON LN. The circuit 124b
`may be configured to delay the signal presented by the
`circuit 123b based on the sum (or difference) generated by
`the circuit 122b. An output of the circuit 124b may present
`the signal PDQS OUT LN to the clock input of the circuit
`121b and the third output of the lower nibble pathway 120b.
`0032. The circuit 125b may be configured to latch a lower
`nibble (e.g., bits 3:0) of the read data signal DQ in response
`to a clock input. The circuit 125b may be further configured
`to present the latched read data as the signal
`DR NDQ OUT3:0). The circuit 126b may be configured
`to generate a sum (or difference) of the signals BASE DE
`LAY LN and OFFSET N LN. The circuit 127b may be
`configured to generate the signal DQS INTN LN as a
`digital complement of the signal presented by the circuit
`123b. The signal DQS INTN LN may be presented to an
`input of the circuit 128b and the fifth output of the lower
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 12
`
`

`

`US 2007/000 8791 A1
`
`Jan. 11, 2007
`
`nibble pathway 120b. The circuit 128b may be configured to
`generate the signal NDQS OUT LN by delaying the signal
`DQS INTN LN based on the sum (or difference) generated
`by the circuit 126b. An output of the circuit 128b may
`present the signal NDQS OUT LN to the clock input of the
`circuit 125b and the fourth output of the lower nibble
`pathway 120b.
`0033 Referring to FIG. 4, a timing diagram is shown
`illustrating various signals implemented in the interface
`between the physical interface 104 and the DDR SDRAM
`device 106. The circuit 104 generally receives aligned DQ
`and DQS signals from the DDR SDRAM device(s) 106. As
`used herein, the term data eye is generally used to refer to
`a characteristic appearance of the read data signal wave
`forms, on the DQ lines. The term read training generally
`refers to a process performed, for example, at powerup or
`reset, to establish optimum DQS strobe settings. The circuits
`124a, 124b, 128a and 128b within the datapath (DP) hard
`macro are generally configured to shift the DQS strobe to be
`optimally positioned relative to DQ (valid read data). In one
`example, the circuits 124a, 124b, 128a and 128b may be
`configured to shift the DQS strobe by one-quarter or one
`fifth cycle.
`0034. The present invention generally provides robust
`sampling of the read data over process, Voltage, and tem
`perature (PVT) variations. The present invention generally
`provides a systematic process for calibrating the center of
`the data valid window over process, Voltage and temperature
`(PVT) corners. A double data rate (DDR) synchronous
`dynamic random access memory (SDRAM) device gener
`ally implements source synchronous data transfer technol
`ogy where the data signal DQ and the related data strobe
`signal DQS are sent together by the transmitting device. Due
`to signal integrity and system implementation factors, a
`receive data valid window may be reduced to a certain extent
`(e.g., the shaded portions in the D0 and D1 regions of the
`signal DQ in FIG. 4). A receiving device implementing the
`present invention may realize an optimal timing for the read
`data strobe signal DQS.
`0035. The present invention generally provides for
`adjusting a delay of the read data Strobe signal DQS to
`approximately center the read data strobe signal DQS in the
`valid data eye window. For example, when the delay is too
`short, the read data strobe signal DQS is generally earlier
`than a minimum boundary of the valid data eye window
`(e.g., trace 140). When the delay is too great, the read data
`strobe signal DQS is generally later than a maximum
`boundary of the valid data eye window (e.g., trace 142). In
`general, a correctly set delay places the read data strobe
`signal DQS within the valid data eye window (e.g., trace
`144).
`0036) The present invention may be implemented in logic
`(e.g., hard intellectual property (IP), firm IP and/or soft IP)
`that may provide read data synchronization from the DQS
`domain on an external DDR SDRAM memory bus to a 1x
`clock domain (e.g., the signal CLK 1X) used by the DDR
`PHY 104 and the DDR memory controller 102. The read
`data strobe signal DQS may be used to clock in the read data.
`The present invention generally enables a reliable data read
`operation for high speed applications.
`0037 Referring to FIG. 5, a flow diagram is shown
`illustrating a process 200 in accordance with a preferred
`
`embodiment of the present invention. In one example, the
`process 200 may begin by setting base delays (e.g.,
`BASE DELAY LN and BASE DELAY UN) in each of
`the datapaths 114 to a predetermined initial value and setting
`offset delays (e.g., OFFSET PLN, OFFSET N LN, OFF
`SET P UN and OFFSET N UN) for each of the datapaths
`114 to zero (e.g., block 202). A write/read/compare test may
`be performed to verify that the memory device 106 may be
`read using the initial base delay and offset delay values.
`0038. In one example, the process of setting the initial
`base and offset delays may comprise the following steps:
`0039) 1. Verifying that the MDELAY (Master Delay)
`circuit 116 has achieved DLL lock. In one example,
`verification may be performed by reading a first bit
`(e.g., L or lock) and a second bit (e.g., LF or lock
`failure) in a register of the MDELAY circuit 116. If the
`verification fails (e.g., the L bit is not one or the LF bit
`is not zero), the MDELAY circuit 116 may be reset to
`recover from the failure condition.
`0040 2. Transferring MDELAY DQS delay control
`values (the base delay values) to the DPs 114. In one
`example, the base delay values may be transferred by
`writing to one or more registers.
`0041) 3. Setting a number of bits (e.g., base delay
`select bits) so the updated delay values may be loaded
`into the base delays of the DPs 114.
`0042. 4. Setting the offset delay values in the DPs 114
`to zero. In one example, the offset delay values in the
`DPs 114 may be set to Zero by using a control register.
`In one example, a number of offset delays (e.g., four)
`may be implemented for each DP114. The delay values
`may be initially set to zero after the reset.
`0043 5. Establishing pointers and storage locations for
`the minimum and maximum offset delay values to be
`determined by the process 200 and initializing the
`offset delay values appropriately (e.g., using signed
`2s-complement format). For example, an offset delay
`value may be implemented for each nibble of each DP
`byte, and for each nibble a positive-edge strobe offset
`and a negative-edge strobe offset may be implemented.
`For example, four offset delay values per DP114 may
`be implemented (e.g., OFFSET N LN, OFFSET
`P LN, OFFSET N UN and OFFSET P UN).
`0044) 6. Verifying that valid DDR data may be read
`with the delay offset values set to zero. For example, a
`routine may be executed that writes to, reads from, and
`compares a selected data pattern to a selected range of
`the DDR memory 106.
`If valid data cannot be read with the delay offset values set
`to Zero, the initial settings may not be sufficient. In one
`example, delay settings for the signal GATEON may be
`re-evaluated. However, high level system debugging
`may also be performed. In one example, a signal (e.g.,
`an error signal) may be generated to inform the user.
`0045. The process 200 generally continues by determin
`ing maximum offset delay values for each DP 114 (e.g.,
`block 204). For example, maximum upper and lower nibble
`offset delay values may be determined for each DP114 (e.g.,
`using a positive adjustment routine). When maximum offset
`delay values have been determined for each of the datapaths,
`
`Micron Technology Inc. et al.
`Ex. 1029, p. 13
`
`

`

`US 2007/000 8791 A1
`
`Jan. 11, 2007
`
`the process 200 generally determines minimum offset delay
`values for each DP 114 (e.g., the block 206). For example,
`minimum upper and lower nibble offset delay values may be
`determined for each DP 114 (e.g., using a negative adjust
`ment routine).
`0046) When both maximum and minimum offset delay
`values have been determined for each offset delay value of
`each of the DPs 114, the process 200 generally determines
`op