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`Provisional Application for Patent Cover Sheet
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`Hyun
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`Lee
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`Ladera Ranch CA
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`Title of Invention
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`MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND METHOD OF
`OPERATION
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`NT003
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`79141
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`The invention was made by an agency of the United States Government or under a contract with an agency of the United
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`C) No.
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`O Yes, the name of the U.S. Government agency and the Government contract number are:
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`EFS - Web 1.0.1
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`Micron Technology Inc. et al.
`Ex. 1025, p. 1
`
`

`

`Doc Code: TR.PROV
`Document Description: Provisional Cover Sheet (SB16)
`
`PTO/SB/16 (11-08)
`Approved for use through 01/31/2014 OMB 0651-0032
`U.S. Patent and Trademark Office: U.S. DEPARTMENT OF COMMERCE
`Under the Paperwork Reduction Act of 1995, no persons are required to respond to a collection of information unless it displays a valid OMB control number
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`Entity Status
`Applicant claims small entity status under 37 CFR 1.27
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`C) Yes, applicant qualifies for small entity status under 37 CFR 1.27
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`/Jamie J. Zheng/
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`Date (YYYY-MM-DD)
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`2012-07-27
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`Jamie
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`Zheng
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`51167
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`EFS - Web 1.0.1
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`Micron Technology Inc. et al.
`Ex. 1025, p. 2
`
`

`

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`Micron Technology Inc. et al.
`Ex. 1025, p. 3
`
`

`

`MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS AND
`
`METHOD OF OPERATION
`
`CROSS REFERENCE TO RELATED APPLICATIONS
`
`[0001] The present application is related to commonly-owned U.S. patent applications No.
`
`12/504,131, No. 12/761,179, No. 13/287,042, and No. 13/287,081, each of which is
`
`incorporated herein by reference in its entirety.
`
`FIELD
`
`[0002] The disclosure herein is related generally to memory modules, and more
`
`particularly to multi-rank memory modules and methods of operation.
`
`BACKGROUND
`
`[0003] With recent advancement of information technology and widespread use of the
`
`Internet to store and process information, more and more demands are placed on the
`
`acquisition, processing, storage and dissemination of vocal, pictorial, textual and numerical
`
`information by microelectronics-based combination of computing and communication
`
`means. In a typical computer or server system, memory modules are used to store data or
`
`information. A memory module usually includes multiple memory devices, such as
`
`dynamic random access memory devices (DRAM) or synchronous dynamic random access
`
`memory devices (SDRAM), packaged individually or in groups, and/or mounted on a
`
`printed circuit board (PCB). A processor or a memory controller accesses the memory
`
`module via a memory bus which, for a single-in-line memory module (SIMM), can have a
`
`32-bit wide data path, or for a dual-in-line memory module (DIMM), can have a 64-bit
`
`wide data path.
`
`[0004] The memory devices of a memory module are generally organized in ranks, with
`
`NT003
`
`1
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 4
`
`

`

`each rank of memory devices generally having a bit width. For example, a memory module
`
`in which each rank of the memory module is 64 bits wide is described as having an "x64"
`
`or "by 64" organization. Similarly, a memory module having 72-bit-wide ranks is described
`
`as having an "x72" or "by 72" organization.
`
`[0005] The memory capacity or memory density of a memory module increases with the
`
`number of memory devices on the memory module. The number of memory devices of a
`
`memory module can be increased by increasing the number of memory devices per rank or
`
`by increasing the number of ranks.
`
`[0006] In certain conventional memory modules, the ranks are selected or activated by
`
`control signals from a processor or memory controller during operation. Examples of such
`
`control signals include, but are not limited to, rank-select signals, also called chip-select
`
`signals. Most computer and server systems support a limited number of ranks per memory
`
`module, which limits the memory density of the memory modules that can be used in these
`
`computer and server systems.
`
`[0007] For memory devices in such as a memory module to be properly accessed,
`
`distribution of control signals and a control clock signal in the memory module is subject to
`
`strict constraints. In some conventional memory modules, control wires are routed so there
`
`is an equal length to each memory component, in order to eliminate variation of the timing
`
`of the control signals and the control clock signal between different memory devices in the
`
`memory modules. The balancing of the length of the wires to each memory devices
`
`compromises system performance, limits the number of memory devices, and complicates
`
`their connections.
`
`[0008] In some conventional memory systems, the memory controllers include leveling
`
`mechanisms for write and/or read operations to compensate for unbalanced wire lengths
`
`and memory device loading on the memory module. As memory operating speed and
`
`memory density continue to increase, however, such leveling mechanisms are also
`
`insufficient to insure proper timing of the control and/or data signals received and/or
`
`2
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 5
`
`

`

`transmitted by the memory modules.
`
`DESCRIPTION OF EMBODIMENTS
`
`[0009] A memory module according to one embodiment includes memory devices
`
`organized in groups, a module control device, and buffer circuits. Command signals,
`
`including one or more read/write commands, control/address (C/A) signals and a system
`
`clock signal from a memory controller are received by the module control device, which
`
`generates module command signals and module control signals in response to the
`
`command signals. The module command signals are transmitted by the module control
`
`device to the memory devices via module command signal lines, and the module control
`
`signals are transmitted by the module control device to the buffer circuits via module
`
`control signal lines.
`
`[0010] In one embodiment, each group of memory devices include at least two subgroups,
`
`each subgroup including at least one memory device. The buffer circuits are associated
`
`with respective groups of memory devices and are distributed across the memory module at
`
`positions corresponding to the respective groups of memory devices. During certain high
`
`speed operations, each module control signal arrives at different buffer circuits at different
`
`points of time across more than one clock cycle of the system clock. A buffer circuit
`
`associated with a respective group of memory devices is inserted into the data paths
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`between the respective group of memory devices and the memory controller. Thus, the
`
`memory controller does not have direct control of the memory devices. Instead, each buffer
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`circuit is configured to select a subgroup in the respective group of memory devices to
`
`communicate data with the memory controller in response to the module control signals.
`
`Thus, the memory module can have more ranks of memory devices than what is supported
`
`by the memory controller.
`
`[0011] In one embodiment, each buffer circuits includes metastability detection circuits to
`
`detect metastability condition in the module control signals and signal adjustment circuits
`
`to adjust the module control signals and/or a module clock signal to mitigate any
`
`3
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 6
`
`

`

`metastability condition in the module control signals.
`
`[0012] Further, in one embodiment, each buffer circuit includes signal alignment circuits
`
`that determine, during a write operation, a time interval between a time when one or more
`
`module control signals are received from the module control circuit and a time when a
`
`strobe or data signal is received from the memory controller. This time interval is used
`
`during a subsequent read operation to time transmission of read data to the memory
`
`controller, such that the read data follows an associated read command by a read latency
`
`value associated with the memory system.
`
`[0013] FIG. 1 shows a system 100 including a memory controller (MCH) 101 and one or
`
`more memory modules 110 coupled to the MCH by a memory bus 105, according to one
`
`embodiment. As shown, the memory bus includes command signal lines 120 and groups of
`
`system data/strobe signal lines 130. Also as shown, each memory module 110 has a
`
`plurality of memory devices 112 organized in a plurality of ranks 114. Each memory
`
`module 110 further includes a module control circuit (module controller or module control
`
`device) 116 coupled to the MCH 101 via the command signal lines 120, and a plurality of
`
`buffer circuits or isolation devices 118 coupled to the MCH 101 via respective groups of
`
`system data/strobe signal lines 130. In one embodiment, the memory devices 112, the
`
`module control circuit 116 and the isolation devices 118 can be mounted on a same side or
`
`different sides of a printed circuit board (module board) 119.
`
`[0014] In the context of the present description, a rank refers to one or more memory
`
`devices that are controlled by a common set of address/control (C/A) signals. The number
`
`of ranks of memory devices in a memory module 110 may vary. For example, as shown,
`
`each memory module 110 may include four ranks of memory devices 112. In another
`
`embodiment, the memory module 110 may include 2 ranks of memory devices. In yet
`
`another embodiment, the memory module may include six or more ranks of memory
`
`devices 112.
`
`[0015] In the context of the present description, a memory controller refers to any device
`
`4
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 7
`
`

`

`capable of sending instructions or commands, or otherwise controlling the memory devices
`
`112. Additionally, in the context of the present description, a memory bus refers to any
`
`component, connection, or groups of components and/or connections, used to provide
`
`electrical communication between a memory module and a memory controller. For
`
`example, in various embodiments, the memory bus 105 may include printed circuit board
`
`(PCB) transmission lines, module connectors, component packages, sockets, and/or any
`
`other components or connections that provide connections for signal transmission.
`
`[0016] Furthermore, the memory devices 112 may include any type of memory devices.
`
`For example, in one embodiment, the memory devices 112 may include dynamic random
`
`access memory (DRAM) devices. Additionally, in one embodiment, each memory module
`
`110 may include a dual in-line memory module (DTMM).
`
`[0017] Referring to FIG. 2, which illustrates one memory module 110 according to an
`
`embodiment, the module control device 116 receives system command signals including
`
`control/address (C/A) signals and a system clock MCK from the MCH 101 via signal lines
`
`120 and generates module command signals and module control signals based on system
`
`command signals. The module control device 116 also generates a module clock signal CK
`
`in response to the system clock signal MCK. The MCK signal may include a pair of
`
`complementary clock signals, MCK and MCK , and the module clock signal may include
`
`a pair of complementary clock signals CK and CK .
`
`[0018] Examples of the system C/A signals include, but are not limited to, Chip Select (or
`
`/CS) signal, which is used to select a rank of memory devices to be accessed during a
`
`memory (read or write) operation; Row Address Select (or /RAS) signal, which is used
`
`mostly to latch a row address and to initiate a memory cycle; Column Address Select (or
`
`/CAS) signal, which is used mostly to latch a column address and to initiate a read or write
`
`operation; address signals, including bank address signals and row/column address signals,
`
`which are used to select a memory location on a memory device or chip; Write Enable (or
`
`/WE) signal, which is used to specify a read operation or a write operation, Output Enable
`
`5
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 8
`
`

`

`(or /OE) signal, which is used to prevent data from appearing at the output until needed
`
`during a read operation, and the system clock signal MCK.
`
`[0019] Examples of module command signals include, but are not limited to module /CS
`
`signals, which can be derived from the system /CS signals and one or more other system
`
`command signals, such as one or more bank address signals and/or one or more
`
`row/column address signals; a module /RAS signal, which can be, for example, a buffered
`
`version of the system /RAS signal; a module /CAS signal, which can be, for example, a
`
`buffered version of the system /CAS signal; module address signals, which can be, for
`
`example, buffered versions of some or all of the address signals; a module /WE signal,
`
`which can be, for example, a buffered version of the system /WE signal; a module /OE
`
`signal, which can be, for example a buffered version of the system /OE signal, and the
`
`module clock signal CK.
`
`[0020] Examples of module control signals include, but are not limited to a mode signal
`
`(MODE), which specifies a mode of operation (e.g., test mode or operating mode) for the
`
`isolation devices 118; one or more enable signals, which are used by an isolation device to
`
`select one or more subgroups of memory devices to communicate data with the memory
`
`controller; and one or more ODT signals, which are used by the isolation devices to set up
`
`on-die termination for the data/strobe signals. In one embodiment, the module control
`
`signals are transmitted to the isolation devices 118 via respective module control signal
`
`lines 230. Alternatively, the module signals can be packetized before being transmitted to
`
`the isolation devices 118 via the module signal lines and decoded/processed at the isolation
`
`devices.
`
`[0021] Module control device 116 transmits the module command signals to the memory
`
`devices 112 via module command signal lines 220. The memory devices 112 operate in
`
`response to the module command signals to receive write data or output read data as if the
`
`module command signals were from a memory controller. The module control device
`
`transmits the module control signals together with the module clock signal CK to the
`
`isolation devices 118 via module control signal lines 230. As shown in FIG. 2, at least
`
`6
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 9
`
`

`

`some of the memory devices in each rank share a same set of module command signal lines
`
`220, and at least some of the isolation devices 118 share a same set of module control
`
`signal lines 230.
`
`[0022] As shown n FIGS. 2A and 2B, each rank 114 includes N memory devices, where
`
`N is an integer larger than one. For example, a first rank includes memory devices M11, • • •
`
`Mil, Mi+1,1, • • •, MN, a second rank includes memory devices M12, • • •, Mi2, Mi+1,2, • • •, MN,2,
`
`and so on. In one embodiment, the memory devices 112 are also organized in groups or
`
`sets, with each group corresponding to a respective group of system data/strobe signal lines
`
`130 and including at least one memory device from each rank. For example, memory
`
`devices M11, M12, M13, and M14 form a first group of memory devices, memory devices Mil,
`
`Mil, Mi3, and Mi4 form an i th group of memory devices, and so on.
`
`[0023] As shown, the isolation devices 118 are associated with respective groups of
`
`memory devices and are coupled between respective groups of system data/strobe signal
`
`lines 130 and the respective groups of memory devices. For example, isolation device ID-1
`
`among the isolation devices 118 is associated with the first group of memory devices M11,
`
`M12, M13, and M14 and is coupled between the group of system data/strobe signal lines
`
`130-1 and the first group of memory devices, isolation devices ID-i among the isolation
`
`devices 118 is associated with the i th group of memory devices Mil, Mil, Mi3, and M i4 and is
`
`coupled between the group of system data/strobe signal lines 130-i and the i th group of
`
`memory devices, and so on.
`
`[0024] In one embodiment, each group or sets of memory devices are coupled to the
`
`associated isolation device 118 via a set of module data/strobe lines 210. Each group or set
`
`of memory devices is organized in subgroups or subsets, with each subgroup or subset
`
`including at least one memory device. The subgroups in a group of memory devices may
`
`be coupled to the associated isolation device 118 via a same set of module data/strobe lines
`
`210 (as shown in FIG. 2A) or via respective subsets of module data/strobe lines 210 (as
`
`shown in FIG. 2B). For example, as shown in FIG. 2B, in the first group of memory
`
`devices, memory devices M11 and/or M13 form a first subgroup, and memory devices M12
`
`7
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 10
`
`

`

`and/or M14 form a second subgroup; in the i th group of memory devices, memory devices
`
`Mil and/or Mi3 form a first subgroup, and memory devices M i2 and/or Mi4 form a second
`
`subgroup; and so on. The first subgroup of at least one memory device in each group of
`
`memory devices is coupled to the associated isolation device 118 via an associated first
`
`subset of module data/strobe lines YA, and the second subgroup of at least one memory
`
`device in each group of memory devices is coupled to the associated isolation device via an
`
`associated second subset of module data/strobe lines YB, as shown. For example, memory
`
`devices M11 and/or M13 form the first subgroup are/is coupled to the isolation device ID-1
`
`via the corresponding first subset of module data/strobe lines YA-1, and memory devices
`
`M12 and/or M14 form the second subgroup are/is coupled to the isolation device ID-1 via
`
`the corresponding second subset of module data/strobe lines YA-2.
`
`[0025] In one embodiment, the isolation devices 118 are added to the data paths between
`
`the MCH 101 and the memory module 110 and include data buffers between the MCH 101
`
`and the respective groups of memory devices. In one embodiment, each isolation device
`
`118 is configured to select a subgroup in the respective group of memory devices to
`
`communicate data with the MCH 101 in response to the module control signals, such that
`
`the memory module can include more ranks than what is supported by the MCH 101.
`
`Further, each isolation devices 118 is configured to isolate unselected subgroup(s) of
`
`memory devices from the MCH 101 during write operations, so that the MCH sees a load
`
`on each data line that is less than a load associated with the respective group of memory
`
`devices. In one embodiment, the MCH sees only a load associated with one memory device
`
`on each data/strobe signal line during write operations.
`
`[0026] In one embodiment, the isolation devices 118 are distributed across the memory
`
`module 110 or the module board 119 in positions corresponding to the respective groups of
`
`memory devices. For example, isolation device 1D-1 is disposed in a first position
`
`corresponding to the first group of memory devices M11, M12, M13, and M14, and isolation
`
`device ID-i is disposed in an i th position separate from the first position and corresponding
`
`to the i1' group of memory devices Mu, Mi2, Mi3, and Mi4. In one embodiment, the first
`
`position is between the first group of memory devices and an edge 201 of the module board
`
`8
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 11
`
`

`

`119 where connections (not shown) to the data/strobe signal lines 130 are placed, and i th
`
`position is between the i th group of memory devices and the edge 201 of the module board
`
`119. In one embodiment, the isolation devices 118 are distributed along the edge 201 of the
`
`memory module 110. In one embodiment, each isolation device 118 is a separate integrated
`
`circuit device packaged either by itself or together with at least some of the respective
`
`group of memory devices. In one embodiment, the module data/strobe signal lines 210, the
`
`module command signal lines 220, and the module control signal lines 230 include signal
`
`traces formed on and/or in the module board 119.
`
`[0027] As an option, memory module 110 may further include a serial-presence detect
`
`(SPD) device 240, which may include electrically erasable programmable read-only
`
`memory (EEPROM) for storing data that characterize various attributes of the memory
`
`module 110. Examples of such data include a number of row addresses, a number of
`
`column addresses, a data width of the memory devices, a number of ranks on the memory
`
`module 110, a memory density per rank, a number of memory device on the memory
`
`module 110, and a memory density per memory device, etc. A basic input/output system
`
`(BIOS) of system 100 can be informed of these attributes of the memory module 110 by
`
`reading from the SPD 240 and can use such data to configure the MCH 101 properly for
`
`maximum reliability and performance.
`
`[0028] Thus, in the memory module 110, command signals are received and buffered by
`
`the module control circuit 116, so that the MCH sees only the module control circuit 116 as
`
`far as the command signals are concerned. Write data and strobe signals from the controller
`
`are received and buffered by the isolation devices 118 before being transmitted to the
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`memory devices 112 by the isolation devices 118. On the other hand, read data and strobe
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`signals from the memory devices are received and buffered by the isolation devices before
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`being transmitted to the MCH via the system data/strobe signal lines 130. Thus, MCH 101
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`does not directly operate or control the memory devices 112. As far as data/strobe signals
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`are concerned, the MCH 101 mainly sees the isolation devices 118, and the system 100
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`depends on the isolation devices 118 to properly time the transmission of the read data and
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`strobe signals to the MCH 101.
`
`9
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 12
`
`

`

`[0029] In one embodiment, operation of the isolation devices are controlled by the
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`module control signals from the module control circuit 116, which generates the module
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`control signals according to the command signals received from the MCH. Thus, the
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`module control signals need to be properly received by the isolation devices 118 to insure
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`their proper operation. In one embodiment, the module control signals are transmitted
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`together with the module clock signal CK, which is also generated by the module control
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`circuit 116 based on the system clock signal MCK. The isolation circuits 118 buffers the
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`module clock signal, which is used to time the sampling of the module control signals.
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`Since the isolation devices 118 are distributed across the memory module, the module
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`control signal lines 230 can stretch across the memory module 110, over a distance of
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`several centimeters. As the module control signals travel over such a distance, they can
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`become misaligned with the module clock signal, resulting in metastability in the received
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`module control signals. Therefore, in one embodiment, the isolation circuits 118 includes
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`metastability detection circuits to detect metastability condition in the module control
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`signals and signal adjustment circuits to adjust the module control signals and/or the
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`module clock signal to mitigate any metastability condition in the module control signals,
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`as explained in further detail below.
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`[0030] Because the isolation devices 118 are distributed across the memory module 110,
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`during high speed operations, it may take more than one clock cycle time of the system
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`clock MCK for the module control signals to travel along the module control signals lines
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`230 from the module control device 116 to the farthest positioned isolation devices 118,
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`such as isolation device ID-1 and isolation device ID-(n-1) in the exemplary configuration
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`shown in FIG. 2. In other words, a same set of module control signals may reach different
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`isolation devices 118 at different times across more than one clock cycle of the system
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`clock. For example, when the clock frequency of the system clock is higher than 800 MHz,
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`the clock cycle time is less than about 1.2 ns. With a signal travel speed of about 70ps per
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`centimeter of signal line, a module control signal would travel about 15 cm during one
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`clock cycle. When the clock frequency increases to 1600 MHz, a module control signal
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`would travel less than 8 cm during one clock cycle. Thus, a module control signal line can
`
`10
`
`Micron Technology Inc. et al.
`Ex. 1025, p. 13
`
`

`

`have multiple module control signals on the line at the same time, i.e., before one module
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`control signal reaches an end of the signal line, another module control signal appear on the
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`signal line.
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`[0031] With the isolation devices 118 receiving module control signals at different times
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`across more than one clock cycle, the module control signals alone are not sufficient to
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`time the transmission of read data signals to the MCH 101 from the isolation devices 118.
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`In one embodiment, each isolation devices includes signal alignment circuits that determine,
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`during a write operation, a time interval between a time when one or more module control
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`signals are received from the module control circuit 116 and a time when a write strobe or
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`write data signal is received from the MCH 101. This time interval is used during a
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`subsequent read operation to time the transmission of read data to the MCH 101, such that
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`the read data follows a read command by a read latency value associated with